CN1508859A - Integrated circuit testing device - Google Patents
Integrated circuit testing device Download PDFInfo
- Publication number
- CN1508859A CN1508859A CNA021571597A CN02157159A CN1508859A CN 1508859 A CN1508859 A CN 1508859A CN A021571597 A CNA021571597 A CN A021571597A CN 02157159 A CN02157159 A CN 02157159A CN 1508859 A CN1508859 A CN 1508859A
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- China
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- integrated circuit
- arrangement
- elastic caoutchouc
- testing
- pressing plate
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The testing device comprises an elastic rubber and a fixing device. The elastic rubber comprises multiple conducting holes and an insulation zone for isolating the said multiple conducting holes. The fixing device comprises a pressure plate and a fixed leg for locking the pressure plate to the elastic rubber so that pins of IC are connected to the conduction region tightly. The elastic rubber in the testing device can include an insulation zone and multiple conduction regions exposed out of surface of the elastic rubber. The invention is suitable to packed IC in small outline type particularly.
Description
Invention field
The present invention relates to a kind of testing apparatus of integrated circuit, especially relate to a kind of test runners of integrated circuit.
Background technology
Existing plane formula, high pin manifold become the packaged type of circuit, mainly cooperate the mount structure of different shape based on the rectangle plane encapsulation, and this packaged type can be with the tight adjacent space that is distributed in planar package four limits of pin.Yet even the spacing of pin is very little, the number of pins of this packaged type still can be subject to the limited edge length of this planar package.
For dealing with the demand of high number of pins, the packaged type of ball grid array is widely adopted.This mode is by electronic contact being distributed in the bottom of whole encapsulation, overcoming the restriction that the pin insufficient space is produced on the edge in the rectangle plane encapsulation.Compared to the rectangle plane packaged type, when the BGA Package mode is established more multiple-contact on limited area, can make the space between contact bigger; In addition, because the contact of BGA Package mode is a soldered ball, help it is welded on the testing circuit board, so the BGA Package mode has become the general packaged type of high number of pins chip.
Ball grid array integrated circuit or rectangle plane encapsulated integrated circuit need a runners that cooperates its pin positions when testing.For example: Fig. 1 is the profile of the test runners 10 of an existing ball grid array integrated circuit, it can make the soldered ball 22 of ball grid array integrated circuit drop in the through hole 14 by a lever (not being shown among Fig. 1) application of force is passed flat board 16 to increase through hole 14 to the right.After stopping the application of force, dull and stereotyped 16 will be by a spring (not being shown among Fig. 1) pushed home left, and mount 12 then descends soldered ball 22 roof pressures and enters in the through hole 14, thus fixing ball grid array integrated circuit.
Yet this existing integrated circuits testing apparatus has following shortcoming:
1. because each soldered ball of ball grid array integrated circuit is subjected to the roof pressure direction of mount is same direction, the opposite side of soldered ball then roof pressure at the through hole edge.If the roof pressure position is inconsistent, the soldered ball meeting unbalance stress of then whole ball grid array integrated circuit easily causes the soldered ball pin of integrated circuit to damage.
2. because mount is that roof pressure contact with soldered ball, roof pressure point is subject to damage under use for a long time, and cost that must both expensive is bought new runners once more.
3. at the integrated circuit of different packaged types or different size, again the cost of both expensive and time, customized especially one cooperates the runners of the pin position of integrated circuit.
Because existing arrangement for testing integrated circuit has above-mentioned shortcoming, can't meet the need of market, and therefore has and need further be improved.
Summary of the invention
Main purpose of the present invention is the testing apparatus that provides a kind of integrated circuit for addressing the deficiencies of the prior art, and it is specially adapted to the test of surface attaching type integrated circuit.
The invention provides a kind of arrangement for testing integrated circuit, it comprises an elastic caoutchouc and a fixture.This elastic caoutchouc comprises the insulation layer that a plurality of conductive holes and are used for isolated these a plurality of conductive holes.This fixture comprises a pressing plate and a fixed leg, and this fixed leg is used for this pressing plate is locked to this elastic caoutchouc, makes the pin of this integrated circuit closely be connected electrically in this conduction region.
The elastic caoutchouc of arrangement for testing integrated circuit of the present invention also can comprise an insulation layer and a plurality of conduction region that exposes to this elastic caoutchouc surface, and it is specially adapted to low profile encapsulation (Small OutlinePackage) type integrated circuit.
Compared to prior art, therefore arrangement for testing integrated circuit of the present invention has following advantage owing to adopt the elastic caoutchouc with conduction region to be electrically connected the pin of integrated circuit and the pad of circuit board:
1. owing to do not need customized especially or buy special runners, thus cost of manufacture and time be minimized.
2. because the cutting property of elastic caoutchouc applicable to integrated circuit dissimilar, size, has diversified advantage.
3. owing to need not weld, therefore use easily, and have the function of avoiding pin impaired.
Description of drawings
The present invention will describe according to accompanying drawing, wherein:
Fig. 1 is the schematic diagram of existing arrangement for testing integrated circuit;
Fig. 2 is the vertical view that the present invention is applied to the ball grid array type integrated circuit;
Fig. 3 is the front view that the present invention is applied to the ball grid array type integrated circuit;
Fig. 4 is the stereogram that the present invention is applied to the ball grid array type integrated circuit;
Fig. 5 is the vertical view that the present invention is applied to low profile encapsulation type integrated circuit;
Fig. 6 is the front view that the present invention is applied to low profile encapsulation type integrated circuit; And
Fig. 7 is the partial enlarged drawing of Fig. 6.
Among the figure:
10 ball grid array arrangement for testing integrated circuit
12 mounts
14 through holes
16 flat boards
22 soldered balls
40,60 arrangement for testing integrated circuit
41,61 testing circuit boards
42,62 integrated circuits
44,64 elastic caoutchoucs
46,66 pressing plates
48,68 springs
50,70 fixed legs
51,71 fixtures
52 soldered balls
72 pins
54,74 insulation layers
56 conductive holes
58,78 pads
76 conduction regions
Embodiment
Fig. 2 is the vertical view that arrangement for testing integrated circuit of the present invention is applied to the ball grid array type integrated circuit, and Fig. 3 is its front view.Arrangement for testing integrated circuit 40 of the present invention comprises a testing circuit board 41, an elastic caoutchouc 44 and a fixture 51.Fixture 51 comprises a pressing plate 46, a fixed leg 50 and a spring 48.Flexibly adjust pressing plate 46 by fixed leg 50 and spring 48 and lock to this testing circuit board 41, this pressing plate 46 is pressed to elastic caoutchouc 44 with an integrated circuit 42 to be measured.
Fig. 4 is the stereogram that arrangement for testing integrated circuit of the present invention is applied to the ball grid array integrated circuit, and this elastic caoutchouc 44 comprises a plurality of cylindric conductive holes 56 and an insulation layer 54, and this insulation layer 54 is used for isolated these a plurality of conductive holes 56.When this pressing plate 46 will this integrated circuit to be measured 42 be pressed to this elastic caoutchouc 44, the soldered ball 52 of integrated circuit 42 closely was electrically connected on the conductive hole 56 of this elastic caoutchouc 44.And testing circuit board 41 corresponding pads 58 also closely are electrically connected to this conduction region 56.Owing in the manufacture process of rubber or plastics, add carbon dust or metal powder, can improve its conductivity and make it become conductive material, therefore the formation method of elastic caoutchouc 44 of the present invention can be by in making the elastomeric material process, add carbon dust in the presumptive area that will form conductive hole 56, make this presumptive area become conductive material.
In the time will carrying out the test of integrated circuit 42, earlier fixture 51 is unclamped, again the pin 52 of integrated circuit 42 is contacted slightly the conductive hole 56 of this elastic caoutchouc 44.By fixed leg 50 pressing plate 46 is locked to this testing circuit board 41 then, this pressing plate 46 is then pressed to elastic caoutchouc 44 with integrated circuit 42, the feasible soldered ball 52 of this integrated circuit at least closely is electrically connected on the conductive hole 56 of elastic caoutchouc 44, and the pad 58 of testing circuit board 41 also closely is electrically connected on conductive hole 56 to form electric pathway.Because the elasticity that the spring 48 of elastic caoutchouc 44 and fixture 51 is provided, the soldered ball 52 of this integrated circuit 42 is closely to be electrically connected on conductive hole 56 with a specific pressure, and can not make soldered ball 52 impaired, can avoid the damage of integrated circuit 42.
Fig. 5 is the vertical view that the present invention is applied to low profile encapsulation type integrated circuit, and Fig. 6 is its front view, and Fig. 7 is the partial enlarged drawing of Fig. 6.As Fig. 5 and shown in Figure 6, arrangement for testing integrated circuit 60 of the present invention comprises a testing circuit board 61, two elastic caoutchoucs 64 and fixtures 71.This fixture 71 comprises a pressing plate 66, a fixed leg 70 and a spring 68.By this fixed leg 70 pressing plate 66 is locked to testing circuit board 61, this pressing plate 66 is pressed to elastic caoutchouc 64 with an integrated circuit 62 to be measured, make the pin 72 of integrated circuit 62 closely be electrically connected on conduction region 76, spring 68 is then in order to flexibly to adjust the pressure of pressing plate 66.As shown in Figure 7, elastic caoutchouc 64 comprises a plurality of strip conduction regions 76 and a plurality of insulation layer 74, and insulation layer 74 isolated conduction regions 76, and testing circuit board 61 has a pad 78.
In the time will carrying out the test of integrated circuit 62, earlier fixture 71 is unclamped, again integrated circuit 62 is placed the precalculated position (pin 72 that is integrated circuit 62 can contact with the conduction region 76 of elastic caoutchouc 64) of elastic caoutchouc 64, by fixed leg 70 pressing plate 66 is locked to testing circuit board 71 then, pressing plate 66 is then pressed to elastic caoutchouc 64 with integrated circuit 62, make conduction region 66 that the pin 72 of at least one integrated circuit closely is electrically connected on elastic caoutchouc 64 (in the present embodiment, pin 72 is electrically connected on three conduction regions 66, as shown in Figure 7), and the pad 78 of testing circuit board 71 also closely be electrically connected on conduction region 66 to form electric pathway.
Because the elasticity that spring provided of elastic caoutchouc and fixture, the pin of integrated circuit is closely to be electrically connected on conduction region with a specified pressure, and do not need pin is welded on the testing circuit board, can avoid integrated circuit to damage, testing apparatus is reusable simultaneously.In addition, because the cutting property of elastic caoutchouc, only need not need again customized plasticizing mould the product specification variation can significantly can be reduced production costs producing after make by cutting off.Moreover, when the present invention is used to research and develop, can allow research staff's according to specific time and site be its product or integrated circuit part to be tested, with scissors or blade elastic caoutchouc is cut off and can use, significantly promote the convenience of using.Because of not needing again the customized runners of spended time and cost, also reduce the time and the cost of research and development simultaneously.
Compared to prior art, therefore arrangement for testing integrated circuit of the present invention has following advantage owing to adopt the elastic caoutchouc with conduction region to be electrically connected the pin of integrated circuit and the pad of circuit board:
1. owing to do not need customized especially or buy special runners, thus cost of manufacture and time be minimized.
2. because the cutting property of elastic caoutchouc applicable to integrated circuit dissimilar, size, has diversified advantage.
3. owing to need not weld, therefore use easily and, have the function of avoiding pin impaired.
The technology of the present invention content and technical characterstic disclose as above, still may be based on teaching of the present invention and announcement and do all replacement and modifications that does not deviate from spirit of the present invention yet be familiar with this technology personage.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by present patent application claims scope.
Claims (9)
1. arrangement for testing integrated circuit comprises:
One elastic caoutchouc, it comprises the insulation layer that a plurality of conductive holes and are used for isolated these a plurality of conductive holes; And
One fixture in order to described integrated circuit is fixed on the described elastic caoutchouc, causes this ic pin can be electrically connected on described conductive hole.
2. arrangement for testing integrated circuit according to claim 1 is characterized in that described fixture comprises:
One pressing plate; And
One fixed leg is used for described pressing plate is locked to this elastic caoutchouc, makes described ic pin closely be electrically connected on described conductive hole.
3. arrangement for testing integrated circuit according to claim 2 is characterized in that described fixture also comprises a spring, in order to flexibly to adjust the pressure of described pressing plate.
4. arrangement for testing integrated circuit according to claim 1 is characterized in that described integrated circuit is a BGA Package type integrated circuit.
5. arrangement for testing integrated circuit comprises:
One elastic caoutchouc comprises an insulation layer and a plurality of conduction region that exposes to described elastic caoutchouc surface; And
One fixture in order to described integrated circuit is fixed on the described elastic caoutchouc, causes described ic pin can be electrically connected on described conduction region.
6. arrangement for testing integrated circuit according to claim 5 is characterized in that described conduction region is strip.
7. arrangement for testing integrated circuit according to claim 5 is characterized in that described integrated circuit is a low profile encapsulation type integrated circuit.
8. arrangement for testing integrated circuit according to claim 5 is characterized in that described fixture comprises:
One pressing plate; And
One fixed leg is used for described pressing plate is locked to described elastic caoutchouc, makes described ic pin closely be electrically connected on described conduction region.
9. arrangement for testing integrated circuit according to claim 8 is characterized in that fixture also comprises a spring, in order to flexibly to adjust the pressure of described pressing plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021571597A CN1508859A (en) | 2002-12-17 | 2002-12-17 | Integrated circuit testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021571597A CN1508859A (en) | 2002-12-17 | 2002-12-17 | Integrated circuit testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1508859A true CN1508859A (en) | 2004-06-30 |
Family
ID=34236505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021571597A Pending CN1508859A (en) | 2002-12-17 | 2002-12-17 | Integrated circuit testing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1508859A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231322B (en) * | 2007-02-09 | 2011-01-26 | 段超毅 | Test connection method for integrated circuit open circuit/ short-circuit |
| CN104616574A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | FPGA (field programmable gate array) removable high-speed operation verification development board |
| CN107807317A (en) * | 2016-08-31 | 2018-03-16 | 科大国盾量子技术股份有限公司 | A kind of electronic component test device |
-
2002
- 2002-12-17 CN CNA021571597A patent/CN1508859A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231322B (en) * | 2007-02-09 | 2011-01-26 | 段超毅 | Test connection method for integrated circuit open circuit/ short-circuit |
| CN104616574A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | FPGA (field programmable gate array) removable high-speed operation verification development board |
| CN104616574B (en) * | 2015-01-28 | 2017-11-10 | 山东华翼微电子技术股份有限公司 | A kind of FPGA is dismantled and assembled and the checking development board of high-speed cruising |
| CN107807317A (en) * | 2016-08-31 | 2018-03-16 | 科大国盾量子技术股份有限公司 | A kind of electronic component test device |
| CN107807317B (en) * | 2016-08-31 | 2024-05-28 | 科大国盾量子技术股份有限公司 | Electronic component testing device |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |