CN1508855A - Method for forming polycrystalline silicon layer and method for manufacturing polycrystalline silicon thin film transistor - Google Patents
Method for forming polycrystalline silicon layer and method for manufacturing polycrystalline silicon thin film transistor Download PDFInfo
- Publication number
- CN1508855A CN1508855A CNA021578095A CN02157809A CN1508855A CN 1508855 A CN1508855 A CN 1508855A CN A021578095 A CNA021578095 A CN A021578095A CN 02157809 A CN02157809 A CN 02157809A CN 1508855 A CN1508855 A CN 1508855A
- Authority
- CN
- China
- Prior art keywords
- layer
- amorphous silicon
- preliminary treatment
- forms
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The method includes following steps. First, an amorphous silicon layer is formed. Pretreatment is carried out for the said amorphous silicon layer to oxidize the surface of it to a silicon oxide layer, or azotize the surface to a silicon nitride layer. Then, the said amorphous silicon layer is crystallized to form a polycrystalline silicon layer. The thin film transistor made according to the invented method possesses lower threshold voltage and higher electron transfer.
Description
Technical field
The present invention relates to a kind of method that forms polysilicon layer, particularly form the method for polysilicon layer with big crystallite dimension.
Background technology
Because polycrystalline SiTFT (polysilicon thin film transistor; Poly-Si TFT) compared with amorphous silicon (amorphous silicon) TFT higher electron mobility, reaction time, higher resolution are faster arranged, therefore, at present multi-crystal TFT widespread usage in LCD to drive LCD.The manufacture method of multi-crystal TFT generally adopts low temperature polycrystalline silicon method (LTPS; Low temperaturepolysilicon).
Fig. 1 a to Fig. 1 c shows in traditional tft array technology, forms the process section of polysilicon layer with the LTPS method.With reference to la figure, on a substrate 100, form a barrier layer 120 and an amorphous silicon layer 200 in regular turn.
Then, make amorphous silicon layer 200 carry out crystallization, for example use quasi-molecule laser annealing (ELA; Excimer laser annealing) mode is carried out crystallization.With reference to Fig. 1 b, amorphous silicon layer 200 is by after the laser radiation, can melt and becomes amorphous silicon liquid 220.When 220 coolings of amorphous silicon liquid, on the interface on amorphous silicon liquid 220/ barrier layer 120, can produce nucleating center (nucleation center) (shown in the point among Fig. 1 b).So, amorphous silicon liquid 220 is understood according to the nucleating center crystallization gradually and is grown up to polysilicon layer 300, shown in Fig. 1 c.
As mentioned above, if amorphous silicon is not done the crystallization preliminary treatment, the crystallite dimension (grain size) of the last polysilicon layer that forms 300 is very little, and technology redundancy (process window) is very narrow.Carrying out subsequent technique, and after finishing TFT, the polysilicon layer of small particle diameter can cause the TFT of gained that higher Vt (threshold voltage is arranged; Threshold voltage) and less electron transfer rate (electron mobility).
Summary of the invention
Therefore, purpose of the present invention is for a kind of method that forms the polysilicon layer of big crystallite dimension that provides is provided.The TFT that uses the method to manufacture has lower Vt and higher electron transfer rate.
For realizing purpose of the present invention, the method that the present invention forms polysilicon layer may further comprise the steps.At first, form an amorphous silicon layer.Then, carry out preliminary treatment, make the surface oxidation of amorphous silicon layer become silicon oxide layer or be nitrided into silicon nitride layer for amorphous silicon layer.Then, make the amorphous silicon layer crystallization and form a polysilicon layer.
Description of drawings
Fig. 1 a to 1c shows in traditional tft array technology, forms the process section of polysilicon layer;
Fig. 2 a to 2d shows the process section that forms polysilicon layer according to the preferred embodiment of the present invention;
Fig. 3 a to 3f shows the process section of making top gate type (top-gate) polysilicon NTFT according to the preferred embodiment of the present invention;
Fig. 4 shows that the present invention has passed through the crystallization preliminary treatment and do not passed through the pretreated amorphous silicon layer of crystallization traditionally, after the irradiation of different laser energy density, and the grain size of gained polysilicon layer and the graph of a relation of laser energy density; And
Fig. 5 shows the Id-Vg figure of the NTFT of the inventive method and conventional method gained.
Description of reference numerals in the accompanying drawing is as follows:
100～substrate, 120～barrier layer
200～amorphous silicon layer, 220～amorphous silicon liquid
300～polysilicon layer, 10～substrate
12～barrier layer 20,22～amorphous silicon layer
24～silicon oxide layer or silicon nitride layer 32～amorphous silicon liquid
34～silicon nitride liquid 40,42～polysilicon layer
PR1, PR2～photoresist pattern 46～n type source/drain region
48～light-doped drain region (LDD), 50～gate dielectric
52～interlayer dielectric layer, 53～the first openings
56～passivation layer, 57～the second openings
60～grid layer, 62～source/drain electrode
70～pixel electrode
Embodiment
Fig. 2 a to 2d shows the process section that forms polysilicon layer according to the preferred embodiment of the present invention.With reference to Fig. 2 a, on a substrate 10, form a barrier layer 12 and an amorphous silicon layer 20 in regular turn.
Then,, amorphous silicon layer 20 is carried out preliminary treatment, make the surface oxidation of amorphous silicon layer 20 become silicon oxide layer 24 or be nitrided into silicon nitride layer 24 with reference to Fig. 2 b.The thickness of silicon oxide layer or silicon nitride layer 24 can be 1 dust to 50 dust, preferably can be 5 dust to 25 dusts.Amorphous silicon layer 20 originally is because of surface oxidation or nitrogenize less thick, with Reference numeral 22 expressions.
For the surface oxidation that makes amorphous silicon layer 20, crystallization preliminary treatment of the present invention can be used and contain oxygen plasma treatment amorphous silicon layer 20, and forms silicon oxide layer, contains oxygen plasma and can be N
2The O plasma.Perhaps, amorphous silicon layer 20 can be immersed in and contain in the oxygen solution, and form silicon oxide layer, contain oxygen solution and can be hydrogen peroxide (H
2O
2) or Ozone Water (O
3Water).Use the UV light irradiation also can form oxide layer.For example, available UV lamp is to shine amorphous silicon surfaces under the condition of medium at air, and forms silicon oxide layer.Perhaps, with boiler tube (furnace) or stove (oven) baking amorphous silicon surfaces, and form silicon oxide layer.
For making amorphous silicon layer 20 surfaces nitrided, crystallization preliminary treatment of the present invention can be used and contain nitrogen plasma treatment amorphous silicon layer 20, and forms silicon nitride layer, contains nitrogen plasma and can be N
2Plasma or NH
3Plasma.Perhaps, amorphous silicon layer 20 can be immersed in and contain in the nitrogen solution, and form silicon nitride layer.Perhaps, with boiler tube (furnace) or stove (oven) baking amorphous silicon surfaces, and form silicon nitride layer.
For convenience of description, below to change into silicon nitride layer 24 with the surface nitrogen of amorphous silicon layer be the example explanation.Then, make amorphous silicon layer 22 crystallizations.Can use many conventional methods to carry out crystallization, comprise and carry out quasi-molecule laser annealing (ELA at low temperatures; Excimer laser annealing), at high temperature carry out solid-phase crystallization (SPC; Solid phase crystallization), discontinuous crystal grain flop-in method (CGG; Continuous graingrowth), crystallization inducing metal method (MIC; Metal induced crystallization), metal induced lateral crystallization method (MILC; Metal induced lateral crystallization) and continuous transverse freezing method (SLS; Sequential lateral solidification) etc.With reference to Fig. 2 c, amorphous silicon layer 22 is by after the laser radiation, can melt and becomes amorphous silicon liquid 32.When cooling, on the interface on amorphous silicon liquid 32/ barrier layer 12, and on the interface of amorphous silicon liquid 32/ silicon nitride solid 34, can produce nucleating center (shown in the point among Fig. 2 c).So, amorphous silicon liquid 32 is understood according to the nucleating center crystallization gradually and is grown up to polysilicon layer 40, shown in Fig. 2 d.
As mentioned above, amorphous silicon layer through the crystallization preliminary treatment, does not have many one decks silicon nitride layer in the conventional method, and therefore, the time of crystallization is shorter.Review method of the present invention and since amorphous silicon layer before crystallization through preliminary treatment and how long one deck silicon nitride layer, silicon nitride layer can make the time lengthening of crystallization, thereby obtains bigger crystallite dimension.Therefore, the crystallite dimension of the formed polysilicon layer 40 of the present invention is bigger, and technology redundancy (process window) broad.
Fig. 3 a to 3f shows the process section of making top gate type (top-gate) polysilicon NTFT according to the preferred embodiment of the present invention.
At first, the method according to above-mentioned Fig. 2 a to 2d forms a barrier layer 12 and an amorphous silicon layer (not shown) in regular turn on a substrate 10.Then, carry out preliminary treatment, make the surface nitrogen of amorphous silicon layer change into silicon nitride layer, carry out crystallization again, and form a polysilicon layer (not shown) for amorphous silicon layer.Then, the polysilicon layer composition is formed polysilicon layer 42, shown in Fig. 3 a.Substrate 10 can be transparent substrates, for example glass or plastics.Barrier layer 12 can be silicon nitride or silica, perhaps, can comprise two-layer: the combination of silicon nitride layer and silicon oxide layer.Amorphous silicon layer can use silane (silane; SiH
4) be reacting gas, with plasma auxiliary chemical vapor deposition method (PECVD; Plasma-enhanced chemical vapordeposition) or Low Pressure Chemical Vapor Deposition (LPCVD; Low pressure chemical vapordeposition) forms.
Then,, form photoresist pattern P RI, use photoresist pattern P R1 to be mask, with phosphorus polysilicon layer 42 is carried out severe and mix, and form n type source/drain region 46 with reference to Fig. 3 b.Then,, remove photoresist pattern P R1, form a gate dielectric 50, form photoresist pattern P R2 again with reference to Fig. 3 c.Use photoresist pattern P R2 to be mask, polysilicon layer 42 is slightly mixed, and form light-doped drain region (LDD in the inboard of n type source/drain region 46 with phosphorus; Lightly-doped drain) 48.
Then,, remove photoresist pattern P R2, on gate dielectric 50, form a metal level (not shown), carry out photoetching and etching for metal level again, and on the correspondence position of polysilicon layer 42, form a grid layer 60 with reference to Fig. 3 d.So far, finish NTFT.
Then,, form an interlayer dielectric layer (interlayer dielectric) 52, in interlayer dielectric layer 52, form first opening 53 that arrives at source/drain region 46 again with reference to Fig. 3 e.Then, metal is inserted in first opening 53, and formation source/drain electrode 62.
Then,, form a passivation layer (passivation layer) 56, in passivation layer 56, form one second opening 57 of the drain electrode 62 that arrives at NTFT again with reference to Fig. 3 f.Then, with pixel electrode 70, ITO (inndium-tin oxide for example; Tin indium oxide) inserts in second opening 57, so far finish tft array technology, obtain the tft array shown in Fig. 3 f.This tft array can be combined with a preceding transparent substrates (as the colored filter substrate) and liquid crystal, and constitutes the TFT-LCD panel.
Fig. 4 shows that the present invention passes through the crystallization preliminary treatment and do not pass through the pretreated amorphous silicon layer of crystallization traditionally, after the irradiation of different laser energy density, and the grain size of the polysilicon layer of gained and the graph of a relation of laser energy density.Before laser radiation, the present invention is to use 0.078W/cm to the preliminary treatment of amorphous silicon layer
2N
2 O plasma treatment 10 seconds, 30 seconds, 50 seconds.Conventional method is not all carried out preliminary treatment to amorphous silicon layer, and as seen from Figure 4, the inventive method is (350-370mj/cm in very wide laser energy density scope
2), the crystallite dimension of polysilicon is all very big and very even, and this expression technology redundancy (process window) is very big.As for using conventional method, the crystallite dimension of polysilicon is all very little, and under different laser energy, the altering a great deal of crystallite dimension, and the technology redundancy is less.
Table 1 is the electrical performance data of the inventive method and conventional method gained NTFT.Fig. 5 then shows the Id-Vg figure of the NTFT of the inventive method and conventional method gained.The present invention is to use 0.078W/cm for the preliminary treatment of amorphous silicon layer
2N
2 O plasma treatment 50 seconds forms the silicon nitride layer of 20 dusts.Conventional method is not carried out preliminary treatment to amorphous silicon layer.
The electrical performance data of table 1 NTFT
| Conventional method | The inventive method is (with N 2O carries out preliminary treatment to amorphous silicon) | |
| ?Vt(V) | ????1.71 | ????0.91 |
| ?Ufe(cm 2/Vs) | ????61 | ????138 |
| ?SS(mV/decade) | ????0.5 | ????0.5 |
Vt: critical voltage (threshold voltage)
Ufe: field-effect mobility (field effect mobility)
SS: subcritical amplitude (subthreshold swing)
By table 1 and Fig. 5 as seen, use the TFT of crystallization preprocess method gained of the present invention to have good electrical properties, Vt is less, and electron mobility is higher.
Though the present invention with preferred embodiment openly as above; but it is not in order to restriction the present invention; under the situation that does not break away from the spirit and scope of the present invention; those skilled in the art can do change and retouching to it, so protection scope of the present invention should be as the criterion so that appended claim is determined.
Claims (30)
1. method that forms polysilicon layer, it comprises:
Form an amorphous silicon layer;
This amorphous silicon layer is carried out preliminary treatment, make the surface oxidation of this amorphous silicon layer become silicon oxide layer or be nitrided into silicon nitride layer; And
Make this amorphous silicon layer crystallization and form a polysilicon layer.
2. the method for formation polysilicon layer as claimed in claim 1, wherein this preliminary treatment makes the surface oxidation of amorphous silicon layer become silicon oxide layer.
3. the method for formation polysilicon layer as claimed in claim 1, wherein this preliminary treatment makes the surface nitrogen of amorphous silicon layer change into silicon nitride layer.
4. the method for formation polysilicon layer as claimed in claim 2, wherein this preliminary treatment is used and is contained this amorphous silicon layer of oxygen plasma treatment, and forms silicon oxide layer.
5. the method for formation polysilicon layer as claimed in claim 4, wherein this to contain oxygen plasma be N
2The O plasma.
6. the method for formation polysilicon layer as claimed in claim 2, wherein this preliminary treatment is immersed in this amorphous silicon layer and contains in the oxygen solution, and forms silicon oxide layer.
7. the method for formation polysilicon layer as claimed in claim 6, wherein this to contain oxygen solution be hydrogen peroxide (H
2O
2) or Ozone Water (O
3Water).
8. the method for formation polysilicon layer as claimed in claim 2, wherein this preliminary treatment is to shine amorphous silicon surfaces under the condition of medium at air with the UV lamp, and forms silicon oxide layer.
9. the method for formation polysilicon layer as claimed in claim 2, wherein this preliminary treatment is toasted amorphous silicon surfaces with boiler tube or stove, and forms silicon oxide layer.
10. the method for formation polysilicon layer as claimed in claim 3, wherein this preliminary treatment is used and is contained this amorphous silicon layer of nitrogen plasma treatment, and forms silicon nitride layer.
11. the method for formation polysilicon layer as claimed in claim 10, wherein this to contain nitrogen plasma be N
2Plasma or NH
3Plasma.
12. the method for formation polysilicon layer as claimed in claim 3, wherein this preliminary treatment is immersed in amorphous silicon layer and contains in the nitrogen solution, and forms silicon nitride layer.
13. the method for formation polysilicon layer as claimed in claim 3, wherein this preliminary treatment is toasted amorphous silicon surfaces with boiler tube or stove, and forms silicon nitride layer.
14. the method for formation polysilicon layer as claimed in claim 1, wherein the thickness of this silicon oxide layer or silicon nitride layer is 1 dust to 50 dust.
15. the method for formation polysilicon layer as claimed in claim 14, wherein the thickness of this silicon oxide layer or silicon nitride layer is 5 dust to 25 dusts.
16. a method of making polycrystalline SiTFT, it comprises:
On a substrate, form an amorphous silicon layer;
This amorphous silicon layer is carried out preliminary treatment, make the surface oxidation of this amorphous silicon layer become silicon oxide layer or be nitrided into silicon nitride layer;
Make this amorphous silicon layer crystallization and form a polysilicon layer, with as active layer; And
Form a gate dielectric, grid, source area and drain region.
17. the method for manufacturing polycrystalline SiTFT as claimed in claim 16, wherein this preliminary treatment makes the surface oxidation of amorphous silicon layer become silicon oxide layer.
18. the method for manufacturing polycrystalline SiTFT as claimed in claim 16, wherein this preliminary treatment makes the surface nitrogen of amorphous silicon layer change into silicon nitride layer.
19. the method for manufacturing polycrystalline SiTFT as claimed in claim 17, wherein this preliminary treatment is used and is contained this amorphous silicon layer of oxygen plasma treatment, and forms silicon oxide layer.
20. the method for manufacturing polycrystalline SiTFT as claimed in claim 19, wherein this to contain oxygen plasma be N
2The O plasma.
21. the method for manufacturing polycrystalline SiTFT as claimed in claim 17, wherein this preliminary treatment is immersed in this amorphous silicon layer and contains in the oxygen solution, and forms silicon oxide layer.
22. the method for manufacturing polycrystalline SiTFT as claimed in claim 21, wherein this to contain oxygen solution be hydrogen peroxide (H
2O
2) or Ozone Water (O
3Water).
23. the method for manufacturing polycrystalline SiTFT as claimed in claim 17, wherein this preliminary treatment is to shine amorphous silicon surfaces under the condition of medium at air with the UV lamp, and forms silicon oxide layer.
24. the method for manufacturing polycrystalline SiTFT as claimed in claim 17, wherein this preliminary treatment is toasted amorphous silicon surfaces with boiler tube or stove, and forms silicon oxide layer.
25. the method for manufacturing polycrystalline SiTFT as claimed in claim 18, wherein this preliminary treatment is used and is contained this amorphous silicon layer of nitrogen plasma treatment, and forms silicon nitride layer.
26. the method for manufacturing polycrystalline SiTFT as claimed in claim 25, wherein this to contain nitrogen plasma be N
2Plasma or NH
3Plasma.
27. the method for manufacturing polycrystalline SiTFT as claimed in claim 18, wherein this preliminary treatment is immersed in amorphous silicon layer and contains in the nitrogen solution, and forms silicon nitride layer.
28. the method for manufacturing polycrystalline SiTFT as claimed in claim 18, wherein this preliminary treatment is toasted amorphous silicon surfaces with boiler tube or stove, and forms silicon nitride layer.
29. the method for manufacturing polycrystalline SiTFT as claimed in claim 16, wherein the thickness of this silicon oxide layer or silicon nitride layer is 1 dust to 50 dust.
30. the method for manufacturing polycrystalline SiTFT as claimed in claim 29, wherein the thickness of this silicon oxide layer or silicon nitride layer is 5 dust to 25 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021578095A CN1314090C (en) | 2002-12-19 | 2002-12-19 | Method for forming polycrystalline silicon layer and method for manufacturing polycrystalline silicon thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021578095A CN1314090C (en) | 2002-12-19 | 2002-12-19 | Method for forming polycrystalline silicon layer and method for manufacturing polycrystalline silicon thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1508855A true CN1508855A (en) | 2004-06-30 |
| CN1314090C CN1314090C (en) | 2007-05-02 |
Family
ID=34236715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021578095A Expired - Lifetime CN1314090C (en) | 2002-12-19 | 2002-12-19 | Method for forming polycrystalline silicon layer and method for manufacturing polycrystalline silicon thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1314090C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872839A (en) * | 2010-05-31 | 2010-10-27 | 中国科学院上海微系统与信息技术研究所 | Phase change memory with low power consumption of stable threshold voltage and manufacturing method thereof |
| CN106062251A (en) * | 2014-02-26 | 2016-10-26 | 株式会社Eugene科技 | Method for forming polysilicon film |
| CN106571306A (en) * | 2016-10-27 | 2017-04-19 | 武汉华星光电技术有限公司 | Thin film transistor and manufacturing method thereof |
| CN115498071A (en) * | 2022-09-20 | 2022-12-20 | 中威新能源(成都)有限公司 | Preparation method of battery, battery and electronic product |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW406861U (en) * | 1994-07-28 | 2000-09-21 | Semiconductor Energy Lab | Laser processing system |
-
2002
- 2002-12-19 CN CNB021578095A patent/CN1314090C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872839A (en) * | 2010-05-31 | 2010-10-27 | 中国科学院上海微系统与信息技术研究所 | Phase change memory with low power consumption of stable threshold voltage and manufacturing method thereof |
| CN101872839B (en) * | 2010-05-31 | 2013-10-30 | 中国科学院上海微系统与信息技术研究所 | Phase change memory with low power consumption of stable threshold voltage and manufacturing method thereof |
| CN106062251A (en) * | 2014-02-26 | 2016-10-26 | 株式会社Eugene科技 | Method for forming polysilicon film |
| CN106062251B (en) * | 2014-02-26 | 2018-11-30 | 株式会社Eugene科技 | The forming method of polysilicon film |
| CN106571306A (en) * | 2016-10-27 | 2017-04-19 | 武汉华星光电技术有限公司 | Thin film transistor and manufacturing method thereof |
| CN115498071A (en) * | 2022-09-20 | 2022-12-20 | 中威新能源(成都)有限公司 | Preparation method of battery, battery and electronic product |
| CN115498071B (en) * | 2022-09-20 | 2024-05-14 | 通威太阳能（成都）有限公司 | Battery preparation method, battery and electronic product |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1314090C (en) | 2007-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8263421B2 (en) | Manufacturing method of semiconductor device | |
| US8435843B2 (en) | Treatment of gate dielectric for making high performance metal oxide and metal oxynitride thin film transistors | |
| WO2004079826A1 (en) | Method for manufacturing thin film transistor, display, and electronic device | |
| US7303981B2 (en) | Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same | |
| JP2012119691A (en) | Thin film transistor manufacturing method | |
| US20040119072A1 (en) | Method of forming a thin film transistor | |
| JP3122699B2 (en) | A method for manufacturing a thin film semiconductor device. | |
| US6869834B2 (en) | Method of forming a low temperature polysilicon thin film transistor | |
| EP1956656A2 (en) | Thin film transistor array panel and method for manufacturing the same | |
| CN1314090C (en) | Method for forming polycrystalline silicon layer and method for manufacturing polycrystalline silicon thin film transistor | |
| US20090200553A1 (en) | High temperature thin film transistor on soda lime glass | |
| JP2002299238A (en) | Polycrystalline semiconductor film-forming method and semiconductor device manufacturing method | |
| CN1285107C (en) | Method for manufacturing low-temperature polysilicon thin-film transistor | |
| JP3170533B2 (en) | Method for manufacturing thin film semiconductor device | |
| CN1265428C (en) | Method of manufacturing film transistor | |
| JP3361670B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2003173969A (en) | Semiconductor film, semiconductor device and method for manufacturing them | |
| CN1519888A (en) | Buffer layer capable of promoting electron mobility raising and thin film transistor containing the buffer layer | |
| CN1801467A (en) | Method for manufacturing thin-film transistor and polysilicon layer | |
| JP3462157B2 (en) | Method for manufacturing semiconductor device | |
| JP2009111302A (en) | Semiconductor device and its manufacturing method | |
| KR20040036761A (en) | Method of silicon deposition using of hdp-cvd | |
| CN1303658C (en) | Method for producing thin film transistor and its structure | |
| JP2898365B2 (en) | Method for manufacturing gate insulating film of insulated gate field effect transistor and gate insulating film of insulated gate field effect transistor manufactured by the manufacturing method | |
| JP2921816B2 (en) | Active matrix substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070502 |