CN1508550A - Signal processing device - Google Patents
Signal processing device Download PDFInfo
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- CN1508550A CN1508550A CNA02155076XA CN02155076A CN1508550A CN 1508550 A CN1508550 A CN 1508550A CN A02155076X A CNA02155076X A CN A02155076XA CN 02155076 A CN02155076 A CN 02155076A CN 1508550 A CN1508550 A CN 1508550A
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Abstract
The invention provides a signal processing device which uses low sampling cycle to sensing higher cycle signal. After the invention calculates the sampling cycle in a fixed time, uses A/D converter to sample the analog signal. The sampling cycle converter part should executes following process: maintains the set sampling cycle in a time, transfers the sampling cycle, when the sampling cycle reaches the biggest cycle, it returns to basic sampling cycle.
Description
(1) technical field
The invention relates to the invention of signal processing apparatus, more specifically be can not sensing about with the sampling of certain cycle the time than its higher cycle signal, can utilize a plurality of low-frequency combination cycle sensed signal treating apparatus at this moment.
(2) background technology
Be used in the systems such as household electrical appliance or industry machine, when signal Processing is carried out in certain input, calculate pairing output signal and send output signal arbitrarily after earlier input signal being converted to digital signal, therefore can carry out stable signal Processing.
Fig. 1 is an example with prior art of this formation.Existing digital signal treating apparatus is to comprise following parts: simulation/digital converter section (hereinafter to be referred as the A/D converter section) 10 that the analog input signal with certain cycle is sampled; Any digital input signal that obtains from A/D converter section 10 in order to make suitable output signal, and carries out arithmetic, the digital digital signal handling part of handling (DSP) 20 such as logic; When need simulate output, the digital signal of digital signal handling part 20 is converted to the number/analog-converted portion (hereinafter to be referred as the D/A converter section) 30 of simulating signal to input signal; And output has converted the simulation efferent 40 of simulating signal to.
Fig. 2 is the formation of above-mentioned prior art and the example of processing signals process.Reception has the signal of the signal source of certain cycle, shows measured value at A/D converter section 10 with certain sampling period T.Fig. 2 (a) and (b) be expression: when the cycle of signal source is Fi, sampling cycle is under the situation of Fi, is identified as 0 sometimes, is identified as certain value sometimes.The confidence level of the output of identification input signal that at this time can not be correct, so this moment in other words is not high.
In contrast, Fig. 2 (c) is the process that has reflected having A/D converter section 10 converted input signals that are equivalent to 4 times of input signals (being exactly Fi/4) sampling cycle.Usually on the digital signal treating apparatus for reflected input signal, sampling cycle is greater than 2 times of input signal cycle, this cycle is called Nyquist (calling Nyquist in the following text) cycle.In the requirement of the output of corresponding signal specific is to allow through the system that reflects after the adequate time or only differentiate within a certain period of time to have or not in the system of input signal, reception has the signal that the signal source of certain cycle is sent, then when A/D converter section 10 is with certain sampling period T sampling, the sampling cycle lower than the cycle Fi of signal source be can not be correct the identification input signal, therefore can not get the output signal that needs.
(3) summary of the invention
The present invention designs in order to solve the problem that above-mentioned prior art exists, and it is a kind of on the device that is having low sampling cycle that its purpose is to provide, and allows the signal processing apparatus of its sensing higher cycle signal.
Another object of the present invention is, the requirement that a kind of output in corresponding signal specific is provided is to allow through in the system that reflects after the adequate time, uses the signal processing apparatus that the digital signal treating apparatus of input signal being sampled than the low cycle of Nyquist cycle also can its signal of sensing.
Of the present invention have a purpose to be again, provide a kind of when having imported signal specific, only judge within a certain period of time to have or not in the system that imports signal specific, allow the signal processing apparatus that the digital signal treating apparatus that has the cycle lower than the cycle of input signal also can its signal of sensing.
For reaching above-mentioned purpose, signal processing apparatus of the present invention is characterized in comprising following parts: calculate the sampling period that changes according to some cycles and the sampling period converter section of output; For analog input signal, according to the sampling period of above-mentioned sampling period converter section input, the simulation of sampling/digital converter section.
Here, above-mentioned sampling period converter section is to carry out following processes repeatedly: keep the sampling period that has been provided with within a certain period of time, after having passed through above-mentioned certain hour, unit according to a certain size changes the above-mentioned sampling period, when the sampling period of above-mentioned setting has arrived maximum sampling period, return the process in basic sampling period.
Moreover above-mentioned sampling period converter section also can be carried out following processes repeatedly: keep the sampling period that has been provided with within a certain period of time, after having passed through above-mentioned certain hour, be converted to the process of optional value between basic sampling period and maximum sampling period the above-mentioned sampling period.
Moreover the sampling period of above-mentioned conversion should be longer than the cycle of input signal.
Constituting output signal of the present invention as mentioned above is the time marquis who is in special status, such as 1) pass through the system that reflects after the sufficient time in the output permission of corresponding signal specific, 2) only judge when having or not the system of input signal within a certain period of time, provide a kind of allow the device that has low sampling cycle can sensing than its cycle method of cycle signal more.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Fig. 1 is the structural representation of the signal processing apparatus of prior art.
Fig. 2 is the oscillogram of prior art signal processing apparatus identification signal.
Fig. 3 is the structural representation according to the signal processing part of signal processing apparatus of the present invention.
Fig. 4 is the identification signal oscillogram that the sampling cycle of the signal processing apparatus according to the present invention changes.
Fig. 5 is the output characteristics oscillogram to the input of signal processing apparatus of the present invention.
Fig. 6 is the process flow diagram of algorithm of the sampling period converter section of signal processing apparatus specific embodiment of the present invention.
Fig. 7 is the process flow diagram of algorithm of the sampling period converter section of another specific embodiment of signal processing apparatus of the present invention.
(5) embodiment
Fig. 3 is the structural representation according to the signal processing part of signal processing apparatus of the present invention.In Fig. 3, the structure position subscript identical with Fig. 1 existing structure identical reference symbol.
According to signal processing apparatus of the present invention be: analog input signal is had the A/D converter section 10 that certain cycle is sampled; Any digital input signal to obtaining from A/D converter section 10 carries out arithmetic in order to make suitable output signal, the digital digital signal handling part of handling 20 such as logic; When need simulate output, the digital signal of digital signal handling part 20 is converted to the D/A converter section 30 of simulating signal to input signal; And export on the existing structure of parts such as simulation efferent 40 composition that has converted simulating signal to, after the sensing special time also calculates the sampling period of changing according to special time, after adding the sampling period converter section 50 of A/D converter section 10 output signals again, allow A/D converter section 10 sample, can in specific system, use with this according to the sampling period of sampling period converter section 50 inputs.
Fig. 4 is the oscillogram of signal processing apparatus of the present invention according to the identification signal of sampling cycle variation.
In the prior art structure, when carrying out fixed sample for the cycle of input signal, can take place to be identified as 0 sometimes, sometimes be identified as the situation of certain value, the present invention is the spacing conversion cycle that continues with specific, though be the sampling cycle lower than input signal therefore but as shown in Figure 4,, but also can confirm the existence of input signal, again can be to allowing the suitable output signal of the slow efferent of reflection 40.
Below for an example that can be suitable for the system of signal processing apparatus of the present invention, such as receiving certain signal and showing the situation of this signal.As the display process efferent and when showing that it is big or small, can not suitably must show output signal fully to efferent 40 according to original method.But in the present invention as shown in Figure 5, though that the display process efferent is replied is slow slightly, output input signal that can be suitable.
Fig. 6 is the process flow diagram according to the algorithm of the sampling period converter section 40 of signal processing apparatus of the present invention.
At first, sampling period converter section 40 is set to the basic sampling period (TB) to the sampling period (T), and the maximum sampling period is set to TMAX, and the periodic change time outputs to A/D converter section 40 (S10) to the basic sampling period (TB) after being set to (TC).In view of the above, A/D converter section 40 is converted to digital signal to input signal according to the basic sampling period (TB).
Then, sampling period converter section 40 is carried out following action repeatedly: be maintained to till time of sampling period change time (TC) the prior appointment that arrives of above-mentioned setting S20 afterwards the sampling period of above-mentioned setting, when having arrived the time in conversion sampling period, judge whether to reach maximum sampling period (TMAX) S30, if when having arrived the maximum sampling period (TMAX), then turn back to (TB) S40 of basic sampling period, otherwise then make the sampling period (T) increase by 1 (S50) again, and turn back to the above-mentioned action of step continuation execution of S20.
Fig. 7 is the process flow diagram of algorithm of the sampling period converter section of another specific embodiment of signal processing apparatus according to the present invention.The stage identical with the process flow diagram of Fig. 6 marked identical stage symbol on this drawing.
The characteristics of this legend are, aforesaid in the certain hour of appointment in advance, kept the sampling period after, when having arrived the time in conversion sampling period, not carrying out a sampling period (T) has increased by 1 stage S50 (as shown in Figure 6), and carries out the stage S60 that comes the sampling period (T) with any sampled value of setting between basic sampling period (TB) and maximum sampling period (TMAX).
According to as mentioned above, the present invention has following effect.In the system that uses the sampling period transformation component, when output signal is in special status, such as 1) pass through the system that reflects after the sufficient time in the output permission of corresponding signal specific, 2) only judge when having or not the system of input signal within a certain period of time, the relative signal processing apparatus that the digital signal treating apparatus of the cycle that input signal is lower than Nyquist cycle also can its signal of sensing, also can the sensing input signal, allow efferent not be subjected to the restriction of time and make output signal fully with this.
Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (4)
1. a signal processing apparatus is characterized in that comprising with lower member: calculate the sampling period that changes according to some cycles and the sampling period converter section of output; For analog input signal, according to the sampling period of described sampling period converter section input, the simulation of sampling/digital converter section.
2. signal processing apparatus as claimed in claim 1, it is characterized in that described sampling period converter section is to carry out following process repeatedly: keep the sampling period that has been provided with within a certain period of time, after having passed through described certain hour, unit according to a certain size changes the described sampling period, when the sampling period of described setting has arrived maximum sampling period, return the process in basic sampling period.
3. signal processing apparatus as claimed in claim 1, it is characterized in that described sampling period converter section carries out following process repeatedly: keep the sampling period that has been provided with within a certain period of time, after having passed through described certain hour, be converted to the process of optional value between basic sampling period and maximum sampling period the described sampling period.
4. signal processing apparatus as claimed in claim 1 is characterized in that the sampling period of described conversion is longer than the cycle of input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02155076XA CN100365616C (en) | 2002-12-20 | 2002-12-20 | Signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02155076XA CN100365616C (en) | 2002-12-20 | 2002-12-20 | Signal processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1508550A true CN1508550A (en) | 2004-06-30 |
| CN100365616C CN100365616C (en) | 2008-01-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02155076XA Expired - Fee Related CN100365616C (en) | 2002-12-20 | 2002-12-20 | Signal processing device |
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Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4463320A (en) * | 1982-07-06 | 1984-07-31 | Rockwell International Corporation | Automatic gain control circuit |
| JPH05151794A (en) * | 1991-07-25 | 1993-06-18 | Asahi Kasei Micro Syst Kk | Sample-hold circuit |
| US5724396A (en) * | 1995-06-07 | 1998-03-03 | Discovision Associates | Signal processing system |
| JPH10188189A (en) * | 1996-12-26 | 1998-07-21 | Yamatake Honeywell Co Ltd | Transmitter |
| JPH11308530A (en) * | 1998-04-17 | 1999-11-05 | Nippon Avionics Co Ltd | Infrared ray image device |
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| CN100365616C (en) | 2008-01-30 |
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Granted publication date: 20080130 Termination date: 20100120 |