CN1507227A - Method of preventing formation of timing loop in synchronous network - Google Patents
Method of preventing formation of timing loop in synchronous network Download PDFInfo
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Abstract
The method of preventing formation of timing loop in synchronous network expands available sync state message protocol and increases mark field to sync clock reference source in sync network. Therefore, when some sync clock returns to the network element the clock is sent via one loop, latent timing loop may be identified easily. Based on the thought, complicated network is split into several son networks and timing loop among different son networks is then prevented by means of the clock reference source. The present invention can prevent the formation of timing loop caused by the switching of sync clock reference source in sync network effectively to ensure the accurate sync of the network elements in the sync network.
Description
Technical field
The present invention relates to network communications technology field, relate in particular to the method that prevents in a kind of Synchronization Network that timing loop from forming.
Background technology
Along with the development of the network communications technology, the digital network technology is also increasingly mature and be widely used.Digital network realizes that reliable transfer of data is accurately synchronous based between each network element, between each network element synchronously can so that the clock frequency control of each network element in predetermined range of tolerable variance, to avoid in the buffer of each network element producing overflowing and getting sky of information bit, cause the slip damage of digital stream, cause data to make mistakes.
For example, for SDH (Synchronous Digital Hierarchy) net, for the pointer adjustment that guarantees SDH equipment does not make SDH desynchronizer and interconnected PDH (Plesiochronous Digital hierarchy) equipment performance deterioration, cause and can't normally commence business, the SDH net must will be operated in the synchronous environment.And some service network equipment as the base station of GSM, need the SDH net to provide high accuracy clock for it, and this demand equally also requires the SDH net to work in the synchronous environment.
Synchronous exactly between each network element in order to guarantee in the SDH net, usually require all network element clocks can obtain the synchronised clock reference from two paths at least, when guaranteeing to break down in a certain path that is used for regularly, reconfigurablely obtain regularly from another standby timing path; The timing base distribution of SDH net is that the SDH network element clock of a large amount of lower grades of process carries out, for carrying out timing in the synchronization timing path that makes each network element can choose first water, present ITU-T G.781 standard recommendation adopts SSM (Synchronization Status Message) method to identify the quality of Synchronization Status Message, as shown in Figure 1, credit rating is clock signal (QL_PRC) G.811 from high to low, G.812 transit exchange's clock signal (QL_SSUA), G.812 end office's clock signal (QL_SSUB), G.813 synchronous equipment timing source signal (QL_SEC), should be as synchronous (QL_DNU).In SDH, this standard code belongs to the 5th to the 8th bit of the S1 byte of first STM-1 frame and represents Synchronization Status Message in STM-N (STM:Synchronous transfer mode, synchronous transfer mode) frame structure; In PDH, ITU-T also stipulates in the 4th to the 8th these 5 idle bits of PCM (Pulse Coding Modulation, pulse code modulation) time slot odd-numbered frame one as the Synchronization Status Message bit, and coding rule is identical with S1 byte among the SDH.Wherein, QL_DNU represents that this clock can not be used for synchronous refernce clocks, the synchronization clock mass that each network element of path in Synchronization Network for may form timing loop the time sends is labeled as QL_DNU, as oppositely just using this quality status stamp at synchronised clock reference source direction of transfer, when network element is selected timing source according to SSM, just can avoid the formation of timing loop like this.
For example; when the Synchronization Network operate as normal, as shown in Figure 2, each network element all is synchronized with PRC (master clock); after the synchronous path of PRC breaks down; then the quality status stamp with the clock of PRC synchronous path direction is QL_DNU, like this at each SDH network element with after G.812 from clock protection taking place and switching, as shown in Figure 3; each network element adopts new timing path; promptly, owing to the QL_DNU quality status stamp of opposite direction Synchronization Status Message, avoided the appearance of timing loop simultaneously from the timing path of clock.Therefore, after above-mentioned technology can realize the auto switching in timing reference source, avoid the appearance of timing loop to a certain extent.
Yet under comparatively complicated networking situation, above-mentioned technology can't be avoided the formation of timing loop.As shown in Figure 4, in the ring type structure Synchronization Network in the drawings, under the normal condition synchronised clock reference source of main BITS (the communication building is the composite supply system regularly) as whole looped network, arrow institute label direction is the clock direction of transfer among the figure, because the SSM among the figure is by counterclockwise transmitting, finally in the counterclockwise direction, the A network element will be received the SSM information that passes over from the B network element, and this SSM information is that the A network element sends in fact.When main BITS lost efficacy, the A network element will think that the SSM that comes that transmits from B can use, so network element A follows the tracks of the clock of B network element, but this moment network element B clock to remain with main BITS be the clock of synchronised clock reference source.Like this, finally caused the appearance of timing loop, and the clock that is equipped with BITS is not as the synchronised clock reference source of looped network.
The appearance of timing loop makes the clock between the part network element lock mutually, cause whole synchronizing network can't normally realize between each network element synchronously, certainly also just can't guarantee the operate as normal of each network element in the Synchronization Network, this is unallowed for the higher digital network of performance requirement.
Summary of the invention
The purpose of this invention is to provide the method that prevents in a kind of Synchronization Network that timing loop from forming,, improve and realize synchronous reliability in the Synchronization Network effectively to prevent the formation of timing loop in comparatively complicated Synchronization Network.
The object of the present invention is achieved like this: prevent the method that timing loop forms in a kind of Synchronization Network, it is characterized in that comprising:
A, define the timing reference input sign respectively for the synchronised clock reference source in the Synchronization Network, and in the timing reference input of each the network element configuration correspondence that has inserted synchronised clock reference source sign, each network element transmits with synchronous state information the timing reference input sign that self disposes when sending Synchronization Status Message in Synchronization Network then;
B, in Synchronization Network, carry out active and standby synchronised clock reference source when switching, each network element determines according to the timing reference input sign of transmitting with synchronous state information that receives and the credit rating of Synchronization Status Message whether this Synchronization Status Message is available, carries out synchronously to select correct synchronised clock reference source.
Described timing reference input sign is carried on S1 byte high 4 of the SDH net synchronization message that realizes based on SSM (Synchronization Status Message) agreement, and value be " 1～15 ", and is designated " 0 " with this and represents undefined this sign.
Described step a comprises:
A1, Synchronization Network is divided into a plurality of subnets, all comprises the active and standby synchronised clock reference source that inserts different network elements respectively in each subnet;
A2, for the active and standby synchronised clock reference source in each subnet defines the timing reference input sign respectively, and the network element that inserts for the active and standby synchronised clock reference source in each subnet disposes the timing reference input sign of the synchronised clock reference source correspondence that it inserted respectively;
When a3, each network element that inserts the synchronised clock reference source outwards send the Synchronization Status Message that is carrying self synchronised clock reference source, the timing reference input sign of self configuration is transmitted in Synchronization Network with this Synchronization Status Message.
Described subnet is the subnet that monocycle constitutes.
Described step b comprises:
B1, in Synchronization Network, carry out active and standby synchronised clock reference source when switching, insert each network element of synchronised clock reference source and judge whether the timing reference input sign of transmitting with synchronous state information that receives is the timing reference input sign of this network element configuration, if, execution in step b2, otherwise, execution in step b3:
B2, determine that this Synchronization Status Message is unavailable, and this network element transfers the clock hold mode to, and outwards to send credit rating be to be not useable for synchronous Synchronization Status Message;
If b3, whether available according to further definite this Synchronization Status Message of credit rating available, then utilizes this Synchronization Status Message to carry out synchronously, otherwise, abandon this Synchronization Status Message.
Described step b2 also comprises: it is after being not useable for synchronous Synchronization Status Message that the network element that inserts standby synchronised clock reference source receives the credit rating of sending, Synchronization Status Message is switched on the standby synchronised clock reference source, and outwards send the Synchronization Status Message that is carrying standby synchronised clock reference source synchronised clock, what transmit with synchronous state information is the timing reference input sign of standby synchronised clock reference source.
The main synchronised clock reference source that inserts when the subnet network element described in the step a1 or be equipped with the synchronised clock reference source be come from other subnets carry the Synchronization Status Message of synchronised clock the time, this method also comprises:
When this network element outwards sends Synchronization Status Message, if carry in the Synchronization Status Message that sends be other subnet transmission that this network element is connecting come synchronised clock information the time, need and to replace with the timing reference input sign that this network element disposes with the timing reference input sign that other subnet Synchronization Status Messages transmit other subnet that comes, be about to transmit in the synchronous subnet at this network element place with synchronous state information for the timing reference input sign of this network element configuration.
By technique scheme as can be seen; the present invention expands existing SSM agreement; be the synchronised clock reference source and increase identification field; this sign is used to indicate the source of synchronised clock; like this when a certain synchronised clock is got back to the network element that sends this synchronised clock through a loop; can discern this potential timing loop easily; therefore; the present invention can effectively prevent the formation of timing loop when the active and standby synchronised clock reference source of generation in the network switches; reaching good clock protection effect, solved the problem that existing in prior technology can't detect and prevent to form between many network elements timing loop.In addition, the present invention is also based on above-mentioned thought, and the networking of complexity is split into a plurality of subnets, and then prevents formation at timing loop between each subnet by the timing reference input sign.Therefore, realization of the present invention can avoid effectively that the switching because of the synchronised clock reference source generates timing loop in Synchronization Network, has improved synchronous reliability between each network element of Synchronization Network.
Description of drawings
Fig. 1 is the synchronization clock mass table of grading of ITUT regulation;
Fig. 2 is existing SDH net timing process schematic diagram A;
Fig. 3 is existing SDH net timing process schematic diagram B;
Fig. 4 is existing ring network timing process schematic diagram;
Fig. 5 is concrete implementing procedure figure of the present invention;
Fig. 6 is ring network timing process schematic diagram among the present invention;
Fig. 7 is the timing process schematic diagram in the complicated networking among the present invention.
Embodiment
Core of the present invention is by the SSM agreement solution existing in prior technology problem of expansion about Synchronization Status Message, promptly by use in the SDH frame structure with SSM high 4 bits together as timing reference input ID (sign), to identify the source of different synchronised clock reference sources, timing reference input ID will transmit in the SDH network together with Synchronization Status Message, the network element that sends this Synchronization Status Message like this can this potential timing loop of very simple identification when receiving this synchronised clock once more through a loop.Another function of the timing reference input ID that defines among the present invention is under complicated networking situation, complicated networking can be divided into the simple clock subnet that several shield mutually by timing reference input ID, to avoid the formation of timing loop effectively under complicated networking.
The specific embodiment of the present invention may further comprise the steps as shown in Figure 5:
Step 1: Synchronization Network is divided into a plurality of subnets, as the SDH net is divided into a plurality of subnets, each subnet comprises a plurality of network elements, comprise at least two synchronised clock reference sources again in each subnet simultaneously, each synchronised clock reference source inserts the different network elements in the subnet respectively, synchronised clock being passed to other network element in the subnet by the network element that inserts, with realize between each network element accurately synchronously;
Step 2: be each the synchronised clock reference source definition timing reference input ID in each subnet, the sign of distinguishing mutually as different synchronised clock reference sources, timing reference input ID is along with the SSM (Synchronization Status Message) that network element sends transmits in subnet together, and other network element transmits this synchronizing information.In the SDH net, use high 4 carrying timing reference input ID of the S1 byte of first STM frame, timing reference input ID value is 1～15, and is set to represent undefined timing reference input ID when clock reference source ID is 0;
Step 3: outwards send network element in the subnet of Synchronization Status Message when sending Synchronization Status Message, the timing reference input ID of the synchronised clock reference source definition that self inserts is sent with SSM;
If certain network element is the synchronous subnet at this network element place and the network element of the synchronous subnet of another one junction, and the synchronised clock that the synchronous subnet of another one passes over is the synchronous refernce clocks source of this synchronous subnet in network element place, and disposed clock source ID for this reference source at this network element, then this network element is when receiving from SSM Synchronication status message that the another one subnet sends over, abandon the timing reference input ID value of this actual reception, the timing reference input ID value that replaces with in this network element configuration is as the criterion, and is carrying the timing reference input ID of this network element self configuration when promptly outwards sending SSM message; Like this, can effectively this subnet and other subnet be kept apart, effectively prevent the clock loop between subnet, guarantee synchronous accuracy;
Step 4: when the active and standby synchronised clock reference source of generation in the subnet is changed, insert each network element of synchronised clock reference source and judge whether the timing reference input ID that transmits with SSM that receives is the timing reference input ID of this network element configuration, promptly whether be the timing reference input ID of the synchronised clock reference source definition that inserts for this network element, if, execution in step 5, otherwise, execution in step 6;
Step 5: determine that this synchronised clock is unavailable, and this network element transfers the clock hold mode to, the credit rating of the outside SSM that sends of this network element is disabled SSM simultaneously, the Synchronization Status Message of representing this network element transmission is unavailable, when the network element of standby synchronised clock reference source access receives this information, this network element is switched to Synchronization Status Message on the standby synchronised clock reference source, promptly the credit rating of the SSM that outwards sends is available Synchronization Status Message, that send with SSM simultaneously is the timing reference input ID of standby synchronised clock reference source, at this moment, the Synchronization Status Message that sends of this network element of receiving of other network element just can follow the tracks of realize synchronous;
Step 6: determine further according to credit rating whether this Synchronization Status Message is available,, then follow the tracks of this Synchronization Status Message and realize synchronously if credit rating is higher than the current synchronous clock grade of this network element, otherwise, abandon this Synchronization Status Message; Step 6 is identical with the implementation procedure of prior art, is not described in detail in this.
For this outbreak is more clearly described, now method of the present invention is further elaborated in conjunction with concrete application example, referring to Fig. 6, provided a typical SDH annular subnet among the figure, wherein: main BITS access network element A, the timing reference input ID of the synchronised clock reference source that main BITS introduces is 1, the credit rating of the SSM that network element A outwards sends is a clock signal (QL_PRC) G.811, be equipped with BITS access network element C, the timing reference input ID of the synchronised clock reference source of its introducing is 2, and outwards the credit rating of the SSM that sends is for G.812;
It also is the SSM of main usefulness BITS that each network element under the normal condition in the whole looped network is synchronized with the main BITS, the SSM about Synchronization Status Message that transmits in the net of use, promptly credit rating G.811, timing reference input ID is 1;
After the master was lost efficacy with BITS, network element A judges by the B network element and passes over whether the timing reference input ID that SSM carries is 1, if 1, then the timing reference input ID with network element A configuration itself is identical, network element A determines that the Synchronization Status Message that network element B sends here is unavailable, network element A changes hold mode over to, and outwards send credit rating and be G.813 SSM, when this SSM passes to the network element C that joins with standby BITS, network element C receives this credit rating for behind the SSM G.813, synchronised clock is switched on the standby BITS of high-quality level more, and is G.812 SSM to two line direction Transfer Quality grades, and the timing reference input ID that SSM carries is 2 by network element C; At this moment, after network element A receives this SSM, because its reference source ID that carries is 2, do not conflict with the timing reference input ID of network element A self configuration, so network element is followed the tracks of this Synchronization Status Message, promptly be synchronized with network element B, and successively down the Transfer Quality grade be G.812 SSM, network elements all on looped network all are synchronized with standby BITS, realize that the normal reliable of whole clock active/standby BITS is switched.
The SDH net of practical application as a rule can not be a simple looped network as shown in Figure 6, in order in the SDH net, to realize the present invention, at first need as step 1 is described, Synchronization Network to be divided, be about to Synchronization Network and be divided into a plurality of subnets, to save limited timing reference input ID resource, if do not carry out the division of subnet, in any case only 15 timing reference input ID also can't satisfy to implement needs of the present invention in the synchronizing network; Now the division thought of the subnet of SDH net is described in conjunction with Fig. 7, network shown in the figure can be divided into left and right two annular subnets, two annular subnets join by two chain a, b, have only two available synchronised clock reference sources in the whole net, and are promptly main with BITS and standby BITS;
The network that provides for Fig. 7, if do not carry out the division of subnet, and dispose different timing reference input ID respectively only for two-way synchronised clock reference source, so after link a, b in the middle of two annular subnets break down, original Synchronization Status Message from left side annular subnet will can not obtain termination because network element in the annular subnet on right side does not carry out the configuration of timing reference input ID in the annular subnet on right side, thereby cause forming in the shape subnet on right side timing loop;
Therefore, for addressing the above problem, must further divide network, be divided into two annular subnets, promptly the left side ring and the right side are encircled, left side ring uses main, standby BITS is as the master, be equipped with the synchronised clock reference source, right ring uses left side ring to pass over Synchronization Status Message as the master by two links, be equipped with the synchronised clock reference source, when two annular subnets join by multilink, then the synchronised clock of one of them link transmission is as main synchronised clock reference source, the synchronised clock that remaining link passes over is as being equipped with the synchronised clock reference source, then, be respectively a left side, the synchronised clock reference source definition corresponding clock reference source ID that uses in right two rings is logically to keep apart left side ring and right ring; On the right looped network C of unit, give simultaneously and transmit the synchronised clock configurable clock generator reference source ID of coming by link a, on network element D, give by link b and transmit the synchronised clock configurable clock generator reference source ID of coming, like this, after link a, b break down, owing to dispose timing reference input ID respectively, will can in the ring of the right side, not form timing loop in the right ring with reference to foregoing principle at network element C, D;
Here the timing reference input ID of configuration had both played the function of synchronised clock reference source sign in the right ring, also play subnet mask and (promptly isolated a left side, right ring) function: the timing reference input ID of Zuo Huanzhong can't pass through link a, b enters in the right ring, and the credit rating that SSM is only arranged can enter right ring, promptly work as network element C or network element D and receive link a, after b transmits next SSM, because of himself having disposed corresponding clock reference source ID, so network element C or network element D will abandon the timing reference input ID that SSM carries, and the timing reference input ID that self disposes is resend away with SSM; Therefore, after carrying out the division of subnet, the timing reference input ID of configuration also can be identical with the timing reference input ID value of configuration in the ring of a left side in right side ring, promptly reuses timing reference input ID sign indicating number, solved the only problem of 15 timing reference input ID sign indicating number inadequate resources.
The present invention carries out the division of subnet for the networking of complexity; and utilize the subnet mask function of timing reference input ID and the identification function of clock reference source ID; solved the problem that existing in prior technology is prone to timing loop well; improve the clock protective value, avoided the appearance of timing loop.
Claims (7)
1, prevent the method that timing loop forms in a kind of Synchronization Network, it is characterized in that comprising:
A, define the timing reference input sign respectively for the synchronised clock reference source in the Synchronization Network, and in the timing reference input of each the network element configuration correspondence that has inserted synchronised clock reference source sign, each network element transmits with synchronous state information the timing reference input sign that self disposes when sending Synchronization Status Message in Synchronization Network then;
B, in Synchronization Network, carry out active and standby synchronised clock reference source when switching, each network element determines according to the timing reference input sign of transmitting with synchronous state information that receives and the credit rating of Synchronization Status Message whether this Synchronization Status Message is available, carries out synchronously to select correct synchronised clock reference source.
2, prevent the method that timing loop forms in the Synchronization Network according to claim 1, it is characterized in that described timing reference input sign is carried on S1 byte high 4 of the SDH net synchronization message that realizes based on SSM (Synchronization Status Message) agreement, value is " 1～15 ", and is designated undefined this sign of " 0 " expression with this.
3, prevent the method that timing loop forms in the Synchronization Network according to claim 1, it is characterized in that described step a comprises:
A1, Synchronization Network is divided into a plurality of subnets, all comprises the active and standby synchronised clock reference source that inserts different network elements respectively in each subnet;
A2, for the active and standby synchronised clock reference source in each subnet defines the timing reference input sign respectively, and the network element that inserts for the active and standby synchronised clock reference source in each subnet disposes the timing reference input sign of the synchronised clock reference source correspondence that it inserted respectively;
When a3, each network element that inserts the synchronised clock reference source outwards send the Synchronization Status Message that is carrying self synchronised clock reference source, the timing reference input sign of self configuration is transmitted in Synchronization Network with this Synchronization Status Message.
4, prevent the method that timing loop forms in the Synchronization Network according to claim 3, it is characterized in that described subnet is the subnet that monocycle constitutes.
5, according to the method that prevents in claim 2 or the 3 described Synchronization Network that timing loop from forming, it is characterized in that described step b comprises:
B1, in Synchronization Network, carry out active and standby synchronised clock reference source when switching, insert each network element of synchronised clock reference source and judge whether the timing reference input sign of transmitting with synchronous state information that receives is the timing reference input sign of this network element configuration, if, execution in step b2, otherwise, execution in step b3:
B2, determine that this Synchronization Status Message is unavailable, and this network element transfers the clock hold mode to, and outwards to send credit rating be to be not useable for synchronous Synchronization Status Message;
If b3, whether available according to further definite this Synchronization Status Message of credit rating available, then utilizes this Synchronization Status Message to carry out synchronously, otherwise, abandon this Synchronization Status Message.
6, prevent the method that timing loop forms in the Synchronization Network according to claim 5, it is characterized in that described step b2 also comprises: it is after being not useable for synchronous Synchronization Status Message that the network element that inserts standby synchronised clock reference source receives the credit rating of sending, Synchronization Status Message is switched on the standby synchronised clock reference source, and outwards send the Synchronization Status Message that is carrying standby synchronised clock reference source synchronised clock, what transmit with synchronous state information is the timing reference input sign of standby synchronised clock reference source.
7, prevent the method that timing loop forms in the Synchronization Network according to claim 3, it is characterized in that: the main synchronised clock reference source that inserts when the subnet network element described in the step a1 or be equipped with the synchronised clock reference source be come from other subnets carry the Synchronization Status Message of synchronised clock the time, this method also comprises:
When this network element outwards sends Synchronization Status Message, if carry in the Synchronization Status Message that sends be other subnet transmission that this network element is connecting come synchronised clock information the time, need and to replace with the timing reference input sign that this network element disposes with the timing reference input sign that other subnet Synchronization Status Messages transmit other subnet that comes, be about to transmit in the synchronous subnet at this network element place with synchronous state information for the timing reference input sign of this network element configuration.
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| CN 02156261 CN1274117C (en) | 2002-12-12 | 2002-12-12 | Method of preventing formation of timing loop in synchronous network |
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| CN 02156261 CN1274117C (en) | 2002-12-12 | 2002-12-12 | Method of preventing formation of timing loop in synchronous network |
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| CN115102660A (en) * | 2022-08-26 | 2022-09-23 | 深圳市英特瑞半导体科技有限公司 | Method, device, equipment and storage medium for breaking damage based on synchronous Ethernet |
| CN115102660B (en) * | 2022-08-26 | 2022-11-04 | 深圳市英特瑞半导体科技有限公司 | Method, device, equipment and storage medium for breaking based on synchronous Ethernet |
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