CN1505142A - Chip possessing noise elimination system and method for making same - Google Patents
Chip possessing noise elimination system and method for making same Download PDFInfo
- Publication number
- CN1505142A CN1505142A CNA021548609A CN02154860A CN1505142A CN 1505142 A CN1505142 A CN 1505142A CN A021548609 A CNA021548609 A CN A021548609A CN 02154860 A CN02154860 A CN 02154860A CN 1505142 A CN1505142 A CN 1505142A
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- chip
- noise canceling
- canceling system
- guiding element
- noise
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The invention discloses a chip with a noise-cancelling system and its making method, it links the noise-cancelling system with its conductor component or an additional one, and thus it can effectively reduce its switching noise.
Description
Technical field
The present invention relates to a kind of chip, refer to especially a kind of noise canceling system directly is electrically connected in chip, can reduce the noise of chip effectively with noise canceling system.
Background technology
Press, see also Fig. 1, Fig. 1 is the end view that the lead frame encapsulation structure 10 of prior art is connected with printed circuit board (PCB) 11.Printed circuit board (PCB) 11 includes a upper surface 12 and a lower surface 13, and with regard to one or four layer printed circuit boards 11, upper surface 12 and lower surface 13 may be bus plane, ground plane, signals layer or component layer one of them. Passive component 14 or 15 is that (Surface MountTechnology, mode SMT) is arranged on the upper surface 12 or the lower surface 13 of printed circuit board (PCB) 11 with surface adhering.For instance, passive component 14 and 15 may be that a decoupling capacitance (de-coupling capacitor) is used for eliminating the bad coupling between circuit, or the switching noise between the bus plane of high-frequency circuit and ground plane (Simultaneous switching noise, SSN).
See also shown in Figure 2, this Fig. 2 is the ball lattice array packaging structure 20 for another prior art, wherein be laid with conductive trace (trace) 22 in the substrate 21 of this ball lattice array packaging structure 20, and chip (chip) the 23rd, sticking placing on this substrate 21, and this chip (chip) 23 and conductive trace (trace) 22 on the substrate 21 are electrically connected by bonding wire 24.Passive component 14 is to use surperficial surface adhering, and (SurfaceMount Technology, mode SMT) is arranged on the upper surface of substrate 21, makes sealing 25 encapsulation this chip (chip) 23 and this passive component 14 at last on this substrate 21.Yet above-mentioned passive component 14 also may be used for eliminating bad coupling between circuit or the switching noise between the bus plane of high-frequency circuit and ground plane for a decoupling capacitance (de-coupling capacitor).
Generally speaking, decoupling capacitance (de-coupling capacitor) should be connected in as much as possible near chip (chip) 23, to promote switching noise (the Simultaneous switchingnoise that it reduces chip (chip) 23, SSN) usefulness, yet among the existing embodiment by Fig. 1 and Fig. 2, this chip (chip) 23 and decoupling capacitance (de-coupling capacitor) are arranged on substrate 21 or the printed circuit board (PCB) 11, under this situation as shown in Figure 3, make chip (chip) 23 and bonding wire 24 and conductive trace (trace) 22 switching noises that added up (SSN) much larger than the switching noise (SSN) of chip (chip) 23 itself, so will reduce the usefulness of decoupling capacitance (de-coupling capacitor) widely.In addition as shown in Figure 1, passive component 14 and 15 occupies the upper surface 12 of part printed circuit board (PCB) 11 or the area of lower surface 13, and in Fig. 2 as can be known, passive component 14 is arranged on the substrate 21.Under above-mentioned situation, work as passive component 14, when 15 quantity is a lot, can cause printed circuit board (PCB) 11 or substrate 21 that the setting of extra cabling or other assembly can't be arranged, when this dwindles the size of printed circuit board (PCB) 11 or substrate 21 at needs, puzzlement very big on the entire circuit layout will be caused, and make this printed circuit board (PCB) 11 or the too big problem of substrate 21 sizes, also therefore increase production cost simultaneously.So therefore these device or assemblies of being arranged between chip (chip) 23 and decoupling capacitance (de-coupling capacitor) will increase the switching noise (SSN) of high-frequency circuit.
Just because of this, the inventor is at the problems referred to above and according to being engaged in the correlation experience that manufactures a product for many years, and concentrated the observation and research concentrated on studies and cooperated the utilization of scientific principle, and proposes a kind of reasonable in design and effectively improve the present invention of above-mentioned shortcoming.
Summary of the invention
Technical problem to be solved by this invention provides a kind of chip and manufacture method thereof with noise canceling system, noise canceling system is arranged at the end face of chip, like this so that can make this noise canceling system be connected in the power subsystem and the ground unit of close chip as much as possible, so the function and the effect of promoting passive component.
Another object of the present invention, be to provide a kind of chip and manufacture method thereof with noise canceling system, reduce the device that is arranged between chip and noise canceling system, so promptly reduce the switching noise that adds up of the high-frequency circuit between chip and passive component, therefore promote the worker's energy and the effect of noise canceling system.
The present invention is a purpose also, be to provide a kind of chip and manufacture method thereof with noise canceling system, noise canceling system is provided with the end face of chip, can save the area of many printed circuit board (PCB)s and substrate, therefore the size that is beneficial to printed circuit board (PCB) and substrate is dwindled, also therefore increase the surface circuit layout area of printed circuit board (PCB) and substrate, so can reduce production costs.
According to aforementioned goal of the invention, the present invention is chip and the method for making thereof that has noise canceling system for a kind of, and wherein this chip (chip) is provided with guiding element, and makes noise canceling system be electrically connected on the guiding element of this chip (chip), as to reach purpose of the present invention.
According to this feature, have at least one first guiding element and at least one second guiding element in this chip (chip), and this first guiding element is arranged at the primary importance in this chip (chip), and this second guiding element is arranged at the second place in this chip (chip), and make power subsystem and ground unit be arranged at that this chip (chip) is gone up and electrically connect with this chip (chip), and this noise canceling system includes electrical connecting unit and noise removing unit and electric connection mutually, and the electrical connecting unit of this noise canceling system electrically connects with first guiding element of this primary importance and second guiding element of the second place respectively.
In addition according to feature of the present invention, this chip (chip) is provided with power subsystem and ground unit and electrically connects with this chip (chip), the end face top of this chip (chip) is provided with the guiding element unit, and this guiding element unit is electrically connected at this power subsystem and this ground unit, and noise canceling system includes electrical connecting unit and noise removing unit, and wherein this electrical connecting unit and this noise removing unit electrically connect mutually, and this electrical connecting unit is electrically connected at this guiding element unit.
The present invention further provides a kind of manufacture method, the steps include: with chip (chip) of noise canceling system
Chip with ground unit and power subsystem is provided;
Form the guiding element layer in the end face of this chip;
This guiding element layer of etching is to form the guiding element unit;
Noise canceling system is provided;
Utilize the surface adhering technology that this noise canceling system is bonded in the end face of this chip, and this noise canceling system is connected with this guiding element unit; And
Firm abutting edge in conjunction with this noise canceling system and this guiding element unit is so that this noise canceling system and this guiding element unit electrically connect.
In order to further specify feature of the present invention and technology contents, see also following relevant detailed description of the present invention and accompanying drawing, yet this accompanying drawing only is used to provide reference and explanation, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the end view that existing lead frame encapsulation structure is connected with printed circuit board (PCB);
Fig. 2 is existing ball lattice array encapsulation cutaway view;
Fig. 3 is the switching noise of existing chip, bonding wire and the conductive trace schematic diagram that adds up;
Fig. 4 is a ball lattice array encapsulation encapsulation cutaway view of the present invention;
Fig. 5 is the cutaway view that chip surface of the present invention is provided with noise canceling system;
Fig. 6 is the cutaway view that is provided with guiding element unit and noise canceling system on the chip of the present invention in addition;
Fig. 7 is the switching noise of noise canceling system elimination chip of the present invention and the schematic diagram that influences of getting rid of bonding wire and conductive trace.
Embodiment
See also Fig. 4 and shown in Figure 6, the present invention is a kind of chip and manufacture method thereof with noise canceling system, wherein power subsystem 30, ground unit 40 and noise canceling system 50 are arranged on the chip (chip) 60 and mutually and electrically connect, so make noise canceling system 50 more effectively eliminate bad coupling between circuit in the chip (chip) 60, or the switching noise of high-frequency circuit (Simultaneous switchingnoise, SSN), and further make this chip with noise canceling system 50 (chip) 60 be arranged on the substrate 70 and electric connection, utilize sealing 80 these chips (chip) 60 of encapsulation at last on this substrate 70 with noise canceling system 50.
See also Fig. 4 to shown in Figure 6, near around this chip (chip) 60 is to be provided with power subsystem 30 and ground unit 40, this power subsystem 30 and ground unit 40 respectively have connection pad 41 and bonding wire 42, and this connection pad 41 is arranged on this chip (chip) 60 and mutually and electrically connects, and to make these connection pads 41 be to be welded with bonding wire 42, and this bonding wire 42 is electrically connected on the conductive trace (figure does not show) on this substrate 70.
See also shown in Figure 5, this first embodiment has first guiding element 61 and second guiding element 62 in this chip (chip) 60, and this first guiding element 61 is arranged at the primary importance 63 in this chip (chip) 60, and this second guiding element 62 is arranged at the second place 64 in this chip (chip) 60, this primary importance 63 and the second place 64 are to communicate with the external world, this first guiding element 61 electrically connects mutually with the connection pad 41 of this power subsystem 30, and this second guiding element 62 electrically connects (figure does not show) mutually with the connection pad 41 of this ground unit 40; The upper surface 67 of this chip (chip) 60 is a protective layer, the first guiding element through hole 65 and the second guiding element through hole 66 are formed on this protective layer, this first guiding element through hole 65 is connected with first guiding element 61 of primary importance 63, and this second guiding element through hole 66 is connected with second guiding element 62 of the second place 64, wherein this primary importance 64 and the second place 64 are positioned near the pars intermedia of this chip (chip) 60, and first guiding element 61 and second guiding element 62 are in communication with the outside; This noise canceling system 50 includes electrical connecting unit 51 and noise removing unit 52 and electric connection mutually, wherein this electrical connecting unit 51 has two electrical connection sections 53, this two electrical connection section 53 extends through this first guiding element through hole 65 and the second guiding element through hole 66 respectively accordingly, and electrically connect with first guiding element 61 of this primary importance 63 and second guiding element 62 of this second place 64 accordingly respectively, this noise canceling system 50 can be the decoupling capacitance (de-couplingcapacitor) of passive component in addition, and above-mentioned guiding element 61,62 is the circuit in the chip (chip) 60, and this power subsystem 30, ground unit 40 and noise canceling system 50 can be arranged at the same side of this chip (chip) 60.
See also shown in Figure 6, be second embodiment, for other is provided with guiding element unit 90 in reaching noise canceling system 50 in upper surface 67 tops of this chip (chip) 60, this guiding element unit 90 includes first guiding element 61 ' and second guiding element 62 ', it is arranged at the primary importance 63 ' and the second place 64 ' of this chip (chip) 60 respectively accordingly, and this first guiding element 61 ' electrically connects with the connection pad 41 of this power subsystem 30, and this second lead 62 ' electrically connects with the connection pad 41 of this ground unit 40, and this chip (chip) 60 and above-mentioned guiding element 61 ', 62 ' surface is provided with protective layer 100, be formed with the first guiding element through hole 65 ' and the second guiding element through hole 66 ' on this protective layer 100, this first guiding element through hole 65 ' is to should primary importance 63 ' and be connected with this first guiding element 61 ', this second guiding element through hole 66 ' is to should the second place 64 ' and be connected with this second guiding element 62 ', and wherein this primary importance 63 ' and the second place 64 ' are positioned near the pars intermedia of this chip (chip) 60; The electrical connecting unit 51 of this noise removing unit 52 has two electrical connection sections 53, two these electrical connection sections 53 extend through this first guiding element through hole 65 ' and the second guiding element through hole 66 ' respectively accordingly, and be electrically connected on first guiding element 61 ' of this primary importance 63 ' and second guiding element 62 ' of this second place 64 ' respectively accordingly, and wherein above-mentioned guiding element 61 ', 62 ' is circuit, and the decoupling zero that this noise canceling system 50 is passive component electricity visitor (de-coupling capacitor).
See also shown in Figure 4, the chip (chip) 60 that will have noise canceling system 50 is arranged at ball formula grid array (BallGridArray, BGA) on the substrate 70, and this substrate 70 is provided with the conductive trace (trace) (figure does not show) that is connected in power supply and ground connection, and make power subsystem 30 of this chip (chip) 60 and ground unit 40 be electrically connected on the power supply of substrate 70 and the conductive trace of ground connection (trace) respectively accordingly by bonding wire 42, and the chip (chip) 60 that utilizes sealing 80 will have noise canceling system 50 is packaged on the substrate 70, and the guiding element unit 90 that forms on this chip is metal level (redistribution layer).
See also shown in Figure 7, expression with noise canceling system 50 directly then when the end face of chip (chip) 60, can get rid of switching noise (the Simultaneous switching noise that the conductive trace (tracel) of bonding wire 42 and substrate 70 causes more and more sooner because of switch speed, SSN), make noise canceling system 50 directly eliminate the switching noise (Simultaneous switching noise, S SN) that causes more and more sooner because of switch speed of chip (chip) 60 effectively.
In addition, a kind of manufacture method with chip of noise canceling system the steps include:
Chip with ground unit and power subsystem is provided;
Form the guiding element layer in the end face of this chip;
This guiding element layer of etching is to form the guiding element unit;
Noise canceling system is provided;
Utilize the surface adhering technology with this noise canceling system for tying end face in this chip, and this noise canceling system is connected with this guiding element unit; And
Firm abutting edge in conjunction with this noise canceling system and this guiding element unit is so that this noise canceling system and this guiding element unit electrically connect.
Wherein, wherein this guiding element layer is the end face that electric conducting material is sputtered at this chip (chip), and utilizes selective etch mode etching guiding element layer, to form the guiding element unit of a plurality of guiding elements.
Invention characteristics and advantage
In sum, by " chip " of the present invention, have following advantage with noise canceling system:
1. directly make noise canceling system be connected in that chip (chip) is gone up and electrically connect, therefore shorten the distance that is electrically connected of chip (chip) and noise canceling system.
2. can reduce effectively chip (chip) switching noise (Simultaneous switching noise, SSN).
3. reduce the assembly setting on printed circuit board (PCB) and the substrate, therefore dwindle printed circuit board (PCB) and substrate size easily, so that can reduce production costs.
Above said content only is a preferable possible embodiments of the present invention, is not to be used to limit protection scope of the present invention, and the equivalent structure that all utilizations specification of the present invention and accompanying drawing content are done changes, and all in like manner all is contained in protection scope of the present invention.
Claims (10)
1. the chip with noise canceling system is characterized in that, comprising: chip; At least one noise canceling system is electrically connected on described chip surface.
2. the chip with noise canceling system as claimed in claim 1 is characterized in that described noise canceling system is a decoupling capacitance.
3. the chip with noise canceling system as claimed in claim 1 is characterized in that two ends of described noise canceling system are electrically connected on the guiding element unit on the upper strata of this chip, with respectively with chip on power supply and ground connection join.
4. the chip with noise canceling system as claimed in claim 1, two ends that it is characterized in that described described noise canceling system are electrically connected on the extra guiding element unit that forms on this chip, with respectively with chip on power supply and ground connection join.
5. the chip with noise canceling system as claimed in claim 4 is characterized in that the extra guiding element unit that forms is a metal level on the described chip.
6. manufacture method with chip of noise canceling system is characterized in that: comprise step:
Chip with ground unit and power subsystem is provided;
Form the guiding element layer in the end face of this chip;
This guiding element layer of etching is to form the guiding element unit;
Noise canceling system is provided;
Utilize the surface adhering technology that this noise canceling system is bonded in the end face of this chip, and this noise canceling system is connected with this guiding element unit, and
Firm abutting edge in conjunction with this noise canceling system and this guiding element unit is so that this noise canceling system and this guiding element unit electrically connect.
7. the manufacture method with chip of noise canceling system as claimed in claim 6 is characterized in that described guiding element layer is the end face that electric conducting material is sputtered at this chip.
8. the manufacture method with chip of noise canceling system as claimed in claim 6 is characterized in that described noise canceling system is a passive component.
9. the manufacture method with chip of noise canceling system as claimed in claim 6 is characterized in that described noise canceling system is a decoupling capacitance.
10. the manufacture method with chip of noise canceling system as claimed in claim 6 is characterized in that described above-mentioned guiding element unit is the circuit layer of chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021548609A CN1505142A (en) | 2002-12-02 | 2002-12-02 | Chip possessing noise elimination system and method for making same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021548609A CN1505142A (en) | 2002-12-02 | 2002-12-02 | Chip possessing noise elimination system and method for making same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1505142A true CN1505142A (en) | 2004-06-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021548609A Pending CN1505142A (en) | 2002-12-02 | 2002-12-02 | Chip possessing noise elimination system and method for making same |
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| Country | Link |
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| CN (1) | CN1505142A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100419623C (en) * | 2005-08-24 | 2008-09-17 | 纬创资通股份有限公司 | Noise information interference resistant system and its method |
| CN101322403B (en) * | 2005-12-21 | 2010-11-10 | 香港应用科技研究院有限公司 | Auto-regressive method and filter for denoising images and videos |
| CN103378074A (en) * | 2012-04-19 | 2013-10-30 | 联发科技股份有限公司 | Chip package |
-
2002
- 2002-12-02 CN CNA021548609A patent/CN1505142A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100419623C (en) * | 2005-08-24 | 2008-09-17 | 纬创资通股份有限公司 | Noise information interference resistant system and its method |
| CN101322403B (en) * | 2005-12-21 | 2010-11-10 | 香港应用科技研究院有限公司 | Auto-regressive method and filter for denoising images and videos |
| CN103378074A (en) * | 2012-04-19 | 2013-10-30 | 联发科技股份有限公司 | Chip package |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
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