CN1499631A - Circuit for testing time constant of integrated resistance-capacitance product inside chip - Google Patents
Circuit for testing time constant of integrated resistance-capacitance product inside chip Download PDFInfo
- Publication number
- CN1499631A CN1499631A CNA021340226A CN02134022A CN1499631A CN 1499631 A CN1499631 A CN 1499631A CN A021340226 A CNA021340226 A CN A021340226A CN 02134022 A CN02134022 A CN 02134022A CN 1499631 A CN1499631 A CN 1499631A
- Authority
- CN
- China
- Prior art keywords
- circuit
- time constant
- electric capacity
- filter
- testing time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Networks Using Active Elements (AREA)
Abstract
The testing circuit includes active RC filter, and controllable unit array added in each first order RC composed of RC circuit structure units associated to each pole in designing RC active filter and filters. Controable unit array connected to conventional RC unit is adjusting unit able to change RC time constant. A circuit for testing RC product time constant is setup, and a logic correcting circuit is setup. The logic correcting circuit compares measured RC time constant and designed desired value. Single filter can be designed by the said method so that the difference between each pole and designed desired value is within deviation needed. Moreover, tunable filter can be designed to make each pole position controllable with accuracy.
Description
The invention belongs to the integrated circuit (IC) design field, relate to a kind of Filter Design method, the accurate controlled Filter Design method of cut-off frequency particularly, it both can be the general filter that works in single cut-off frequency, also can be the filter of cut-off frequency accurate conversion between several frequencies.
Along with development of technology, the electronic system of communication system and household electrical appliance becomes increasingly complex.Handle for the signal with several different systems, different frequent points, different bandwidth utilizes a center processor pattern, need in a system, increase a plurality of filters and finish.As present collection and wireless communication system, there are GSM, GPRS, W-CDMA system and CDMA, CDMA 1X, CDMA2000 system.In each system inside, after upgrading, variation has all taken place in the bandwidth of signal and frequency, and therefore, integrated a plurality of filters are to satisfy the requirement of signal processing in mobile phone; In practical application each time, all be to use one of them filter, thereby make Redundancy Design essential.
Integrated circuit can be introduced random error in the process of making, promptly the actual parameter of each device and design load have departing from of a little.As design a RC active filter, and because the influence of resistance and electric capacity random error, the cut-off frequency of practical filter can near the swing at random cut-off frequency that requires, maximum error can reach+and/-50%.
The at present basic method that adopts laser-adjusting is finely tuned in the integrated circuit testing stage the high resistance of required precision and electric capacity and is satisfied the requirement of system to precision.But along with aging speed difference during the integrated circuit aging and IC interior diverse location in use, the precision of chip in application can reduce gradually.
Error profile between the different silicon circles is incoherent, and the device error that same silicon circle is gone up on the diverse location chip also is incoherent.Therefore, when utilizing the laser-adjusting means, need all carry out in various degree correction, thereby improve the cost of chip at each chip.
The defective of employing method is at present:
(1) needs accurate testing equipment
(2) error can increase gradually in the use
(3) cost height
(4) need take bigger chip area
In view of the defective of present said method, the objective of the invention is error to be realized that the particularly correction of resistance capacitance product time constant error makes filter cutoff frequency accurately controlled from dynamic(al) correction in the integrated automatic correction system of chip internal.
The objective of the invention is to realize by the following method.
Circuit for testing time constant at chip internal integrated resistor electric capacity product, realization is accurately controlled at cut-off frequency in the design of RC active filter, comprise active RC filter, increase the controllable array among each single-order RC that the RC active filter RC circuit structure unit related with each limit in the Design of Filter constitutes, the unit can be realized under logical signal control and being connected or disconnection of prototype unit in this controllable array; The controllable array is the adjustment unit that is connected and can changes the RC time constant with conventional RC unit; The test circuit of a RC product time constant is set, the time constant and the numerical value in the side circuit of needs are compared and computing, obtain different logic control signals and open or turn-off the controllable array and adjust the numerical value that time constant makes it to reach to be needed; One logic correcting circuit is set, and this circuit compares RC time constant that measures and the numerical value that design needs.
The correction of RC time constant can disposablely reach, and also can utilize step-by-step method progressively to approach and obtain.Utilize the precision of step-by-step method will be higher than the one-time calculation method.
After adopting design as above, the integrated automatic correction system of chip internal realizes that to error the particularly correction of resistance capacitance product time constant error makes filter cutoff frequency accurately controlled from dynamic(al) correction.
Description of drawings is as follows,
Fig. 1: the circuit of existing RC active filter
Fig. 2: RC product time constant test circuit
Fig. 3: single cut-off frequency is controlled filter accurately
Fig. 4: a plurality of cut-off frequency points are controlled tunable optic filter accurately
The correction array schematic diagram that Fig. 5: RC mixes
The invention will be further described below in conjunction with drawings and Examples.
Figure 1 shows that existing RC active filter prototype circuit.Signal VinP connects the positive input terminal of fully differential operational amplifier after resistance R 1 input, operational amplifier positive input termination capacitor C 1, and C1 meets operational amplifier negative output terminal VoutN; Signal VinN connects the negative input end of operational amplifier after resistance R 2 input, and the operational amplifier negative input end connects capacitor C 2, and C2 meets operational amplifier positive output end VoutP.
The cut-off frequency of this RC active filter is only relevant with the RC time constant, but because the influence of random error, cut-off frequency is a change at random; When a system needs filter to work in different cut-off frequencies, need integrated a plurality of filter circuits.
Figure 2 shows that RC product time constant test circuit.Annexation is: reference voltage Vref concatenation operation amplifier positive input terminal, the operational amplifier negative input end connects resistance and transistor MT1 source electrode, the output of MT1 grid concatenation operation amplifier and drain and connect current mirror I1, current mirror I1, I2, the I3 ratio is 1: 1: K, current mirror I2 connects another one current mirror I4, current mirror I4, the I5 ratio is 1: N, electric current I 3 and I5 and switch SW 1, SW2 connects, SW1, SW2 one end is connected with electric capacity and comparator positive input terminal, an other end is ground connection and power supply respectively, switch SW 1, SW2 is controlled by OUT and OUTB, the negative input end of comparator connects another one reference voltage Vref 2, exports OUTB and OUT respectively behind the output process two-stage inverter of comparator.
OUT is the input of COUNTER1 and CLKref is the input of COUNTER2, and COUNTER1 and COUNTER2 are subjected to Start﹠amp; End LOGIC module controls, they are output as the input of CALCULATOR module, and CALCULATOR is output as OUTPUT.
Operation principle is: when voltage on the electric capacity when returning the higher limit of comparator between the dead zone, OUTB is low for height OUT, switch SW 1 imports the electric capacity charging with the I3 electric current, switch SW 2 imports power supplys with electric current I 5; When voltage on the electric capacity when returning the higher limit of comparator between the dead zone, OUT is low for height OUTB, switch SW 2 imports capacitor discharge with the I5 electric current, switch SW 1 imports ground with electric current I 3.
When voltage on the electric capacity was lower than back the lower limit of comparator between the dead zone, OUTB was low for height OUT again, begins a new charge cycle, thereby obtains a triangular wave oscillator, and OUT and OUTB are periodic pulse signal.The cycle of pulse signal and RC time constant are proportional.
COUNTER1 and COUNTER2 are opened for OUT and reference clock CLKref counting simultaneously, when counting down to M2, COUNTER2 stops the counting of COUNTER1 and COUNTER2 simultaneously, the result who supposes COUNTER1 this moment is M1, M1 and M2 just obtain the absolute value information about the RC time constant after CALCULATOR handles.
The electric current of current mirror I1 is: I1=Vref/R
Charging current is: I3=K*I1
Discharging current is: I5=N*I1
The triangular wave rising edge time: C*dV/I3
The triangular wave trailing edge time: C*dV/I5
Triangle is wave period: T=RC* (dv/Vref) * (1/K+1/N)
The cycle of reference clock is Tref, then has:
T*M1＝Tref*M2
The absolute value that obtains the RC time constant thus is:
RC＝Tref*(M2/M1)*(Vref/dV)*(K*N/(K+N))
In following formula, dV is the voltage between the dead zone that returns of comparator, and Vref is a reference voltage, determines and varies with temperature little voltage as voltage values such as bandgap voltage references.
Be illustrated in figure 3 as accurately controlled filter of single cut-off frequency.Annexation is: the positive input terminal that connects the fully differential operational amplifier behind signal VinP process switch SW PR, resistance R P and the SWPRD, operational amplifier positive input termination capacitor C P1, CP1 meets operational amplifier negative output terminal VoutN, capacitor C P[2, N] through switch SW P[2, N] be connected, N through switch SW P[2 with the operational amplifier positive input terminal] D is connected with the negative output terminal VoutN of operational amplifier; Connect the negative input end of fully differential operational amplifier behind signal VinN process switch SW NR, resistance R N and the SWNRD, the operational amplifier negative input end meets capacitor C N1, CN1 meets operational amplifier positive output end VoutP, capacitor C N[2, N] through switch SW N[2, N] be connected, N through switch SW N[2 with the operational amplifier negative input end] D is connected with the positive output end VoutP of operational amplifier.
Reference voltage Vref concatenation operation amplifier positive input terminal, the operational amplifier negative input end connects SWNR switch and transistor MT1 source electrode, resistance R N passes through switch SW NRD ground connection by the negative input end of switch SW NR concatenation operation amplifier, the output of transistor MT1 grid concatenation operation amplifier and drain and connect current mirror I1, current mirror I1, I2, the I3 ratio is 1: 1: K, current mirror I2 connects another one current mirror I4, current mirror I4, the I5 ratio is 1: N, electric current I 3 and I5 and switch SW 1, SW2 connects, SW1, SW2 one end is connected with electric capacity and comparator positive input terminal, an other end is ground connection and power supply respectively, capacitor C N[2, N] by switch SW N[2, N] be connected with the comparator positive input terminal and by switch SW N[2, N] D ground connection, switch SW 1, SW2 is controlled by OUT and OUTB, the negative input end of comparator connects another one reference voltage Vref 2, exports OUTB and OUT respectively behind the output process two-stage inverter of comparator.
OUT is the input of COUNTER1 and CLKref is the input of COUNTER2, and COUNTER1 and COUNTER2 are subjected to Start﹠amp; End LOGIC module controls, they are output as the input of CALCULATOR module, and CALCULATOR is output as Adder input and Adder is output as the Register2 input, Register2 is output as switch controlling signal SW[P, N] [2, N] [, D], Start﹠amp; End LOGIC module be input as Register1.
With step-by-step method explanation operation principle: with Adder and Register zero clearing, enter calibration phase after powering on, SW[P, N] between the source electrode and ground of R with resistance R P or RN access transistor MT1, disconnect other all switches.According to formula RC=Tref* (M2/M1) * (Vref/dV) * (K*N/ (K+N)), the data M 1 that calculated in advance is good leaves among the Register1.
Carry out the counting operation first time, in the cycle, the result of COOUNTER1 will be greater than the data M 1 that prestores at M2 reference clock signal; CALCULATOR output control adder Adder carries out add-one operation, with the Adder storage in Register2, signal SW[P, N] [2, N] [, D] control pair of switches conducting, with capacitor C N] 2, N] in one in parallel with capacitor C N1.
Once count computing again, check whether the data among the COUNTER1 equate with M1.If two data are unequal, Adder carries out add-one operation again, till repeating the data of above-mentioned adjustment process in COUNTER1 and M1 equating; If two data equate, then with the Adder storage in Register, change the Register address, one group of new RC is proofreaied and correct, till all RC finish correction.
In above adjustment process, if Adder and Register are put 1 when initially powering on, then Adder need subtract 1 computing in correction.
More than adjust and carry out, the higher order filter that has a plurality of zero points and limit is adjusted, need to calculate in advance many group M1 storage and in Registerl, get final product at a limit.
Be illustrated in figure 4 as accurately controlled tunable optic filter of a plurality of cut-off frequency points.In Register1, store multi-group data M[CF1, CFM in advance] [P1, PX], M[P1, PX] be filter when being operated in cut-off frequency CF1～CFM, multi-stage filter is proofreaied and correct the RC time constant on each frequency, and the data that the position of each pole and zero needs in the filter.
According to formula RC=Tref* (M2/M1) * (Vref/dV) * (K*N/ (K+N))
M[P1，PX]＝Tref*(M2/RC[P1，PX])*(Vref/dV)*(K*N/(K+N))
RC[P1 wherein, PX] each pole and zero data of obtaining for Theoretical Calculation.
Data M [CF1, CFM] [P1, PX] is carried out above-mentioned trimming process one by one, when obtaining on tunable each frequency, working, the zero point of multi-stage filter and the pole location error logic control signal SW[CF1 in needing scope, CFM] [P, N] [2, N] [, D].
When filter is operated in frequency CF1, with data SW[CF1] [P, N] [2, N] [, D] from register Register2, read, control the annexation of corresponding correction array unit and prototype unit then, the filter that just can to obtain a cut-off frequency be the CF1 frequency; Equally, sense data is respectively SW[CF1 from register, CFM] [P, N] [2, N] [, D] time, the accurate controlled filter of tunable range between CF1 frequency～CFM frequency of a cut-off frequency just obtained.
The correction array unit both can be an electric capacity, also can be resistance.Be illustrated in figure 5 as the correction array schematic diagram that RC mixes.Being with electric capacity correction array difference, is in parallel between the correcting unit of electric capacity and the prototype unit; And connect between the correcting unit of resistance and the prototype unit.
Claims (10)
1, a kind of circuit for testing time constant at chip internal integrated resistor electric capacity product, realization is accurately controlled at cut-off frequency in the design of RC active filter, comprise active RC filter, it is characterized in that, increase the controllable array among each single-order RC that the RC active filter RC circuit structure unit related with each limit in the Design of Filter constitutes, the unit can be realized under logical signal control and being connected or disconnection of prototype unit in this controllable array; The controllable array is the adjustment unit that is connected and can changes the RC time constant with conventional RC unit; The test circuit of a RC product time constant is set, the time constant and the numerical value in the side circuit of needs are compared and computing, obtain different logic control signals and open or turn-off the controllable array and adjust the numerical value that time constant makes it to reach to be needed; One logic correcting circuit is set, and this circuit compares RC time constant that measures and the numerical value that design needs.
2, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 1 is characterized by: described controllable array both can be controlled capacitor cell array, also can be controlled resistance unit array.
3, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 2, it is characterized by: described controlled capacitance array is in parallel with the electric capacity in the prototype circuit; The controllable resistor array can with the resistance serial or parallel connection in the prototype circuit.
4, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 1, it is characterized by: described RC circuit for testing time constant is an oscillator, the signal period of oscillator is directly proportional with the RC time constant.
5, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 4 is characterized by: described pierce circuit is in each constituent element of decision signal period, and except RC, other constituent element all is accurate controlled.
6, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 4, it is characterized by: described pierce circuit can be a triangular-wave generator, also can make sawtooth waveforms or sine-wave generator.
7, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 1, it is characterized by: described logic correcting circuit measures in a period of time by the waveform number that oscillator is sent, calculate with the data of storage in advance, the result is stored in the register, each unit and the annexation of prototype unit in the output of the register control correction array, thus change RC time constant realizes.
8, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 7 is characterized by: described logic correcting circuit can be proofreaied and correct in disposable realization, also can progressively realize proofreading and correct.
9, the circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 1 is characterized by: the accurate controllable filter of cut-off frequency both can be the filter that is operated in single cut-off frequency point, also can be tunable optic filter.
10, circuit for testing time constant at chip internal integrated resistor electric capacity product according to claim 1, it is characterized by: described RC product time constant test circuit annexation is: reference voltage Vref concatenation operation amplifier positive input terminal, the operational amplifier negative input end connects resistance and transistor MT1 source electrode, the output of MT1 grid concatenation operation amplifier and drain and connect current mirror I1, current mirror I1, I2, the I3 ratio is 1: 1: K, current mirror I2 connects another one current mirror I4, current mirror I4, the I5 ratio is 1: N, electric current I 3 and I5 and switch SW 1, SW2 connects, SW1, SW2 one end is connected with electric capacity and comparator positive input terminal, an other end is ground connection and power supply respectively, switch SW 1, SW2 is controlled by OUT and OUTB, the negative input end of comparator connects another one reference voltage Vref 2, exports OUTB and OUT respectively behind the output process two-stage inverter of comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021340226A CN1499631A (en) | 2002-11-08 | 2002-11-08 | Circuit for testing time constant of integrated resistance-capacitance product inside chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021340226A CN1499631A (en) | 2002-11-08 | 2002-11-08 | Circuit for testing time constant of integrated resistance-capacitance product inside chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1499631A true CN1499631A (en) | 2004-05-26 |
Family
ID=34231352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021340226A Pending CN1499631A (en) | 2002-11-08 | 2002-11-08 | Circuit for testing time constant of integrated resistance-capacitance product inside chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1499631A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101820261A (en) * | 2010-04-21 | 2010-09-01 | 广州市广晟微电子有限公司 | Device and method for correcting cut-off frequency of filter |
| CN101894195A (en) * | 2010-08-02 | 2010-11-24 | 昆山锐芯微电子有限公司 | Method for determining time constant of depletion region of photodiode and improving residual image |
| CN103036532A (en) * | 2011-10-10 | 2013-04-10 | 神讯电脑(昆山)有限公司 | Underpower component automatic test circuit |
| CN103546153A (en) * | 2012-07-16 | 2014-01-29 | 中兴通讯股份有限公司 | Time constant correcting circuit and method |
| CN108318720A (en) * | 2018-02-06 | 2018-07-24 | 苏州瑞铬优电子科技有限公司 | A kind of bidirectional current detection amplifier |
| CN110113028A (en) * | 2019-04-29 | 2019-08-09 | 西安电子科技大学 | Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter |
| CN114337600A (en) * | 2022-03-11 | 2022-04-12 | 华南理工大学 | On-chip differential active RC filter calibration and tuning method |
-
2002
- 2002-11-08 CN CNA021340226A patent/CN1499631A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101820261A (en) * | 2010-04-21 | 2010-09-01 | 广州市广晟微电子有限公司 | Device and method for correcting cut-off frequency of filter |
| CN101820261B (en) * | 2010-04-21 | 2013-03-27 | 广州市广晟微电子有限公司 | Device for correcting cut-off frequency of filter |
| CN101894195A (en) * | 2010-08-02 | 2010-11-24 | 昆山锐芯微电子有限公司 | Method for determining time constant of depletion region of photodiode and improving residual image |
| CN103036532A (en) * | 2011-10-10 | 2013-04-10 | 神讯电脑(昆山)有限公司 | Underpower component automatic test circuit |
| CN103036532B (en) * | 2011-10-10 | 2016-10-12 | 神讯电脑(昆山)有限公司 | Automatic testing circuit for low power elements |
| CN103546153A (en) * | 2012-07-16 | 2014-01-29 | 中兴通讯股份有限公司 | Time constant correcting circuit and method |
| CN103546153B (en) * | 2012-07-16 | 2018-10-12 | 中兴通讯股份有限公司 | The correcting circuit of time constant and bearing calibration |
| CN108318720A (en) * | 2018-02-06 | 2018-07-24 | 苏州瑞铬优电子科技有限公司 | A kind of bidirectional current detection amplifier |
| CN110113028A (en) * | 2019-04-29 | 2019-08-09 | 西安电子科技大学 | Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter |
| CN110113028B (en) * | 2019-04-29 | 2021-08-20 | 西安电子科技大学 | Voltage-dividing integral type constant-time calibration circuit of on-chip active RC filter |
| CN114337600A (en) * | 2022-03-11 | 2022-04-12 | 华南理工大学 | On-chip differential active RC filter calibration and tuning method |
| CN114337600B (en) * | 2022-03-11 | 2022-06-03 | 华南理工大学 | On-chip differential active RC filter calibration and tuning method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107241098B (en) | Offset calibration circuit of comparator in asynchronous successive approximation type analog-to-digital converter | |
| CN102843136B (en) | A kind of high-speed, high precision low-power consumption dynamic comparer offset correction method on a large scale | |
| EP3340472A1 (en) | Dac capacitor array and analog-to-digital converter, method for reducing power consumption of analog-to-digital converter | |
| US10270459B2 (en) | DAC capacitor array, SAR analog-to-digital converter and method for reducing power consumption thereof | |
| CN107807511A (en) | Calibration equipment and method, calibration equipment manufacture method and integrated circuitry construction method | |
| CN110311677B (en) | SAR ADC based on novel capacitance switch switching algorithm | |
| CN102594348B (en) | Calibration circuit and method for calibrating capacitive compensation in digital-to-analog converters | |
| CN1960180A (en) | Clock signal detection circuit | |
| EP3322096A1 (en) | Dac capacitor array, sar analog-to-digital converter and method for reducing power consumption | |
| CN108462492A (en) | A kind of correcting circuit of SAR_ADC unbalance of system voltage and bearing calibration | |
| CN112422106B (en) | Comparator for inhibiting offset voltage and method for inhibiting offset voltage of comparator | |
| CN1499631A (en) | Circuit for testing time constant of integrated resistance-capacitance product inside chip | |
| CN103414474B (en) | High-precision small-signal difference analog-digital converter | |
| CN108306618A (en) | A kind of photovoltaic IV testers | |
| CN105811984B (en) | Input sampling and converting circuit | |
| CN111327324A (en) | Capacitor array structure suitable for successive approximation type analog-to-digital converter | |
| CN114204942B (en) | Successive approximation type analog-to-digital converter and conversion method | |
| CN108809314A (en) | Optimize the SAR ADC comparison circuits and its method of controlling switch of capacitor array area | |
| CN109212448B (en) | Self-stabilizing zero circuit | |
| US20010045864A1 (en) | Method and arrangement for calibrating an active filter | |
| CN115473531A (en) | High-precision high-linearity analog-to-digital converter with low power consumption and small layout | |
| US7157945B2 (en) | Window comparator and method of providing a window comparator function | |
| CN102263106A (en) | Semiconductor integrated circuit | |
| CN106411287B (en) | A kind of tunable complex intermediate frequency filter of low-power consumption double mode | |
| CN101710827A (en) | Dynamic offset generating circuit for streamline analog-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |