CN112422106B - Comparator for inhibiting offset voltage and method for inhibiting offset voltage of comparator - Google Patents
Comparator for inhibiting offset voltage and method for inhibiting offset voltage of comparator Download PDFInfo
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- CN112422106B CN112422106B CN202110094207.XA CN202110094207A CN112422106B CN 112422106 B CN112422106 B CN 112422106B CN 202110094207 A CN202110094207 A CN 202110094207A CN 112422106 B CN112422106 B CN 112422106B
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- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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Abstract
The invention provides a comparator for inhibiting offset voltage and a method for inhibiting the offset voltage of the comparator, comprising the following steps: a comparison module; the differential operation module generates a first mismatch signal and a second mismatch signal; the voltage-controlled oscillation module generates a first oscillation signal and a second oscillation signal based on the first mismatch signal and the second mismatch signal; the counting module is used for counting the first oscillating signal and the second oscillating signal; a digital control module generating a control signal based on the count value; and the decoding module is used for decoding the control signal to obtain a trimming signal. The positive phase input end and the negative phase input end of the comparison module receive the common mode signal and output a first mismatch signal and a second mismatch signal; quantizing the first and second mismatch signals, respectively; and generating a control signal based on the counting value to adjust the load size or the input pipe size of the comparison module. The invention is fully automatic, has small consumed area and small occupied time, and has very little influence on the bandwidth of the comparator; meanwhile, the invention is executed when the chip is powered on, so that the drift of the offset voltage can be tracked.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a comparator for suppressing an offset voltage and a method for suppressing an offset voltage of the comparator.
Background
Comparators are the most commonly used modules for most Analog to Digital converters (ADCs). The comparator is an important module of the successive conversion ADC, the sigma-delta ADC or the Flash ADC, and offset (offset) of the comparator directly influences the output precision of the ADC, even the output is saturated, and the normal work of the ADC is influenced. Therefore, the design of the comparator generally focuses on how to suppress or eliminate the offset voltage.
ExistingIn the technology, a method of increasing the sizes of an input pair transistor and an output load of a comparator is generally adopted to suppress the offset voltage of the comparator from a design end, the mismatch caused by the increase of the sizes of the input pair transistor and the output load is reduced, and the offset voltage is smaller, but the design occupies a larger area, particularly when the number of comparators is large; like for example Flash ADC, whose number of comparators grows exponentially with conversion accuracy, 3bit requires 7 (by 2)3-1) and 63 out of 6 bits, therefore, it is obviously not desirable to suppress the offset voltage by increasing the area of these types of ADCs, which directly increases the cost of a single chip.
Another method is to introduce an automatic storage offset mechanism in the design, i.e. the input is short-circuited first, then the output is connected to the capacitor, so that the offset voltage of the equivalent output is stored on the capacitor, and the offset voltage stored on the capacitor is subtracted from the actual output during normal conversion, so as to offset the offset of the comparator. The method also belongs to an automatic calibration method, but an additional phase is required to be provided to enable the comparator to firstly enter an input short-circuit mode to store the offset voltage before the comparator normally works every time, and obviously, the conversion time is occupied under the condition; in addition, a capacitor is required to be inserted, the capacitor can increase the output capacitive load of the comparator, and the bandwidth of the comparator is reduced; therefore, this approach is not suitable for use in ultra-high speed ADC designs.
Besides, a more common method is to input a small ramp signal to the comparator to capture the position of the output jump point corresponding to the input signal, and then adjust the size according to the recorded position of the input signal and record the adjusted position in the memory.
Therefore, how to reduce the chip consumption area, reduce the conversion time, and not affect the comparator bandwidth while achieving the automatic calibration of the offset voltage of the comparator has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a comparator for suppressing an offset voltage and a method for suppressing an offset voltage of the comparator, which are used to solve the problems that a calibration circuit for an offset voltage of a comparator in the prior art consumes a large chip area, occupies a conversion time, and affects a bandwidth of the comparator.
To achieve the above and other related objects, the present invention provides a comparator for suppressing an offset voltage, comprising:
the comparison module is used for comparing the input signals;
the differential operation module is connected with the output end of the comparison module and outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals output by the comparison module and mismatched;
the voltage-controlled oscillation module is connected with the output end of the differential operation module and generates a first oscillation signal and a second oscillation signal based on the first mismatch signal and the second mismatch signal respectively;
the counting module is connected with the output end of the voltage-controlled oscillation module and is used for respectively counting the first oscillation signal and the second oscillation signal within a preset time period to obtain a first counting value and a second counting value;
the digital control module is connected with the output end of the counting module, judges the polarity and the magnitude of the offset voltage based on the difference value of the first counting value and the second counting value and generates a corresponding control signal;
and the decoding module is connected with the output end of the digital control module, decodes the control signal to obtain a trimming signal, trims the load size or the input tube size of the comparison module based on the trimming signal, and further calibrates the offset voltage of the comparison module.
Optionally, when the trimming signal trims the load size of the comparison module, the comparison module includes a first input tube, a second input tube, a first switch, a second switch, a third switch, a fourth switch, a current source, a first adjustable load, and a second adjustable load;
the source electrodes of the first input tube and the second input tube are grounded through the current source; the grid electrode of the first input transistor is connected with an inverted input signal through the first switch, is connected with a common-mode signal through the second switch, and the drain electrode of the first input transistor is connected with a power supply voltage through the first adjustable load; the grid electrode of the second input transistor is connected with a positive input signal through the third switch, the common-mode signal through the fourth switch, and the drain electrode of the second input transistor is connected with the power supply voltage through the second adjustable load; the first adjustable load and the second adjustable load adjust the load size based on the control of the trimming signal;
the first switch and the third switch receive a first switch signal, the second switch and the fourth switch receive a second switch signal, and the first switch signal and the second switch signal are inverse signals.
Optionally, when the trimming signal trims the size of the input tube of the comparison module, the comparison module includes a current source, a first load, a second load, and a plurality of sets of input pair tubes;
each group of input pair tubes comprises a first input tube, a second input tube, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch, and the source electrodes of the first input tube and the second input tube are grounded through the current source; the grid electrode of the first input transistor is connected with an inverted input signal through the first switch, is connected with a common-mode signal through the second switch, and the drain electrode of the first input transistor is connected with a power supply voltage through the first load; the grid electrode of the second input transistor is connected with a positive input signal through the third switch, the common-mode signal through the fourth switch, and the drain electrode of the second input transistor is connected with the power supply voltage through the second load; the fifth switch is connected in series with the branch where the first input tube is located, the sixth switch is connected in series with the branch where the second input tube is located, control ends of the fifth switch and the sixth switch are connected with the trimming signal, and the size of the input tube connected into the comparison module is adjusted based on the control of the trimming signal;
the first switch and the third switch receive a first switch signal, the second switch and the fourth switch receive a second switch signal, and the first switch signal and the second switch signal are inverse signals.
Optionally, the difference operation module includes a first subtraction unit and a second subtraction unit;
the positive phase input end of the first subtraction operation unit is connected with the negative phase output end of the comparison module, and the negative phase input end of the first subtraction operation unit is connected with the positive phase output end of the comparison module and outputs a first mismatch signal;
and the positive phase input end of the second subtraction operation unit is connected with the positive phase output end of the comparison module, and the negative phase input end of the second subtraction operation unit is connected with the negative phase output end of the comparison module to output a second mismatch signal.
Optionally, the voltage-controlled oscillation module includes a first voltage-controlled oscillator and a second voltage-controlled oscillator;
the first voltage controlled oscillator receives the first mismatch signal and generates the first oscillation signal, wherein the frequency of the first oscillation signal is proportional to the magnitude of the first mismatch signal;
the second voltage controlled oscillator receives the second mismatch signal and generates the second oscillation signal, wherein a frequency of the second oscillation signal is proportional to a magnitude of the second mismatch signal.
Optionally, the counting module includes a first counter and a second counter;
the first counter receives the first oscillating signal and counts the first oscillating signal;
and the second counter receives the second oscillating signal and counts the second oscillating signal.
Optionally, the digital control module further receives an offset calibration threshold, and ends calibration of the offset voltage when an absolute value of a difference between the first count value and the second count value is less than or equal to the offset calibration threshold.
To achieve the above and other related objects, the present invention provides a method for suppressing an offset voltage of a comparator, the method at least comprising:
1) the common-mode signal is received by a positive phase input end and a negative phase input end of a comparison module, the comparison module outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals which are mismatched and output by the comparison module;
2) quantizing the first mismatch signal and the second mismatch signal respectively to obtain a first count value and a second count value;
3) and judging the polarity and the magnitude of the offset voltage based on the difference value of the first counting value and the second counting value, and generating a corresponding control signal to modify the load magnitude or the input tube dimension of the comparison module so as to calibrate the offset voltage of the comparison module.
Optionally, in step 1), the positive phase output signal is subtracted from the negative phase output signal of the comparing module to obtain a first mismatch signal, and the negative phase output signal is subtracted from the positive phase output signal of the comparing module to obtain a second mismatch signal.
Optionally, the method for quantizing the first mismatch signal and the second mismatch signal in step 2) includes:
generating a first oscillation signal and a second oscillation signal based on the first mismatch signal and the second mismatch signal, respectively; counting the first oscillation signal and the second oscillation signal within a preset time respectively to quantify output mismatch of the comparison module.
Optionally, the relationship between the offset voltage and the first and second count values satisfies:
（VOP-VON）=K*（N2- N1）；
the VOP is a positive phase output signal of the comparison module, the VON is a negative phase output signal of the comparison module, the N2 is a count value corresponding to a second mismatch signal obtained by subtracting the negative phase output signal from the positive phase output signal of the comparison module, the N1 is a count value corresponding to a first mismatch signal obtained by subtracting the positive phase output signal from the negative phase output signal of the comparison module, and K is a real number greater than zero.
More optionally, the method for suppressing the offset voltage of the comparator further comprises adding a step 4) before the step 3): and comparing the absolute value of the difference value of the first count value and the second count value with an offset calibration threshold value, and finishing the calibration of the offset voltage when the absolute value of the difference value of the first count value and the second count value is less than or equal to the offset calibration threshold value.
As described above, the comparator for suppressing offset voltage and the method for suppressing offset voltage of the comparator according to the present invention have the following advantages:
the comparator for inhibiting the offset voltage and the method for inhibiting the offset voltage of the comparator are fully automatic, the consumed area is small, the occupied time is short, and the influence on the bandwidth of the comparator is very small; meanwhile, the method for inhibiting the offset voltage of the comparator can be executed when the chip is powered on, so that even if the offset voltage changes along with the aging of the device, the offset voltage can be eliminated by the method, namely the drift of the offset voltage can be tracked.
Drawings
Fig. 1 is a schematic diagram of a comparator for suppressing offset voltage according to the present invention.
Fig. 2 is a schematic diagram of another structure of the offset voltage suppressing comparator according to the present invention.
FIG. 3 is a flow chart illustrating a method for suppressing the offset voltage of the comparator according to the present invention.
Description of the element reference numerals
1-a comparator to suppress the offset voltage; 11-a comparison module; 12-a differential operation module; 121-a first subtraction unit; 122-a second subtraction unit; 13-a voltage controlled oscillation module; 131-a first voltage controlled oscillator; 132-a second voltage controlled oscillator; 14-a counting module; 141-a first counter; 142-a second counter; 15-a digital control module; 16-a decoding module.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to fig. 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present embodiment provides a comparator 1 for suppressing an offset voltage, where the comparator 1 for suppressing an offset voltage includes:
the device comprises a comparison module 11, a difference operation module 12, a voltage-controlled oscillation module 13, a counting module 14, a digital control module 15 and a decoding module 16.
As shown in fig. 1, the comparison module 11 is used for comparing input signals.
Specifically, in this embodiment, the comparator 1 for suppressing the offset voltage calibrates the offset voltage by adjusting the load of the comparing module 11. As an example, the comparing module 11 includes a first input tube MN1, a second input tube MN2, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a current source MN3, a first adjustable load R1, and a second adjustable load R2. The source of the current source MN3 is grounded, the gate is connected to a bias voltage (not shown), and the drain is connected to the first input transistor MN1 and the second input transistor MN 2. The source of the first input tube NM1 is connected to the drain of the current source MN 3; the drain of the first input tube NM1 is connected to a power supply voltage via the first adjustable load R1, and the drain of the first input tube NM1 outputs the non-inverted output signal VOP of the comparing module 11; the gate of the first input tube NM1 is connected to an inverted input signal INN via the first switch K1 and also connected to a common mode signal VCM via the second switch K2. The source of the second input tube NM2 is connected to the drain of the current source MN 3; the drain of the second input tube NM2 is connected to the power voltage via the second adjustable load R2, and the drain of the second input tube NM2 outputs the inverted output signal VON of the comparing module 11; the gate of the second input tube NM2 is connected to the non-inverting input signal INP via the third switch K3, and is also connected to the common mode signal VCM via the fourth switch K4. The first switch K1 and the third switch K3 receive a first switch signal Calb, the second switch K2 and the fourth switch K4 receive a second switch signal calc, and the first switch signal Calb and the second switch signal calc are inverse signals. Wherein the first adjustable load R1 and the second adjustable load R2 each may comprise a series-parallel connection of a plurality of resistors; as an example, each of the first adjustable load R1 and the second adjustable load R2 includes a plurality of resistors connected in parallel, each of the resistors is connected in series to a switch, the switch receives the trimming signal output by the decoding module 16, and the number of the resistors connected to the comparing module 11 is adjusted by selecting the corresponding switch, thereby adjusting the load size; as another example, each of the first adjustable load R1 and the second adjustable load R2 includes a plurality of resistors connected in series, each resistor is connected in parallel with a switch, the switches receive the trimming signal output by the decoding module 16, and the number of the resistors connected to the comparing module 11 is adjusted by selecting the corresponding switch, thereby achieving adjustment of the load size; any circuit structure capable of realizing adjustable load is suitable for the present invention, and is not described herein.
It should be noted that, in this embodiment, the current source MN3 is implemented by an NMOS transistor, and any device capable of providing a current source is suitable in practical use. In this embodiment, the first input tube MN1 and the second input tube MN2 are NMOS tubes, and in actual use, the circuit connection relationship can be adjusted adaptively by replacing or using other types of devices, such as a PMOS tube, an NPN transistor, and a PNP transistor, which is not limited to this embodiment.
As shown in fig. 1, the differential operation module 12 is connected to the output end of the comparison module 11 and outputs a first mismatch signal and a second mismatch signal, where the first mismatch signal and the second mismatch signal are differential signals output by the comparison module 11 and mismatched.
Specifically, in the present embodiment, the difference operation module 12 includes a first subtraction unit 121 and a second subtraction unit 122. The positive phase input end of the first subtraction unit 121 is connected to the inverted output signal VON of the comparison module 11, the inverted input end is connected to the positive phase output signal VOP of the comparison module 11, and a first mismatch signal (VON-VOP) is output after subtraction. The positive phase input end of the second subtraction unit 122 is connected to the positive phase output signal VOP of the comparison module 11, the negative phase input end is connected to the negative phase output signal VON of the comparison module 11, and a second mismatch signal (VOP-VON) is output after subtraction.
It should be noted that any circuit structure capable of acquiring the first mismatch signal (VON-VOP) and the second mismatch signal (VOP-VON) is applicable to the present invention, and is not limited to this embodiment.
As shown in fig. 1, the voltage controlled oscillation module 13 is connected to the output end of the differential operation module 12, and generates a first oscillation signal VCO1 and a second oscillation signal VCO2 based on the output signal of the differential operation module 12.
Specifically, in the present embodiment, the voltage controlled oscillation module 13 includes a first voltage controlled oscillator 131 and a second voltage controlled oscillator 132. The first voltage controlled oscillator 131 is connected to the output of the first subtraction unit 121 and generates a corresponding first oscillation signal VCO1 based on the first mismatch signal (VON-VOP). The second voltage controlled oscillator 132 is connected to the output of the second subtraction unit 122 and generates a corresponding second oscillating signal VCO2 based on the second mismatch signal (VOP-VON). The frequency of the first oscillating signal VCO1 is proportional (set as needed, directly or inversely proportional) to the first mismatch signal (VON-VOP), and the frequency of the second oscillating signal VCO2 is proportional (consistent with the relationship between the first oscillating signal and the first mismatch signal) to the second mismatch signal (VOP-VON).
As shown in fig. 1, the counting module 14 is connected to the output terminal of the voltage-controlled oscillation module 13 and counts the first oscillation signal VCO1 and the second oscillation signal VCO2 respectively within a preset time period.
Specifically, the counting module 14 includes a first counter 141 and a second counter 142. The first counter 141 is connected to the output end of the first voltage controlled oscillator 131, and counts the first oscillation signal VCO1 within a preset time period to obtain a first count value N1. The second counter 142 is connected to the output end of the second voltage-controlled oscillator 132, and counts the second oscillating signal VCO2 within a preset time period to obtain a second count value N2.
It should be noted that the mismatch of the output of the comparison module 11 is quantified based on the vco module 13 and the counting module 14. Meanwhile, due to the existence of the first counter 141 and the second counter 142, the polarity of the output mismatch of the comparison module 11 can be judged according to the relative sizes of the two count values, so that the trimming is convenient, in addition, the performance deviation (including but not limited to power supply, temperature and process) of the oscillator caused by some common factors can be eliminated, and further, the quantization precision of the output mismatch of the comparison module 11 is prevented from being influenced by the performance deviation.
As shown in fig. 1, the digital control module 15 is connected to the output end of the counting module 14, determines the polarity and magnitude of the offset voltage based on the difference between the first count value N1 and the second count value N2, and generates a corresponding control signal.
Specifically, in this embodiment, the relationship between the offset voltage and the first and second count values N1 and N2 satisfies:
（Vop-Von）=K*（N2- N1）；
vop is a positive phase output signal of the comparison module 11, Von is a negative phase output signal of the comparison module 11, N2 is the second count value, N1 is the first count value, K is a real number greater than zero, and the value of K can be set based on the offset voltage range and accuracy to be actually detected.
In particular, it is emphasized that the mismatch voltage cannot be calibrated to zero due to the accuracy of the analog circuit, and it is only necessary to ensure that the offset voltage is calibrated to not affect the accuracy of the ADC during practical use. Therefore, as another implementation manner of the present invention, a setting value, namely an offset calibration threshold, is introduced, the offset calibration threshold is defined as a minimum level to which an offset voltage needs to be calibrated, and is denoted as ∈, when an absolute value of a difference between the first count value N1 and the second count value N2 is less than or equal to the offset calibration threshold ∈, calibration of the offset voltage is ended, and a current trimming signal is retained through a register.
As shown in fig. 1, the decoding module 16 is connected to the output end of the digital control module 15, decodes the control signal to obtain a trimming signal, trims the load of the comparison module 11 based on the trimming signal, and further calibrates the offset voltage of the comparison module 11.
Specifically, the decoding module 16 may be disposed outside the digital control module 15, or may be disposed inside the digital control module 15 (the functions of digital control and decoding are realized by the same functional module), which is not limited in this embodiment.
Example two
As shown in fig. 2, the present embodiment provides a comparator 1 for suppressing an offset voltage, which is different from the first embodiment in that the comparator 1 for suppressing an offset voltage calibrates an offset voltage by adjusting the size of an input tube of the comparison module 11.
As shown in fig. 2, the comparing module 11 includes, as an example, a plurality of input pair transistors, a current source MN3, a first load r1 and a second load r 2.
Specifically, each pair of input pair transistors includes a first input transistor MN1, a second input transistor MN2, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch (not shown), and a sixth switch (not shown). The connection relationship and the received switching signals of the first input tube MN1, the second input tube MN2, the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 are the same as those in the first embodiment, and are not described herein. The fifth switch is connected in series with the branch of the first input tube MN1, for example, the drain of the first input tube MN 1; the sixth switch is connected in series with the branch of the second input tube MN2, for example, the drain of the second input tube MN 2; the control ends of the fifth switch and the sixth switch are connected with the trimming signal, and the size of an input tube connected into the comparison module 11 is adjusted based on the control of the trimming signal. Each group of input geminate transistors are in parallel connection, each group of input geminate transistors are selected by switching on and off of the fifth switch and the sixth switch in each group, and the size of the input geminate transistors is adjusted by changing the number of the input geminate transistors which are connected in parallel.
Specifically, the first load r1 and the second load r2 are resistors, and the resistance values are not controlled by the trimming signal.
It should be noted that any way of adjusting the size of the input pair tube is applicable to the present invention, and is not limited to this embodiment. Other structures and working principles of the present invention are the same as those of the first embodiment, and are not described in detail herein.
EXAMPLE III
As shown in fig. 3, in this embodiment, the method for suppressing the offset voltage of the comparator is implemented by the comparator 1 for suppressing the offset voltage according to the first embodiment or the second embodiment, and any hardware circuit or software code capable of implementing the method of the present invention is suitable for the present invention in practical use. The method for inhibiting the offset voltage of the comparator comprises the following steps:
1) the common-mode signal is received by a positive phase input end and a negative phase input end of a comparison module, the comparison module outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals which are mismatched and output by the comparison module.
Specifically, if the second switch signal Cal is set to a high level, the first switch signal Calb is set to a low level, and both the positive phase input end and the negative phase input end of the comparison module 11 receive the common mode signal VCM. If there is no mismatch in the input tube and/or load (i.e. there is no mismatch in the comparison module 11), the comparison module 11 outputs a difference value (VOP-VON) equal to 0, and since manufacturing mismatch is unavoidable, the output (VOP-VON) is generally not 0, which is the mismatch voltage of the output, defined as (VOP-VON) = Δ Vo.
Specifically, in order to facilitate subsequent trimming, the present invention obtains the differential signal with mismatched output from the comparison module 11. As an example, the positive phase output signal VOP is subtracted from the negative phase output signal VON of the comparison module 11 to obtain a first mismatch signal (VON-VOP), and the negative phase output signal VON is subtracted from the positive phase output signal VOP of the comparison module 11 to obtain a second mismatch signal (VOP-VON).
2) And quantizing the first mismatch signal and the second mismatch signal respectively to obtain a first count value and a second count value.
Specifically, in the present embodiment, a first oscillation signal VCO1 is generated based on the first mismatch signal (VON-VOP), and the frequency of the first oscillation signal VCO1 is proportional to the magnitude of the first mismatch signal (VON-VOP); generating a second oscillation signal VCO2 based on the second mismatch signal (VOP-VON), a frequency of the second oscillation signal VCO2 being proportional to a magnitude of the second mismatch signal (VOP-VON). Then, the first oscillation signal VCO1 and the second oscillation signal VCO2 are respectively counted within a preset time to obtain a first count value N1 and a second count value N2, so as to realize quantization of the output mismatch of the comparison module 11.
3) The polarity and magnitude of the offset voltage are determined based on the difference between the first count value N1 and the second count value N2, and a corresponding control signal is generated to modify the load magnitude or the input tube size of the comparison module 11, so as to calibrate the offset voltage of the comparison module 11.
Specifically, in this embodiment, the relationship between the offset voltage and the first and second count values N1 and N2 satisfies:
（VOP-VON）=K*（N2- N1）。
specifically, the method further includes the step of decoding the control signal to obtain a trimming signal, so as to trim the load size or the input pipe size of the comparison module 11.
As shown in fig. 3, as another implementation of the present invention, the offset calibration threshold epsilon is first set before step 1), and then step 4) is added before step 3): comparing the absolute value of the difference of the first count value N1 and the second count value N2 to a misalignment calibration threshold ε; ending the calibration of the offset voltage if the absolute value of the difference between the first count value N1 and the second count value N2 is less than or equal to the offset calibration threshold ε; calibrating an offset voltage if an absolute value of a difference between the first count value N1 and the second count value N2 is greater than the offset calibration threshold ε. When calibration is started, | N2-N1| is generally larger than epsilon, as the calibration is carried out, the size of a load or an input pipe is trimmed, output offset is gradually reduced, | N2-N1| is reduced, then | N2-N1| is judged whether to be reduced to be smaller than or equal to epsilon, if the output offset is larger than epsilon, the load or the size of the input pipe is continuously trimmed until | N2-N1| is smaller than or equal to epsilon, calculation convergence is carried out, the calibration is finished, and the calibration value is stored in a register for being used in the subsequent work of a comparator.
The comparator for inhibiting the offset voltage and the method for inhibiting the offset voltage of the comparator have the advantages that the calibration process is completely and automatically carried out, any artificial interruption participation and signal injection are not needed, and all digital circuits are used for quantifying the offset and controlling the feedback, so that the static power consumption is avoided, and the area is very small. In addition, the calibration method does not introduce a large capacitor at the load end, has little influence on the bandwidth of the comparator, does not need to additionally spend one phase to store offset before the comparison of the comparator every time, and only needs to execute one-time calibration before the chip leaves a factory or when a user powers on, thereby saving time.
In summary, the present invention provides a comparator for suppressing an offset voltage and a method for suppressing an offset voltage of the comparator, including: the comparison module is used for comparing the input signals; the differential operation module is connected with the output end of the comparison module and outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals output by the comparison module and mismatched; the voltage-controlled oscillation module is connected with the output end of the differential operation module and generates a first oscillation signal and a second oscillation signal based on the first mismatch signal and the second mismatch signal respectively; the counting module is connected with the output end of the voltage-controlled oscillation module and is used for respectively counting the first oscillation signal and the second oscillation signal within a preset time period to obtain a first counting value and a second counting value; the digital control module is connected with the output end of the counting module, judges the polarity and the magnitude of the offset voltage based on the difference value of the first counting value and the second counting value and generates a corresponding control signal; and the decoding module is connected with the output end of the digital control module, decodes the control signal to obtain a trimming signal, trims the load size or the input tube size of the comparison module based on the trimming signal, and further calibrates the offset voltage of the comparison module. The common-mode signal is received by a positive phase input end and a negative phase input end of a comparison module, the comparison module outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals which are mismatched and output by the comparison module; quantizing the first mismatch signal and the second mismatch signal respectively to obtain a first count value and a second count value; and judging the polarity and the magnitude of the offset voltage based on the difference value of the first counting value and the second counting value, and generating a corresponding control signal to modify the load magnitude or the input tube dimension of the comparison module so as to calibrate the offset voltage of the comparison module. The comparator for inhibiting the offset voltage and the method for inhibiting the offset voltage of the comparator are fully automatic, the consumed area is small, the occupied time is short, and the influence on the bandwidth of the comparator is very small; meanwhile, the method for inhibiting the offset voltage of the comparator can be executed when the chip is powered on, so that even if the offset voltage changes along with the aging of the device, the offset voltage can be eliminated by the method, namely the drift of the offset voltage can be tracked. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A comparator for suppressing an offset voltage is characterized by comprising:
the comparison module is used for comparing the input signals;
the differential operation module is connected with the output end of the comparison module and outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals output by the comparison module and mismatched;
the voltage-controlled oscillation module is connected with the output end of the differential operation module and generates a first oscillation signal and a second oscillation signal based on the first mismatch signal and the second mismatch signal respectively;
the counting module is connected with the output end of the voltage-controlled oscillation module and is used for respectively counting the first oscillation signal and the second oscillation signal within a preset time period to obtain a first counting value and a second counting value;
the digital control module is connected with the output end of the counting module, judges the polarity and the magnitude of the offset voltage based on the difference value of the first counting value and the second counting value and generates a corresponding control signal;
and the decoding module is connected with the output end of the digital control module, decodes the control signal to obtain a trimming signal, trims the load size or the input tube size of the comparison module based on the trimming signal, and further calibrates the offset voltage of the comparison module.
2. The offset voltage suppressing comparator as claimed in claim 1, wherein: when the load of the comparison module is modified by the modification signal, the comparison module comprises a first input tube, a second input tube, a first switch, a second switch, a third switch, a fourth switch, a current source, a first adjustable load and a second adjustable load;
the source electrodes of the first input tube and the second input tube are grounded through the current source; the grid electrode of the first input tube is connected with an inverted input signal through the first switch, is connected with a common-mode signal through the second switch, and the drain electrode of the first input tube is connected with a power supply voltage through the first adjustable load; the grid electrode of the second input tube is connected with a positive-phase input signal through the third switch, the common-mode signal through the fourth switch, and the drain electrode of the second input tube is connected with the power supply voltage through the second adjustable load; the first adjustable load and the second adjustable load adjust the load size based on the control of the trimming signal;
the first switch and the third switch receive a first switch signal, the second switch and the fourth switch receive a second switch signal, and the first switch signal and the second switch signal are inverse signals.
3. The offset voltage suppressing comparator as claimed in claim 1, wherein: when the input tube size of the comparison module is modified by the modification signal, the comparison module comprises a current source, a first load, a second load and a plurality of groups of input pair tubes;
each group of input pair tubes comprises a first input tube, a second input tube, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch, and the source electrodes of the first input tube and the second input tube are grounded through the current source; the grid electrode of the first input tube is connected with an inverted input signal through the first switch, is connected with a common-mode signal through the second switch, and the drain electrode of the first input tube is connected with a power supply voltage through the first load; the grid electrode of the second input tube is connected with a positive-phase input signal through the third switch, the common-mode signal through the fourth switch, and the drain electrode of the second input tube is connected with the power supply voltage through the second load; the fifth switch is connected in series with the branch where the first input tube is located, the sixth switch is connected in series with the branch where the second input tube is located, control ends of the fifth switch and the sixth switch are connected with the trimming signal, and the size of the input tube connected into the comparison module is adjusted based on the control of the trimming signal;
the first switch and the third switch receive a first switch signal, the second switch and the fourth switch receive a second switch signal, and the first switch signal and the second switch signal are inverse signals.
4. The offset voltage suppressing comparator as claimed in claim 1, wherein: the difference operation module comprises a first subtraction operation unit and a second subtraction operation unit;
the positive phase input end of the first subtraction operation unit is connected with the negative phase output end of the comparison module, and the negative phase input end of the first subtraction operation unit is connected with the positive phase output end of the comparison module and outputs a first mismatch signal;
and the positive phase input end of the second subtraction operation unit is connected with the positive phase output end of the comparison module, and the negative phase input end of the second subtraction operation unit is connected with the negative phase output end of the comparison module to output a second mismatch signal.
5. The offset voltage suppressing comparator as claimed in claim 1, wherein: the voltage-controlled oscillation module comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator;
the first voltage controlled oscillator receives the first mismatch signal and generates the first oscillation signal, wherein the frequency of the first oscillation signal is proportional to the magnitude of the first mismatch signal;
the second voltage controlled oscillator receives the second mismatch signal and generates the second oscillation signal, wherein a frequency of the second oscillation signal is proportional to a magnitude of the second mismatch signal.
6. The offset voltage suppressing comparator as claimed in claim 1, wherein: the counting module comprises a first counter and a second counter;
the first counter receives the first oscillating signal and counts the first oscillating signal;
and the second counter receives the second oscillating signal and counts the second oscillating signal.
7. The offset voltage suppressing comparator as claimed in claim 1, wherein: the digital control module also receives an offset calibration threshold value, and ends the calibration of the offset voltage when the absolute value of the difference value of the first count value and the second count value is less than or equal to the offset calibration threshold value.
8. A method for suppressing offset voltage of a comparator is characterized by at least comprising the following steps:
1) the common-mode signal is received by a positive phase input end and a negative phase input end of a comparison module, the comparison module outputs a first mismatch signal and a second mismatch signal, and the first mismatch signal and the second mismatch signal are differential signals which are mismatched and output by the comparison module;
2) generating a first oscillation signal and a second oscillation signal based on the first mismatch signal and the second mismatch signal respectively, and counting the first oscillation signal and the second oscillation signal respectively within a preset time to obtain a first count value and a second count value so as to quantify the output mismatch of the comparison module;
3) and judging the polarity and the magnitude of the offset voltage based on the difference value of the first counting value and the second counting value, and generating a corresponding control signal to modify the load magnitude or the input tube dimension of the comparison module so as to calibrate the offset voltage of the comparison module.
9. The method of claim 8, wherein: in the step 1), the positive phase output signal is subtracted from the negative phase output signal of the comparison module to obtain a first mismatch signal, and the negative phase output signal is subtracted from the positive phase output signal of the comparison module to obtain a second mismatch signal.
10. The method of claim 8, wherein: the relation between the offset voltage and the first and second count values satisfies:
（VOP-VON）=K*（N2- N1）；
the VOP is a positive phase output signal of the comparison module, the VON is a negative phase output signal of the comparison module, the N2 is a count value corresponding to a second mismatch signal obtained by subtracting the negative phase output signal from the positive phase output signal of the comparison module, the N1 is a count value corresponding to a first mismatch signal obtained by subtracting the positive phase output signal from the negative phase output signal of the comparison module, and K is a real number greater than zero.
11. The method for suppressing the offset voltage of the comparator according to any one of claims 8-10, wherein: the method for inhibiting the offset voltage of the comparator further comprises the step 4) added before the step 3): and comparing the absolute value of the difference value of the first count value and the second count value with an offset calibration threshold value, and finishing the calibration of the offset voltage when the absolute value of the difference value of the first count value and the second count value is less than or equal to the offset calibration threshold value.
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