CN105634425B - Automatic configuration method for electronic system and operational amplifier - Google Patents
Automatic configuration method for electronic system and operational amplifier Download PDFInfo
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- CN105634425B CN105634425B CN201410598838.5A CN201410598838A CN105634425B CN 105634425 B CN105634425 B CN 105634425B CN 201410598838 A CN201410598838 A CN 201410598838A CN 105634425 B CN105634425 B CN 105634425B
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Abstract
The invention provides an electronic system and an automatic configuration method of an operational amplifier, which are suitable for the operational amplifier arranged in the electronic system. The method comprises the following steps: estimating an internal resistance value of the electronic system; estimating an operating frequency of the electronic system; determining a control parameter according to the internal resistance value and the operating frequency to adjust a characteristic of the operational amplifier. Therefore, the operational amplifier can automatically detect the operating frequency of the system under different operating clocks, and adjust the characteristic parameters of the operational amplifier to optimize the performance of the analog/digital converter.
Description
Technical Field
The present invention relates to an electronic system, and more particularly, to an electronic system having an operational amplifier with a self-tuning mechanism.
Background
The performance of an electronic device may be affected by variations in many source parameters, in which case many electronic device characteristics, such as gain, noise figure (noise figure), accuracy … of output power, current or voltage, etc., may be affected accordingly. The variation of these parameters may be caused by the process, temperature or other factors of the device.
Analog-to-Digital converters (Analog-to-Digital converters) play a very important role in many applications (e.g., scan graphics systems, computer systems, Digital televisions, and biomedical electronics) that require signal converters with high speed, high resolution, and low power consumption, the most important core circuit in the Analog-to-Digital Converter is an operational amplifier, and when the Analog-to-Digital Converter operates at different clock speeds, the characteristic parameters required by the operational amplifier, such as the direct current voltage (DC-Gain), the Gain bandwidth product (Gain bandwidth product), and the slew rate (slew rate) change accordingly. When the application system operates at a relatively low clock, the adc consumes additional power and the parameters may not be set to optimize the performance of the adc.
Disclosure of Invention
In order to solve the problem that the operational amplifier has different circuit characteristics under different operation clocks, the present invention provides an operational amplifier with a self-calibration mechanism, which can automatically detect the operating frequency of the system and adjust the characteristic parameters of the operational amplifier.
In an embodiment of the present invention, after the operational amplifier determines the operating frequency of the system, the operational amplifier obtains the control parameters of the operational amplifier by using a look-up table (lut) circuit, so as to optimize the performance of the operational amplifier.
An embodiment of the present invention is an automatic configuration method of an operational amplifier, which is suitable for an operational amplifier disposed in an electronic system. The method comprises the following steps: estimating an internal resistance value of the electronic system; estimating an operating frequency of the electronic system; determining a control parameter according to the internal resistance value and the operating frequency to adjust a characteristic of the operational amplifier.
Another embodiment of the present invention is an electronic system capable of automatically adjusting an operational amplifier in the electronic system. The electronic system further comprises a resistance correction circuit, a frequency estimation circuit and a look-up table circuit. The resistance correction circuit is used for estimating an internal resistance value of the electronic system and generating a first control signal. The frequency estimation circuit adjusts a capacitance value of a capacitance resistor according to the internal resistance value and a clock signal of the electronic system, and generates a corresponding second control signal. And the table look-up circuit receives the first control signal and the second control signal and obtains a control parameter of the operational amplifier through a table look-up method. The operational amplifier receives the control parameter to adjust a characteristic of the operational amplifier.
The invention has the beneficial technical effects that: the invention can make the operational amplifier automatically detect the operation frequency of the system under different operation time pulse, and adjust the characteristic parameter of the operational amplifier to optimize the performance of the analog/digital converter.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for automatic configuration operation of an operational amplifier according to the present invention.
FIG. 2 is a diagram of an electronic system with an operational amplifier with a self-tuning mechanism according to the present invention.
FIG. 3 is a circuit diagram of an electronic system with an operational amplifier having a self-tuning mechanism according to another embodiment of the present invention.
FIG. 4 is a flowchart of a method of resistance calibration according to an embodiment of the present invention.
FIG. 5 is a circuit diagram of an electronic system with an operational amplifier having a self-tuning mechanism according to another embodiment of the present invention.
FIG. 6A is a flowchart illustrating a frequency estimation method according to an embodiment of the invention.
FIG. 6B is a flowchart illustrating a frequency estimation method according to another embodiment of the present invention.
FIG. 6C is a flowchart illustrating a frequency estimation method according to another embodiment of the present invention.
Fig. 7 is a waveform diagram illustrating the operation of the circuit of fig. 5.
FIG. 8 is a circuit diagram of an embodiment of a two-stage operational amplifier.
Fig. 9 is a circuit diagram of a circuit capable of adjusting voltage gain and bandwidth gain.
FIG. 10 is a circuit diagram of a circuit for adjusting slew rate.
Reference numerals
21-a resistance correction circuit;
22-frequency estimation circuit;
23-a table look-up circuit;
24-an operational amplifier;
30-an electronic system;
31-bandgap circuit;
32. 52-resistor group;
33-a counter;
51-a charging time estimation unit;
53-capacitor bank;
81. 83-circuit;
82-a common mode feedback circuit;
0 to a first control signal;
0-a second control signal;
bp0, bn0, bn 1-end points;
C. cc to capacitance;
cal _ out, Cal _ out 1, Cal _ out 2, Cal _ out 3;
CLK to a clock signal;
CMFB-common mode feedback voltage;
i1, I2, IB-current;
outn, outp output signal;
pre _ outn, Pre _ outp to the preceding stage output signal;
s11, S13, S15, S41, S42, S601 to S603, S611 to S613, S621 to S628;
sc-control signal;
t301, T30N-switch;
r, R1, R51, R301, R30N-resistor;
v1, V2, V3-charging voltage;
Vbias-a bias voltage;
Vbg-a bandgap voltage;
vc-voltage;
VINN, VINP-input voltage;
Vref-a reference voltage.
Detailed Description
FIG. 1 is a flow chart of an embodiment of a method for auto-configuration of an operational amplifier according to the present invention. In the present embodiment, the operational amplifier is configured in an electronic system or circuit, such as a filter, an analog-to-digital converter circuit, a chip, or a handheld electronic device. In step S11, a controller or a control circuit in the electronic system first estimates an equivalent internal resistance of the electronic system. The electronic system includes an operational amplifier, a bandgap circuit and a current mirror circuit. The electronic system is coupled to an external resistor, and the resistance value of the external resistor is known. After the electronic system is started, the bandgap voltage output by the bandgap circuit is stable and is not easy to drift with voltage, temperature or process parameter (process drift), so that the bandgap voltage can be used to estimate the internal resistance of the electronic system.
Next, in step S12, when the internal resistance of the electronic system is determined, the operating frequency of the electronic system is estimated. In one embodiment, the operating frequency of the electronic system is not actually measured, but rather the equivalent capacitance of the capacitor bank is found out from the operating frequency of the electronic system corresponding to the operating frequency. Then, in steps S13 and S15, when the operating frequency of the electronic system is known, the control parameter of the operational amplifier is known through a look-up table circuit according to the operating frequency and the internal resistance of the electronic system. In one embodiment, after the operating frequency of the electronic system is determined, a capacitance value of a capacitor bank (capacitor bank) in the electronic system is estimated, and a control parameter of the operational amplifier is obtained through a look-up table circuit according to the resistance value and the capacitance value.
FIG. 2 is a diagram of an electronic system with an operational amplifier with a self-tuning mechanism according to the present invention. The electronic system includes a resistance calibration circuit 21, a frequency estimation circuit 22, a lookup table circuit 23 and an operational amplifier 24.
When the electronic system is turned on, reset or receives a control signal to adjust the control parameter of the operational amplifier 24, the resistance correction circuit 21 estimates an internal resistance value of the electronic system through a resistor bank (resistor bank) in the electronic system. Then, the frequency estimation circuit 22 measures the operating frequency of the electronic system. In one embodiment, after the operating frequency of the electronic system is known, a capacitance value corresponding to a capacitor bank (capacitor bank) in the electronic system is further estimated. Specifically, when the resistance and the capacitance are measured, a first control signal and a second control signal for estimating the resistance and the capacitance can also be obtained. In one embodiment, the first control signal and the second control signal are digital signals, which are respectively represented by "N: 0" and "M: 0", wherein N, M is a positive integer, which respectively represents the number of resistors in the resistor group and the number of capacitors in the capacitor group.
The lookup table circuit 23 performs a lookup table according to the capacitance and the resistance or the first control signal and the second control signal to obtain the control parameter of the operational amplifier 24. The dc voltage gain, gain bandwidth product and slew rate of the operational amplifier 24 can be adjusted by these parameters. In addition, the operation current of the operational amplifier can be optimized through the self-adjusting mechanism.
FIG. 3 is a circuit diagram of an electronic system with an operational amplifier having a self-tuning mechanism according to another embodiment of the present invention. From another perspective, the electronic system 30 of FIG. 3 includes an operational amplifier, a bandgap circuit 31 and a resistance correction circuit 32. The bandgap circuit 31 is not easily disturbed by temperature and other variables, and therefore is suitable for providing a stable bandgap voltage. External resistance R1Has a known resistance value, and an external resistor R1The smaller the error of (2) is, the better, the error of 1% or 5% is recommended. In the present embodiment, the internal resistance of the electronic system is obtained by adjusting the resistance of the resistor group 32.
The current flowing through the external resistor R can be copied by the current mirror circuit1Current of (I)1To generate a current I flowing through the resistor group 322. The resistor bank 32 includes a plurality of switching devices, such as T301-T30N, and a plurality of resistors, such as R301～R30NThe switch device is controlled by the control signal "N: 0" to determine the equivalent resistance R of the resistor set 322. Using the Kirchhoff Circuit law (Kirchhoff Circuit laus), it can be expressed as follows:
Vbg＝I1x R1＝I2x R2
in the present embodiment, the equivalent resistance value R of the resistor group 322Is initially set to a minimum value, at which point VcWill be less than the energy gap voltage Vbg. The comparator will convert the voltage VcAnd energy gap voltage VbgThe comparison result is transmitted to the D-type flip-flop. The counter 33 will gradually increase the control signal "" N:0 "" by one bit according to the D-type flip-flop until the voltage Vc is larger than the bandgap voltage VbgIt is stopped. For an example, assume that there are 5 resistors in the resistor group 32, i.e. N equals to 5, and the binary proportional relationship of the resistance values of each resistor is the same. When the resistance value estimation is started, the control signal is "00001". If the voltage Vc is less than the energy gap voltage V at this timebgThe counter 33 increases the control signal to "00010" and determines whether the voltage Vc is greater than the bandgap voltage V according to the output of the D-type flip-flopbg. Suppose that when the control signal is "01111", the voltage Vc is larger than the bandgap voltage VbgThen, the equivalent resistance value R of the resistor group 322It can be known. In another embodiment, assuming that the control signal is "01111", the voltage Vc is greater than the bandgap voltage VbgThen the last determined control signal is the previous control signal "01110".
Similarly, the equivalent resistance value R of the resistor group 32 can also be set2Preset to the maximum value and then gradually decrease the equivalent resistance value R by the counter 332Until the voltage Vc is less than VbgIt is stopped. Or in another embodiment, the equivalent resistance value R of the resistor group 322Preset to an intermediate value according to the voltages Vc and VbgBy gradually decreasing or increasing the equivalent resistance value R2. In the foregoing manner, the equivalent resistance value of the last resistor group 32 is the internal resistance value of the electronic system.
FIG. 4 is a flowchart of a method of resistance calibration according to an embodiment of the present invention. Referring to fig. 3 and 4, in the present embodiment, the predetermined condition is that the electronic device or the system is executed only when the electronic device is turned on or reset, but in other embodiments, the resistance correction can be performed according to a correction request signal when the electronic device is operating. In step S41, an equivalent resistance value of the resistor group is determined. Next, in step S42, the bandgap voltage V is determinedbgWhether greater than a voltage Vc. If gap voltage VbgIf the resistance value is larger than Vc, the process returns to step S41 to adjust the equivalent resistance value of the resistor group. If gap voltage VbgAnd if the resistance is smaller than Vc, the resistance correction is finished.
When the internal resistance of the electronic system is determined, the RC charging and discharging method can be used to estimate the operation clock, the operation clock or the capacitance of the electronic system according to the following formula.
Vref＝Vdd×(1-e-Tclk/RC)
In which V isref: reference voltage
Vdd: operating voltage
Tclk: clock period
R: resistance value
C: capacitance value
Please refer to fig. 5. FIG. 5 is a circuit diagram of an electronic system with an operational amplifier having a self-tuning mechanism according to another embodiment of the present invention. From fig. 5, it can be seen that the reference voltage VrefCan be divided by a resistor R51And R52To decide. For the operation of the resistor group 52, please refer to the description of fig. 3. Since the resistance value of the resistor bank 52 has already been determined, it is next done to re-determine the capacitance value of the capacitor bank 53. The capacitor bank 53 includes a plurality of switching devices and a plurality of capacitors, and the switching devices are controlled by the control signal "M: 0" to determine the equivalent capacitance of the capacitor bank 53. The comparator outputs a voltage Vc and a reference voltage VrefThe charging time estimation unit 51 controls the capacitance of the capacitor bank 53 to determine whether the operating frequency of the electronic system is correctly estimated. In an embodiment of the invention, the operating frequency of the electronic system is not directly estimated, but the capacitance of the capacitor bank 53 corresponding to the operating frequency of the electronic system is estimated by fixing the clock width of the electronic system.
Fig. 7 is a waveform diagram illustrating the operation of the circuit of fig. 5. Referring to fig. 5 and 7, a clock width is first generated as a charging time by using a clock signal CLK known in the electronic system. In this embodiment, the clock width is 5 CLK cycles. In fig. 7, the charging voltages V1, V2, and V3 respectively represent the charging variation of the voltage Vc in fig. 5 under different conditions. Situation 71 indicates that the capacitance value of capacitor group 53 is too small. It can be seen from the figure that the charging voltage V1 is already greater than the reference voltage V before the end of the charging timerefThe output Cal _ out of the comparator is also pulled up to the high logic level. Therefore, in the case 71, the charging time estimation unit 51 adjusts the capacitance of the capacitor bank 53 by the control signal "M: 0".
Referring back to FIG. 5, when the capacitance of the capacitor 53 and the resistance of the resistor 52 are confirmed, the control signals "N: 0" and "M: 0" are transmitted to a lookup circuit, and the lookup circuit performs a lookup according to the received control signals "N: 0" and "M: 0" to obtain the control parameters of the operational amplifier. The operational amplifier adjusts the operational amplifier according to the control parameter, so that the power of the operational amplifier is optimized.
FIG. 6A is a flowchart illustrating a frequency estimation method according to an embodiment of the invention. The frequency estimation method of the present embodiment is not used to estimate an actual frequency value, but to estimate whether the capacitance of a capacitor bank corresponds to the actual operating frequency value. Please refer to the circuit diagram of fig. 5 together with the frequency estimation method of fig. 6A to 6C. When the frequency estimation method is performed, a clock width is first generated by using the operation clock in the electronic system as the charging time. In step S601, the capacitance of a capacitor bank is first trimmed. In this step, the capacitance of the capacitor bank may be set to a predetermined value, such as the maximum capacitance or the minimum capacitance.
In step S602, the charging time estimation unit 51 determines whether the time point when the output Cal _ out is pulled up to the high logic level is less than the end point of the charging time, as shown in the condition 71 in fig. 7. If so, the process returns to step S601 to perform fine adjustment on the capacitance value of the capacitor bank 53. If not, step S603 is performed. In step S603, the charging time estimation unit 51 determines whether the time difference between the time point when the output Cal _ out is pulled up to the high logic level and the end point of the charging interval is greater than the length of one operation clock cycle. If so, go back to step S601 to fine-tune the capacitance value of the capacitor bank 53 again to reduce the capacitance value. If not, this indicates that the capacitance value of capacitor bank 53 at this time correctly corresponds to the operating frequency. The charging time estimation unit 51 will transmit the control signal of the capacitor set to a look-up table circuit or a control circuit for subsequent operations.
In the present embodiment, the control method of the capacitor bank 53 is similar to the control method of the resistor bank 32 in fig. 3, and thus, reference may be made to the resistance adjustment method of the resistor bank 32 in fig. 3 for the manner of adjusting the capacitance value of the capacitor bank 53.
FIG. 6B is a flowchart illustrating a frequency estimation method according to another embodiment of the present invention. When the frequency estimation method is performed, a clock width is first generated by using the operation clock in the electronic system as the charging time. In step S611, the capacitance of a capacitor bank is first trimmed. In this step, the capacitance of the capacitor bank may be set to a predetermined value, such as the maximum capacitance or the minimum capacitance.
In step S612, the charging time estimation unit 51 determines whether the time point when the output Cal _ out is pulled up to the high logic level is greater than the end point of the charging time, as shown in the condition 73 in fig. 7. If so, the process returns to step S611 to perform fine adjustment on the capacitance value of the capacitor bank 53. If not, step S613 is performed. In step S613, the charging time estimation unit 51 determines whether the time difference between the time point when the output Cal _ out is pulled up to the high logic level and the end point of the charging time is less than the length of one operation clock cycle. If not, the process returns to step S611 to perform fine adjustment on the capacitance value of the capacitor bank 53 again to increase the capacitance value. If so, this indicates that the capacitance value of capacitor bank 53 at this time correctly corresponds to the operating frequency. The charging time estimation unit 51 will transmit the control signal of the capacitor set to a look-up table circuit or a control circuit for subsequent operations.
FIG. 6C is a flowchart illustrating a frequency estimation method according to another embodiment of the present invention. When the frequency estimation method is performed, a clock width is first generated by using the operation clock in the electronic system as the charging time. In step S621, the capacitance of the capacitor bank is first set to a predetermined value, such as the maximum capacitance or the minimum capacitance. In step S622, it is determined whether the time point when the output Cal _ out of the comparator is pulled up to the high logic level is greater than the end point of the charging time, as shown in the condition 73 in fig. 7. If so, step S626 is performed to perform fine tuning on the capacitance value of the capacitor bank 53 to reduce the capacitance value of the capacitor bank. If not, step S623 is performed to fine tune the capacitance value of the capacitor bank 53 to increase the capacitance value of the capacitor bank.
In step S624, the charging time estimation unit 51 determines whether the time point when the output Cal _ out is pulled up to the high logic level is less than the end point of the charging time, as shown in the condition 71 in fig. 7. If so, the process returns to step S623 to fine-tune the capacitance of the capacitor bank 53. If not, step S625 is performed. In step S625, the charging time estimation unit 51 determines whether the time difference between the time point when the output Cal _ out is pulled up to the high logic level and the end point of the charging time is greater than one operation clock cycle length. If so, the process returns to step S623 to perform fine adjustment on the capacitance value of the capacitor bank 53 again to reduce the capacitance value. If not, this indicates that the capacitance value of capacitor bank 53 at this time correctly corresponds to the operating frequency. The charging time estimation unit 51 will transmit the control signal of the capacitor set to a look-up table circuit or a control circuit for subsequent operations.
In step S627, the charging time estimation unit 51 determines whether the time point when the output Cal _ out is pulled up to the high logic level is greater than the end point of the charging time, as shown in the condition 73 in fig. 7. If so, go back to step S626 to fine-tune the capacitance value of the capacitor bank 53. If not, step S628 is performed. In step S628, the charging time estimation unit 51 determines whether the time difference between the time point when the output Cal _ out is pulled up to the high logic level and the end point of the charging time is less than the length of one operation clock cycle. If not, the capacitance of the capacitor bank 53 is adjusted again to increase the capacitance in step S626. If so, this indicates that the capacitance value of capacitor bank 53 at this time correctly corresponds to the operating frequency. The charging time estimation unit 51 will transmit the control signal of the capacitor set to a look-up table circuit or a control circuit for subsequent operations.
Although the method or circuit described in the embodiments of the present invention is described above, the method and circuit in the embodiments can be combined with each other to form a new embodiment, which is not limited to the foregoing description.
FIG. 8 is a circuit diagram of an embodiment of a two-stage operational amplifier. In the above embodiment, the parameters obtained by the lookup table circuit are used to control the bias voltage VBiasAnd current IB. In one embodiment, the parameter is the control signal Sc shown in the figure, and the control signal Sc can be generated in the manner described with reference to fig. 1 or fig. 2. By adjusting the bias voltage VBiasAnd current IBThe DC voltage gain, gain bandwidth product and slew rate of the operational amplifier are adjusted. In addition, the operation of the operational amplifier can be optimized by the self-adjusting mechanism. In the embodiment, the circuit 81 can be used to adjust the gain bandwidth or the dc voltage gain, and the circuit 83 includes a common mode feedback circuit 82 for adjusting the slew rate. In other embodiments, the circuit 81 may be composed of a plurality of circuit modules (circuit modules), as shown in the circuit of fig. 9, to avoid that a single circuit 81 cannot correctly adjust the gain bandwidth or the dc voltage gain. Similarly, the circuit 83 may be composed of a plurality of circuit blocks, as shown in the circuit of fig. 10, to avoid the situation that a single circuit 83 cannot make the voltage rise to the predetermined voltage quickly. Note that, in the composition of the circuit 83, a plurality of circuit blocks shown in fig. 10 may be used, but only one common mode feedback circuit 82 is required.
Claims (8)
1. A method for automatically configuring an operational amplifier in an electronic system, the method comprising:
estimating an internal resistance of the electronic system, wherein the estimating the internal resistance of the electronic system is performed by adjusting a resistance of a resistor set in the electronic system, and recording a first control signal of the resistor set after the resistance of the resistor set is determined, wherein the estimating the internal resistance of the electronic system comprises:
generating a bandgap voltage by using a bandgap circuit;
generating a first current by using the energy gap voltage;
using a current mirror circuit to copy the first current to generate a second current;
generating a comparison voltage by using the second current to flow through the resistor group;
comparing the bandgap voltage with the comparison voltage;
when the energy gap voltage is larger than the comparison voltage, increasing the first control signal to increase the resistance value; and
when the energy gap voltage is not larger than the comparison voltage, recording the first control signal of the resistor group, wherein the resistance value is equal to the internal resistance value; estimating an operating frequency of the electronic system; and
determining a control parameter to adjust a characteristic of the operational amplifier according to the internal resistance value and the operating frequency, wherein the control parameter includes a bias current of the operational amplifier.
2. The method of claim 1, wherein estimating the operating frequency of the electronic system is performed by adjusting a capacitance of a capacitor bank in the electronic system, and recording a second control signal of the capacitor bank when the capacitance of the capacitor bank is determined.
3. The method of claim 2, wherein the control parameter is obtained by passing the first control signal and the second control signal through a look-up table circuit.
4. An electronic system for automatically adjusting an operational amplifier, the system comprising:
a resistance calibration circuit for estimating an internal resistance of the electronic system and generating a first control signal, wherein the resistance calibration circuit comprises:
the circuit comprises an energy gap circuit, a first current circuit and a second current circuit, wherein the energy gap circuit generates an energy gap voltage, and the energy gap voltage and an external resistor generate a first current;
a current mirror circuit for duplicating the first current to generate a second current;
a resistor set having a resistance value, wherein the resistor set adjusts the resistance value according to the first control signal, and wherein the second current flows through the resistor set to generate a comparison voltage;
a first comparator for comparing the bandgap voltage with the comparison voltage to generate a comparison result, wherein the comparison result is a first logic level when the bandgap voltage is greater than the comparison voltage, and wherein the comparison result is a second logic level when the bandgap voltage is not greater than the comparison voltage; and
a counter for adjusting the first control signal according to the comparison result, wherein the counter increments the first control signal to increment the resistance value when the comparison result is the first logic level, wherein the counter stops adjusting the first control signal when the comparison result is the second logic level, and the resistance values of the resistor group are equal to the internal resistance value;
a frequency estimation circuit, which adjusts a capacitance value of a capacitor group according to the internal resistance value and a clock signal of the electronic system and generates a corresponding second control signal;
and a table look-up circuit for receiving the first control signal and the second control signal and obtaining a control parameter of the operational amplifier by a table look-up method, wherein the operational amplifier receives the control parameter to adjust a characteristic of the operational amplifier, and the control parameter comprises a bias current of the operational amplifier.
5. The electronic system of claim 4, wherein the resistor set has a plurality of resistors and a plurality of switching devices, and wherein the first control signal is used to control the switching devices.
6. The electronic system of claim 4, wherein the system further comprises:
a comparator having a positive input terminal coupled to the capacitor bank and a negative input terminal receiving a reference voltage; and
and the charging time estimation unit generates the second control signal according to an output signal of the comparator and the clock pulse signal.
7. The electronic system of claim 6, wherein the charge time estimation unit determines a charge time according to the clock signal, and adjusts the capacitance of the capacitor bank according to a comparison between a time required for the voltage at the positive input terminal to be charged to the reference voltage and the charge time.
8. The electronic system of claim 4, wherein the control parameter is used to adjust a DC voltage gain, a gain bandwidth product, or a slew rate of the operational amplifier.
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| CN101242164A (en) * | 2007-02-08 | 2008-08-13 | 联发科技（新加坡）私人有限公司 | Method and apparatus for tuning an active filter |
| CN103312293A (en) * | 2012-03-15 | 2013-09-18 | 瑞昱半导体股份有限公司 | Impedance correction device and impedance correction method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101242164A (en) * | 2007-02-08 | 2008-08-13 | 联发科技（新加坡）私人有限公司 | Method and apparatus for tuning an active filter |
| CN103312293A (en) * | 2012-03-15 | 2013-09-18 | 瑞昱半导体股份有限公司 | Impedance correction device and impedance correction method |
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