CN1490854A - Method for forming self aligned metal silicide - Google Patents
Method for forming self aligned metal silicide Download PDFInfo
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- CN1490854A CN1490854A CNA021468826A CN02146882A CN1490854A CN 1490854 A CN1490854 A CN 1490854A CN A021468826 A CNA021468826 A CN A021468826A CN 02146882 A CN02146882 A CN 02146882A CN 1490854 A CN1490854 A CN 1490854A
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Abstract
The present invention discloses a method for forming a self-aligned metal silicate on a semiconductor device, comprising the following steps: providing a substrate; forming the first dielectric layer on the substrate; depositing a polycrystal silicon layer on the first dielectric layer to form at least one structure of polycrystal silicon gate; depositing a conformance dielectric layer on the structure of polycrystal silicon gate and the substrate; depositing the second dielectric layer on the conformance dielectric layer; removing a part of the second dielectric layer to expose the top surface of the gate structure; depositing a metal layer on the exposed surface of the gate structure and the second dielectric layer; annealing the substrate to form a metal silicate on the gate structure; and removing at least one part of the metal layer. By depositing the second dielectric layer with a proper thickness on a substrate and then depositing a metal layer, the deposited metal layer will not be contacted with any diffusing area because other active areas are covered by the second dielectric layer in advance, so that the problem of bridge connection of the self-aligned metal silicate can be avoided.
Description
Technical field
The present invention relates to a kind of method of making semiconductor device, particularly about a kind of method that on semiconductor device, forms self-aligned metal silicate.
Background technology
In modern integrated circuits (IC), in one of significant consideration that reduces manufacturing cost for dwindling size of components.Another considers that emphasis then is a data reading speed.For memory integrated circuits (Memory IC), its speed depends primarily on the speed of bit line (word lines).When making great efforts to dwindle the size of IC assembly along with semiconductor industry, the width of character line also dwindles thereupon, cause the resistance of character line to raise, and its speed descends.Also therefore, when the speed of character line was slowed down because of the raising of its resistance, the speed of internal memory IC integral body also descended thereupon.
In order to make dynamical IC, the character line of low resistance then becomes development priority.In existing metal-oxide semiconductor (MOS) (MOS) IC, compound crystal silicon is usually used in replacing aluminum metal as grid material.Yet with the aluminum metallic matrix ratio, the shortcoming of compound crystal silicon is that its resistance is obviously higher, but can be by ion doping and appropriateness reduces.Yet even carry out high-concentration dopant, the compound crystal silicon after the doping still has quite high resistance.One of mode that solves is to deposit a metal level on compound crystal silicon, or after the CMOS transistor forms, deposits a metal level to reduce the resistance of compound crystal silicon at its area of grid.Only can form metal silicide (silicide) with the compound crystal silicon layer reaction under it at the metal level on the compound crystal silicon.This kind forms the manufacturing process of metal silicide thereby is also referred to as " autoregistration " technology.By on the compound crystal silicon grid, forming metal silicide, formed compound crystal silicon metal silicide (polycide), its resistance is significantly lower
Yet, in self-aligned metal silicate (salicide) manufacturing process, except transistor gate, outside multiple active region also is revealed in.As shown in Figure 1, self-aligned metal silicate 10 forms on the grid 12 on the transistor (unnumbered).Simultaneously, the 10 meeting whiles of self-aligned metal silicate are on transistorized regions and source 14 and 16, and formation on the active region 18 of other assembly (not shown).Self-aligned metal silicate 10 forms electrically connect with source electrode 14 and active region 18.The bridge joint of the unexpected self-aligned metal silicate of this kind (bridging) may make the IC circuit to work.
Summary of the invention
The objective of the invention is at the defective of above manufacturing process and propose a kind of method that forms self-aligned metal silicate, can be when forming the compound crystal silicon metal suicide structure that metal silicide layer and compound crystal silicon layer form, the metal level that is deposited can not contact with any diffusion region, avoids the bridge joint problem of self-aligned metal silicate.
According to the present invention, a kind of method that forms self-aligned metal silicate is provided, its step comprises: a substrate is provided; In substrate, form first dielectric layer; Deposition one compound crystal silicon layer is to form at least one grid structure on first dielectric layer; Deposition second dielectric layer on substrate and grid structure; Second dielectric layer of removing a part is to expose the top surface of grid structure; Deposition one metal level on the top surface that grid exposes and second dielectric layer; This substrate annealed form metal silicide layer on the grid structure to be formed on.
The step of second dielectric layer of a removal part in one embodiment, comprises the step of an etch-back.
The step of second dielectric layer of a removal part in another embodiment, comprises the step of a cmp (CMP).
Simultaneously,, also provide a kind of method that on the semiconductor device, forms self-aligned metal silicate, comprise the following step: provide a substrate according to the present invention; In substrate, form first dielectric layer; Deposition one compound crystal silicon layer is to form at least one compound crystal silicon grid structure on first dielectric layer; Deposition one compliance dielectric layer in compound crystal silicon grid structure and substrate; Deposit second dielectric layer on this compliance dielectric layer; Remove a part of second dielectric layer to expose the top surface of grid structure; Deposit a metal level on the grid structure surface of exposing and second dielectric layer; This substrate is annealed to form metal silicide layer on grid structure; And a part of at least this metal level of removal.
The invention has the beneficial effects as follows, second dielectric layer by deposition suitable thickness on substrate and grid, and second dielectric layer on the grid removed, and then carry out the manufacturing process of depositing metal layers, because other active region is all covered by second dielectric layer in advance, therefore the metal level that is deposited can not contact with any diffusion region, therefore, has avoided the bridge joint problem of self-aligned metal silicate yet; The compound crystal silicon metal suicide structure that the composite construction of being made up of metal silicide layer and compound crystal silicon layer simultaneously forms can still be kept the low resistance of appropriateness when grid structure dwindles, avoid postponing the access speed of MOS assembly.
And for allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, following conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the end view that existing transistor forms the self-aligned metal silicate bridge joint;
Fig. 2 is to the manufacturing process end view that Figure 5 shows that according to one embodiment of the invention.
Embodiment
According to following embodiment, and be auxilliary, describe embodiments of the invention in detail with accompanying drawing.Wherein, same drawing reference numeral is represented same or analogous assembly.
Fig. 2 is to Figure 5 shows that manufacturing process end view according to an embodiment of the invention.As shown in Figure 2, semiconductor device comprises a transistor (not label), and it has a grid 24, one gate dielectrics 22, and diffusion region 26 and 28.Generally speaking, diffusion region 26 and 28 is as transistorized source electrode and drain region (source/drain regions), but diffusion region 26 or 28 is that source electrode or drain electrode are not emphasis at this at this.In order to describe the present invention, 26 of diffusion regions are source electrode, and diffusion region 28 then is drain electrode.Semiconductor device 20 also comprises another active region (not shown), also has a diffusion region 30.Above-mentioned formation all can form by existing C MOS manufacturing process.
Definition semiconductor silicon substrate 20 earlier forms one first dielectric layer in substrate 20.For example substrate 20 is carried out thermal oxidation (thermal oxidation) and generated silicon dioxide (SiO with reaction
2) as first dielectric layer, and follow-up as gate oxide 22.Then deposit a compound crystal silicon layer on first dielectric layer.By general chemical vapor deposition (CVD), can form the compound crystal silicon layer of thickness 2000 to 3000 dusts as low-pressure chemical vapor deposition (LPCVD).And compound crystal silicon layer then is defined and be etched with formation grid 24.
In the present embodiment, in order to reduce the resistance of compound crystal silicon layer, the mode that can be implanted by thermal diffusion method or ion is mixed this compound crystal silicon layer with the phosphorus or the arsenic of high concentration, to reduce the resistance of compound crystal silicon layer.
And be the step of mask with the compound crystal silicon layer then, carry out ion and implant to form diffusion region 26,28 and 30.In the present embodiment, diffusion region 26,28 and 30 is n-type diffusion region.Then, on substrate 20 and grid 24, deposit second dielectric layer 32 of suitable thickness according to the present invention.Second dielectric layer 32 can be made of phosphorosilicate glass (PSG) or the boron-phosphorosilicate glass (BPSG) that aumospheric pressure cvd method (APCVD) or electricity slurry enhanced chemical vapor deposition method (PECVD) form.
In an embodiment of the present invention, can carry out a selectivity step earlier, on substrate 20 and grid 24, form a compliance (conformal) dielectric layer earlier.For example strengthen vapour deposition process (PECVD) and form silicon nitride layer with low pressure gas phase deposition method (LPCVD) or electricity slurry.Owing to the fine and close character of silicon nitride layer, can be used as the good protection layer (passivation layer) of element.Then depositing second dielectric layer 32 again is covered on this compliance dielectric layer.
Then as shown in Figure 3, second dielectric layer 32 of top layer part is removed, to expose the top surface of grid 24.Removing the step of part second dielectric layer can be finished by a cmp (CMP) or an etch-back (etch back) step, removes second dielectric layer and the compliance dielectric layer of adequate thickness, to expose the top of grid 24.
After expose on the top layer of grid 24, as shown in Figure 4, deposit a metal level (not shown) on the surface of second dielectric layer 32 and the grid structure 24 that exposes.The metal material of deposition can be titanium Ti, tantalum Ta, tungsten W, molybdenum Mo etc., perhaps other eight families metal, as metals such as cobalt Co, platinum Pt, palladium Pd or nickels, be deposited on grid structure 24 and second dielectric layer, 32 surfaces by sputter (sputtering deposition) mode, to form metal level.
Then carry out annealing (annealing) program, under hot conditions, make the metal level of deposition produce chemical reaction, to form metal silicide (silicide) 34, as TiSi with its grid that contacts down 24 surfaces
2, WSi
2Or CoSi
2Therefore, the composite construction of being made up of metal silicide layer and compound crystal silicon layer then forms compound crystal silicon metal silicide (polycide) structure, can still keep the low resistance of appropriateness when grid structure dwindles, and avoids postponing the access speed of MOS assembly.And because other active region is all covered by second dielectric layer 32 in advance as diffusion region 26,28 and 30, therefore the metal level that is deposited can not contact with any diffusion region, also therefore, has avoided bridge joint (bridging) problem of self-aligned metal silicate.
As shown in Figure 5, the unreacted metal layer can then be removed by the selectivity etching.And after removing unnecessary unreacted metal layer, then form the MOS modular construction, and the problem of bridge joint can not appear therebetween.Then, the follow-up manufacturing processes such as existing interlayer dielectric layer, interconnect and contact hole that carry out are to finish the structure of semiconductor integrated circuit.
Though the present invention discloses as above with preferred embodiment, be not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention, the equivalent transformation of having done all is included in the claim of the present invention.
Claims (13)
1. a method that forms self-aligned metal silicate is characterized in that, comprises:
One substrate is provided;
In this substrate, form one first dielectric layer;
Deposition one compound crystal silicon layer is to form at least one grid structure on this first dielectric layer;
Deposition one second dielectric layer in this grid structure and this substrate;
Remove this second dielectric layer of a part to expose the top surface of this grid structure;
Deposit a metal level on this grid structure that exposes surface and this second dielectric layer; And
This substrate is annealed to form a metal silicide layer on this grid structure.
2. the method for formation self-aligned metal silicate according to claim 1 is characterized in that, this second dielectric layer is made of boron-phosphorosilicate glass.
3. the method for formation self-aligned metal silicate according to claim 1 is characterized in that, also comprises a step: deposit a compliance dielectric layer in this grid structure and this substrate.
4. the method for formation self-aligned metal silicate according to claim 3 is characterized in that, this compliance dielectric layer is made of silicon nitride.
5. the method for formation self-aligned metal silicate according to claim 1 is characterized in that, the step of removing this second dielectric layer of a part comprises the step of an etch-back.
6. the method for formation self-aligned metal silicate according to claim 1 is characterized in that, the step of removing this second dielectric layer of a part comprises a cmp step.
7. according to the method for 1 described formation self-aligned metal silicate of claim the, it is characterized in that this metal level is by titanium Ti, tungsten W or cobalt Co constitute.
8. a method that forms self-aligned metal silicate on the semiconductor device is characterized in that, comprises:
One substrate is provided;
In this substrate, form one first dielectric layer;
Deposition one compound crystal silicon layer is to form at least one compound crystal silicon grid structure on this first dielectric layer;
Deposition one compliance dielectric layer in this compound crystal silicon grid structure and this substrate;
Deposit one second dielectric layer on this compliance dielectric layer;
Remove this second dielectric layer of a part to expose the top surface of this grid structure;
Deposit a metal level on this grid structure that exposes surface and this second dielectric layer;
This substrate is annealed to form a metal silicide layer on this grid structure; And
Remove a part of at least this metal level.
9. the method that forms self-aligned metal silicate on the semiconductor device according to claim 8 is characterized in that this second dielectric layer is made of boron-phosphorosilicate glass.
10. the method that forms self-aligned metal silicate on the semiconductor device according to claim 8 is characterized in that this compliance dielectric layer is made of silicon nitride.
11. the method that forms self-aligned metal silicate on the semiconductor device according to claim 8 is characterized in that, the step of this this second dielectric layer of removal part comprises an etch-back step.
12. the method that forms self-aligned metal silicate on the semiconductor device according to claim 8 is characterized in that, the step of this this second dielectric layer of removal part comprises a cmp step.
13. the method that forms self-aligned metal silicate on the semiconductor device according to claim 8 is characterized in that, this metal level is by titanium Ti, and one of tungsten W or cobalt Co constitute.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021468826A CN1490854A (en) | 2002-10-18 | 2002-10-18 | Method for forming self aligned metal silicide |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021468826A CN1490854A (en) | 2002-10-18 | 2002-10-18 | Method for forming self aligned metal silicide |
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| CN1490854A true CN1490854A (en) | 2004-04-21 |
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| CNA021468826A Pending CN1490854A (en) | 2002-10-18 | 2002-10-18 | Method for forming self aligned metal silicide |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101506955B (en) * | 2006-09-21 | 2010-11-17 | 英特尔公司 | Dielectric spacers for metal interconnects and method to form the same |
| CN108346574A (en) * | 2017-01-25 | 2018-07-31 | 联华电子股份有限公司 | The method for making the semiconductor element with cobalt suicide layer |
-
2002
- 2002-10-18 CN CNA021468826A patent/CN1490854A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101506955B (en) * | 2006-09-21 | 2010-11-17 | 英特尔公司 | Dielectric spacers for metal interconnects and method to form the same |
| CN108346574A (en) * | 2017-01-25 | 2018-07-31 | 联华电子股份有限公司 | The method for making the semiconductor element with cobalt suicide layer |
| CN108346574B (en) * | 2017-01-25 | 2021-08-10 | 联华电子股份有限公司 | Method for manufacturing semiconductor element with cobalt silicide layer |
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