NL1008773C2 - Self-aligned borderless contacts and local interconnections manufacture - Google Patents

Abstract

The integral process is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. The method comprises (i) providing a substrate having shallow trench isolation areas (31) for defining at least a local interconnection and an active area, (ii) forming first and second gate electrodes respectively on the local interconnect area and the active area, each electrode respectively having a gate oxide layer (32), a polysilicon layer (33a,b) above the gate oxide layer, a silicide layer (34a,b) and a first isolation layer (35a,b), (iii) forming source/drain regions (36) in the substrate by ion implantation using the gate electrodes as masks, (iv) forming spacers (37a,b,c,d) around the gate electrodes, (v) etching a portion of the first gate electrode and a portion of the first spacer to expose a portion of the silicide layer of the first gate electrode, (vi) eliminating the exposed portion of the gate oxide layer, (vii) forming a self-aligned silicide layer (42a,b,c) on the surface of the source/drain regions, and (viii) forming a second isolation layer (44) and a dielectric layer (43a) over the second isolation layer, etching a portion of the second isolation layer and the dielectric layer to form a first opening above the local interconnect area and a second opening above the active area. The first opening exposes portions of the first gate electrode, the silicide layer, the first spacer and the self-aligned silicide layer on the surface of the source/drain region of the first electrode. The second opening exposes portions of the second gate electrode, the second spacer and the self-aligned silicide layer on the surface of the source/drain region of the second electrode.

Description

NL 43.511 Ra / hc

BACKGROUND OF THE INVENTION Field of the Invention

This invention relates to a method of manufacturing semiconductors, and more particularly to self-aligned local connection and contact (SALIC) technology, which integrates a process of self-aligned and limitless contacts, as well as a process of local connections .

Description of related technique

As the integration of elements in integrated circuits (IC) increases, the resistance of source / -10 drain regions in the elements of metal oxide semiconductor (MOS) transistors increases at the same time. Since the resistance of the source / drain region is almost equal to the resistance of a channel of the MOS transistor, a process of self-aligned silicide (SALICIDE) is used to reduce the layer resistance of the source / drain regions to maintain a set of narrow connections between the metal layer and the MOS transistor. The salicide process is currently used in a method of manufacturing an extremely large-scale integrated 20 (VLSI) device.

Furthermore, a double gate, such as an N + / P '*' poly-double gate, is applied in the element in a deep submicron process when an increase in the density of the integrated circuits and a decrease in the size of the 25 elements is necessary. . For better performance, a tungsten silicide (WSix) layer is used to cover the doped polygate layer of elements, while at the same time a polysilicide gate is formed by determining the tungsten silicide layer and the polygate layer.

Figures 1A-1D show a conventional method of manufacturing a self-aligned silicide. First, referring to Fig. 1A, there is a 1008773 2 silicon substrate 10 that includes narrow slot isolation regions 11, a gate oxide layer 12a, and a polygate layer 13a. The narrow slot isolation area 11 is formed in a number of steps. First, narrow slots are formed in the substrate 10. Subsequently, the narrow slots are filled with, for example, silicon dioxide. Finally, the narrow slot isolation region is formed by an anisotropic dry etching method. An active region 9 for a transistor element is successively formed adjacent to each second narrow slot isolation region 11.

Furthermore, the gate oxide layer 12a is formed from, for example, silicon dioxide. The polygate layer 13a is formed by, for example, a low pressure chemical vapor method. The thickness of the polygate layer 13a is about 2000 A ~ 3500 A.

Referring to Fig. 1B, the polygate layer 13a is covered with a tungsten silicide layer 14a. The tungsten-10 silicide layer 14a can be formed in a low-pressure chemical vapor deposition (LPCVD) process, the reaction being carried out, for example, by a mixing gas of tungsten hexafluoride (WFS) and silane at a temperature of about 300 ° C «400 ° C. The thickness of the tungsten silicide layer 14a is about 40 DEG-800 A. Subsequently, a silicon nitride layer 15a is formed by deposition over the tungsten silicide layer 14a. For example, the method of forming the silicon nitride layer 15a is a low pressure chemical vapor deposition method.

Next, referring to Fig. 1C, a structure for the gate electrode 13 'is formed above the substrate 10 by a conventional photolithography etching method, whereby the gate oxide layer 12a, the polygate layer 13a, the tungsten silicide layer 14a and the silicon nitride 15a are determined. The gate electrode 13 'includes a gate oxide 12b, a polygate layer 13b, a tungsten silicide layer 14b, and a silicon nitride 15b.

A spacer layer 16, with reference to Fig. 1D, is formed around the side wall of the gate electrode 13 '.

Next, the self-aligned silicide 17 is formed on a portion of the surface of the substrate 10. The 1008773 3 self-aligned silicide 17 can be formed by a first step of forming a titanium layer by spraying over the silicon 10. Then the silicide 17 is formed in the interface of the titanium layer and the exposed portions of the substrate 10 by, for example, a rapid thermal oxidation process.

On the other hand, as the integration of the semiconductor device increases, the surface of the chip cannot provide enough areas for connections within the device. To meet the increasing need for internal connections, connections of more than two metal layers are currently used in integrated circuit design, especially in complex IC products, such as, for example, a microprocessor. Even four or five metal layers are used in the design for joining the elements in the microprocessor.

Figures 2A-2D show a conventional method of manufacturing local connections in local areas in the device. Fig. 2A shows a substrate 20, the substrate 20 having a narrow slot isolation region 21 for determining the memory cells. Furthermore, the substrate 20 is covered by a gate oxide layer 22, a first gate electrode 23 and a second gate electrode 24 formed above the gate oxide layer 22, and spacer layers 25 surrounding the side walls of the first gate electrode 23 and the second gate electrode 24 are formed. The first gate electrode 23 and the second gate electrode 24 are made of, for example, polysilicon doped with impurities. The spacer layer 25 is made of, for example, silicon dioxide.

Next, referring to Fig. 2B, a method for forming self-aligned silicide (SALI-CIDE) is used. Before using the salicidal process, the exposed portion of the gate oxide layer is removed. For example, the method first includes the step of depositing a metal layer over the first gate electrode 23, the second gate electrode 24, and a gate oxide layer 22. The metal layer is, for example, a titanium layer which is deposited by microwave DC atomizing.

The thickness of the metal layer is preferably about 1008773 4 200 ~ 1000 A. Then, the titanium layer reacts with the surface of the first gate electrode 23, the second gate electrode 24 and the exposed portion of the substrate. 20 in order to obtain the silicide 26 at a high temperature. The silicide is, for example, titanium silicide (TiSi2).

A titanium nitride layer 27a, with reference to Fig. 2C, is deposited by reactive sputtering deposition over the substrate 20 to cover the first gate electrode 23, the second electrode 24, and the spacer layer 25. The reactive sputter deposition method uses the titanium as a metal target. The impact-atomized ions react with the nitrogen of the plasma in an argon and nitrogen-filled environment to obtain titanium nitride (TiN). Then, a photoresist layer 28 is formed over the substrate 20, the photoresist layer 28 being determined to cover portions of the substrate 20. For example, the portion of the titanium nitride layer 27a that is on the surface of the first gate electrode 23 and half of the second gate electrode 24 is exposed, referring to FIG. 2C.

The exposed titanium nitride 27a not covered by the photoresist layer 28 is etched away with reference to Figure 2D and the titanium nitride residual layer 27b is formed. Then, in the subsequent manufacturing process, the front process of the local compounds is performed by removing the photoresist layer 28. The back process can be easily performed by those skilled in the art to complete the device.

30 It is critical in LOGICA technology to provide the self-aligned, limitless contacts and the local connections (LI) at the same time. Meanwhile, it should be compatible with the self-aligned titanium silicide (SALI-CIDE) and N + / P + poly-double-hole process LOGICA modules. In the conventional manufacturing method, this is not achieved due to the difficulties in integrating the salicide process and the LI into the salicide and N + / P + poly base line logic process.

1008773 5

SUMMARY FOR THE INVENTION

It is therefore an object of the present invention to provide a method in which self-aligned, limitless contacts and local connections of semiconductor devices are manufactured in an integral process.

To this end, it is another object of the present invention to provide a method in which the self-aligned titanium silicide (SALICIDE) and the N + / P + polydub-10 belgate process LOGICA modules are compatible. That is, this invention provides a self-aligned local connection and contact (SALIC) logic technology method to form the self-aligned, boundless contacts and the local connections (LI) simultaneously.

In accordance with the aforementioned and other objects of the present invention, a method of manufacturing self-aligned, limitless contacts and local connections is provided. The method includes providing a substrate, the substrate having a plurality of narrow slot insulating layers, which narrow slot insulating layers are used to determine at least one local bond area and an active area.

Then, a first gate electrode and a second gate electrode are formed on the local connection region and the active region, respectively. The first gate electrode and the second gate electrode have a gate oxide layer, a polysilicon layer above the gate oxide layer, a silicide layer, and a first insulating layer, respectively.

Then, a number of source / drain regions in the substrate are formed by ion implantation using the first gate electrode and the second gate electrode as masks. A first spacer layer and a second spacer layer are formed around the first gate electrode and the second gate electrode. Thereafter, a portion of the first gate electrode and a portion of the first spacer layer are etched away for exposure of a portion of the silicide layer of the first gate electrode. Then the exposed portion of the gate oxide layer is removed.

Then the self-aligned silicide layer! 008773 6 formed on the exposed surface of the source / drain region. Then, a second insulating layer and a dielectric layer are formed over the second insulating layer. The second insulating layer and the dielectric layer have a first opening above the local connection area and a second opening above the active area. The first aperture is used to expose portions of the first hole electrode, the silicide layer, the first spacer layer, and the self-aligned silicide layer on the surface of the source / drain region around the first electrode. The second opening is used to expose portions of the second gate electrode, the second spacer layer, and the self-aligned silicide layer on the surface of the source / drain region around the second electrode.

By the method described above, self-aligned, limitless contacts and local connections of semiconductor devices are manufactured in an integral process. The method is compatible with the self-aligned titanium silicide (SALICIDE) and N + / P + poly-double-process processes LOGICA modules. That is, this invention provides a self-aligned local connection and contact (SALIC) method of logic technology to form the self-aligned, limitless contacts and the local connections (LI) simultaneously.

25 BRIEF DESCRIPTION OF THE DRAWING

The invention will become more apparent upon reading the following detailed description of preferred embodiments, with reference to the accompanying drawings, in which: 1A-1D show cross-sectional views of selected process steps of a conventional procedure used in the manufacture of a self-aligned silicide;

Fig. 2A-2D show cross-sectional views of representations of selected process steps of a conventional procedure used in the manufacture of topical joints; and

Fig. 3A-3H show cross-sectional views of representations of selected process steps of a procedure in accordance with a preferred embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The invention provides a new method in which self-aligned, limitless contacts and local connections of semiconductor devices are manufactured in an integral process. The method is compatible with self-aligned titanium silicide (SALICIDE) and N + / P + poly-double gate epic LOGIC modules. That is, this invention provides a self-aligned local connection and contact (SALIC) logic technology method to form self-aligned, boundless contacts and local connections (LI) simultaneously.

Figures 3A-3H show cross-sectional views of representations of selected process steps of a procedure in accordance with the preferred embodiment of the invention, introducing a method for self-aligned local connection and contact (SALIC) technology. Fig. 3A shows a substrate 30 and narrow slot isolation regions 31 formed therein. The narrow slot isolation regions 31 are filled with, for example, silicon dioxide (SiO 2). Active regions and local junction regions of the semiconductor device are defined between the narrow slot isolation regions 31, for example, the active region 9 'and the local junction region 9 "as shown in FIG. 3A. Next, a gate oxide layer 32, a polysilicon layer, for example, an N + / P + poly-double gate layer 33, a silicide layer, for example, a TiSi2 layer 34, and an insulating layer, for example, a silicon nitride layer 35 formed successively above the substrate 30.

The stacked structure of the N + / P + polymer double layer layer 33, the TiSi2 layer 34, and the silicon nitride layer 35 is determined by a conventional photolithography and etching process, referring to FIG. 3B. for forming gate electrodes, for example, a first gate electrode 3a above the local connection region 9 "and the second gate electrode 3b above the active region 9". The first gate electrode comprises a N + / P + double gate layer 33a, a TiSi2 layer 34a, and a silicon nitride layer 35a The second gate electrode 3b includes an N + / P + double gate layer 33b, a TiSi2 layer 34b , and a silicon nitride layer 35b The first gate electrodes 3a and the second gate electrode 3b are considered to be the gate structures for forming the local connections simultaneously and for the self-aligned silicide in different regions in the same design.

Referring to Figure 3C, the source / drain regions 36 are formed in the substrate 30 adjacent to regions under the first gate electrode 3a and the second gate electrode 3b by ion implantation. Spacer layers are then formed around the side wall of the gate electrodes. As shown in Fig. 3C, first spacer layers 37a, 15 and 37b, and second spacer layers 37c and 37d are formed around the first gate electrode 3a and second gate electrode 3b, respectively. The spacer layers 37a, 37b and 37c, 37d are made of, for example, silicon nitride.

A photoresist layer 38a, with reference to Fig. 3D, is formed over the substrate 30. The photoresist layer 38a includes a first opening 39, the first opening being a portion of approximately half the surface of the silicon nitride layer 35a, the spacer layer 37a, and a portion of the gate oxide layer 32. The opening 39 exposes a portion of the local connection area 9 "and is used to explain the formation process of the local connections in the device.

Then, the exposed silicon nitride layer 35a and the horizontal portion of the exposed spacer layer 37a next to the silicon nitride layer 35a are etched away by, for example, an anisotropic etching method using the gate oxide layer 32 as an etch stop layer and using of the TiSi2 layer 34a as an etching end point. As shown in Fig. 3E, a silicon nitride 35 35c and the spacer layer 37e are formed by the etching process described above. The photoresist layer 38a is then removed. The exposed portion of the gate oxide layer 32 is removed by, for example, a wet etching process to form a gate oxide layer 32a.

1008773 9

Next, referring to Fig. 3F, a conventional process for forming the self-aligned silicide is used to form the silicides 42a, 42b and 42c in the surface of the source / drain regions. The Si-5 licides 42a, 42b and 42c are made of, for example, TiSi2. Then, a second insulating layer is applied over the substrate 30, for example, a silicon nitride layer 44 formed over the substrate 30. The silicon nitride layer 44 is used as a barrier layer to prevent damage to the device caused by the plasma used in the following process.

Then, an interlayer dielectric (ILD) layer 43 is formed over the substrate 30 to cover the silicon nitride layer 44. Thereafter, a photoresist layer 38b is formed over the ILD layer 43. The photoresist layer 38b includes a second opening 40 and a third opening 41. The second opening 40 and the third opening 41 are located above the active region and the local connection area.

The entire ILD layer 43 above the substrate 30, with reference to Fig. 3G, is converted into an ILD layer 43a by etching away the exposed ILD layer 43 using the silicon nitride layer 44 as an etching stopper. -low. The ILD layer 43a includes an opening 40a and an opening 4la. The aperture 40a thereby exposes a portion of the silicon nitride layer 35c, a portion of the TiSi2 layer 34a, the spacer layer 37e, and a portion of the silicide 42a. The opening 41a thereby exposes a limitless contact area 41 '. The boundless contact region 41a includes a portion of the narrow slot insulating region 31, a portion of the silicon nitride layer 35b, and a portion of the silicide 42b. The photoresist layer 38b is then removed.

In accordance with what has been described above, the opening 40a is used to form the local connections, and the opening 41a is used to form the self-aligned and limitless contact.

A barrier / adhesive layer 45 is applied over the substrate 30, referring to FIG. 3H. The exposed portions, ie exposed portions of the silicon nitride layer 35c, the TiSi2 layer 34a, the spacer 1008773. layer 37e and the silicide 42a in the opening 40a, and portions of the narrow slot insulating region 31, the silicon nitride layer 35b, and the silicide 42b in the opening 41a are covered by the barrier / adhesive layer 45. The side walls of the opening 40a and the opening 41a are also covered by the barrier / adhesive layer 45. The barrier / adhesive layer 45 is made of, for example, titanium and titanium nitride.

Then, a tungsten coating layer 46 is formed over the substrate 30 filling the openings 10a and 41a of the ILD layer 43a to cover the barrier / adhesive layer 45. The tungsten coating layer 46 is formed by, for example, chemical vapor deposition. A chemical mechanical polishing method (CMP) is performed to flatten the barrier / adhesive layer 45, the tungsten layer 46, and the ILD layer 43a. An alloy layer, for example an Al-Cu layer 47, is formed over the substrate 30, i.e. over the ILD layer 43a and the tungsten layer 46 to form the multiple compounds in the device. The following process for the device can be performed by a conventional method.

In accordance with the preferred embodiment described above, this invention provides a new method in which self-aligned, limitless contacts and local connections of semiconductor devices are fabricated in an integral process.

Using the process of this invention, a number of desirable advantages are achieved. For example, because the method is compatible with the self-aligned titanium silicide (SALICIDE) and N + / P + poly-double-gate-process-30 LOGIC modules, the self-aligned local connection and contact (SALIC) method for logic technology to form simultaneously of the self-aligned, limitless contacts and the local connections (LI), the manufacturing time is reduced and the manufacturing efficiency is also improved.

The invention has been described using exemplary preferred embodiments. However, it should be realized that the scope of the invention is not limited to the described embodiments. In contrast, it is intended to cover various modifications and similar configurations. The scope of the claims, therefore, should be considered in the widest possible interpretation, so that all such modifications and similar configurations are included.

1008773

Claims (12)

A method of manufacturing self-aligned, boundless contacts and local connections, comprising: providing a substrate, the substrate having a plurality of narrow slot insulation layers, which slot insulation layers are used to determine at least one local connection area and an active area; forming a first gate electrode and a second gate electrode on the local connection region and the active region, respectively, the first gate electrode and the second gate electrode forming a gate oxide layer, respectively, a polysilicon layer above the gate oxide layer, a silicide layer and a first insulating layer; forming a number of source / drain regions in the substrate by ion implantation using the first gate electrode and the second gate electrode as masks; forming a first spacing layer and a second spacing layer around the first gate electrode 20 and the second gate electrode, respectively; etching a portion of the first gate electrode and a portion of the first spacer layer to expose a portion of the silicide layer of the first gate electrode; Removing the exposed portion of the gate oxide layer; forming a self-aligned silicide layer on the surface of the source / drain region; and forming a second insulating layer and a dielectric layer over the second insulating layer, the second insulating layer and the dielectric layer having a first opening above the local connection area and a second opening above the active area, which first opening is used for exposing portions of the first 35 gate electrode, the silicide layer, the first spacer layer and the self-aligned silicide layer on the surface of the 1008773 source / drain region around the first electrode, and every second opening is used to expose portions of the second gate electrode, the second spacer layer, and the self-aligned silicide layer on the surface of the source / drain region around the second electrode, thereby creating the self-aligned, boundless contact and the local connection are formed on it. The method of claim 1, further comprising: forming a barrier / adhesive layer on side walls 10 and bottoms of the first opening and the second opening; and forming a plug layer over the substrate to fill the first opening and the second opening. The method of claim 2, wherein the barrier / adhesive layer is a Ti / TiN layer. The method of claim 3, wherein the Ti / TiN layer is formed by deposition. The method of claim 4, wherein the plug layer consists of tungsten. 6. A method according to claim 1, wherein the silicon layer consists of TiSi2. The method of claim 6, wherein the silicide layer is formed by deposition. The method of claim 1, wherein the first insulating layer and the second insulating layer consist of silicon dioxide. The method of claim 1, wherein the first spacer layer and the second spacer layer consist of silicon nitride. 10. A method according to claim 1, wherein the removal of the gate oxide layer is carried out by a wet etching method. The method of claim 1, wherein forming the self-aligned silicide comprises: forming a metal layer over the substrate; 35 reacting the metal layer with the exposed surface of the source / drain region at a predetermined temperature to obtain the self-aligned silicide. 12. A method of manufacturing self-aligned, limitless contacts and local connections, comprising: providing a substrate, the substrate having a number of narrow slot insulating layers, which 5 slot insulating layers are used to determine at least a local connection area and an active area; forming a first gate electrode and a second gate electrode on the local connection region and the active region, respectively, the first gate electrode and the second gate electrode, respectively, a gate oxide layer, a polysilicon layer above the gate oxide layer has a silicide layer and a first insulating layer; forming a number of source / drain regions in the substrate by ion implantation using the first gate electrode and the second gate electrode as masks; forming a first spacing layer and a second spacing layer around the first gate electrode and the second gate electrode, respectively; Etching a portion of the first gate electrode and a portion of the first spacer layer to expose a portion of the silicide layer of the first gate electrode; removing the exposed portion of the gate oxide layer; forming a self-aligned silicide layer on the surface of the source / drain region; forming a second insulating layer and a dielectric layer over the second insulating layer, the second insulating layer and the dielectric layer having a first opening above the local connection area and a second opening above the active area, which first opening is used for exposing portions of the first gate electrode, the silicide layer, the first spacer layer, and the self-aligned silicide layer on the surface of the source / drain region around the first electrode, and which second aperture is used for exposing portions of the second gate electrode, the second spacer layer, and the self-aligned silicide layer on the surface of the source / drain region around the second electrode; forming a barrier / adhesive layer on side walls and bottoms of the first opening and the second opening; and forming a plug layer over the substrate to fill the first opening and the second opening. 1008773