CN1486465A - Handling conditional processing in a single instruction multiple datapath processor architecture - Google Patents
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Abstract
A processor enable (PE) state of a datapath during conditional processing is maintained by saving a current PE state of the datapath as an indication thereof before the conditional processing, and manipulating the indication during the conditional processing to reflect changes in the PE state of the datapath that may occur during the conditional processing. Where the conditional processing block is an if-then-else processing block, the PE state is saved during if-processing by storing the indication as a value representing the current PE state, and the manipulating includes changing the value based on the PE state during the if-processing. The PE state is inverted, or not, prior to performing the else-processing based on whether the if-processing changed the PE state of the datapath. At the end of the conditional processing block, the saved PE state of the datapath is restored based at least in part on the value. An instruction set and an SIMD processor for carrying out these steps are also provided. The instruction set also includes instructions that combine one or more of the PE saving and manipulating steps with a branch operation.
Description
The application relates to the application of the disclosed in the lump BRANCH of being entitled as HANDLING FOR SINGLE INTRUCTIONMULTIPLE DATAPATH PROCESSOR ARCHITECTURES, and this application and the application are incorporated herein by reference in submitting on the same day.
Technical field
The condition program (conditional processing) that the invention relates to single instruction multiple data path (single instruction multipledatapaths (SIMD)) processor structure is handled.
Background technology
Parallel processing is effective ways of handling multidata item array (array of data items).The single instruction multiple data path processor is the parallel processing structure of arrays.Each data routing can only be handled a data item in a time.Lift a simple example, the single instruction multiple data path processor has four data paths, have four data item arrays each data item will one of them be handled by four data routings of correspondence.
The term of execution of single instruction multiple data path processor program, if the beginning calculated example in this way-then-the condition program block of all the other (if-then-else) program blocks before, can enable a plurality of data routings earlier.Before the executive condition program block, the PE state of each data routing, i.e. the state that whether enables or forbid, must store earlier in case during the executive condition program any situation changed the PE state.In addition, after leaving the condition program block, the PE state of data routing must revert back to the state before the entry condition program block.
A kind of during the condition sequential operation method of management data path P E state be that PE state with each data routing remains in the register stack (stack).The PE state of data routing will be changed during the condition routine processes, so in advance the PE state is pushed in (push) register stack.After finishing the condition program block, eject (pop) previous PE state from register stack, and a plurality of back and forth with the PE state of the data routing before the executive condition program block according to the path.If the condition program block (for example comprises a plurality of conditional operations, if nested-then-all the other computings (nested if-then-else operations)), then storehouse must comprise the PE state (and afterwards replying a plurality of PE states according to the path) of the data routing of multiple register when being stored in the multiple condition computing.When the Nested conditions computing, because parallel register can be used to do the quantity of storehouse its limit is arranged, so come managing stack to seem very difficult with software.
Summary of the invention
The objective of the invention is to, during the condition program, the present PE state storage of data routing relevant before the condition program is become indication, to keep the PE state of data routing, and handle the contingent change of PE state of the data routing during the condition program, thereby have influence on the indication during the condition program.Another object of the present invention is to, carry out the instruction set and the single instruction multiple data path processor of these steps.
In a preferred embodiment, may comprise more than one following feature.
After the condition program, reply the PE state of the data routing of storage according to the indication of at least one part.And store, manipulation and return phase carried out by in a plurality of data routings of the single instruction multiple data path processor of executive condition program each.
In illustrated embodiment, if the condition program comprises program (if-processing) statement.Storing step comprises the value of indication of the present PE state of storage representation data routing.Maneuvering sequence comprises foundation PE state of data routing during the condition program and changes value.If during the PE Status Disable of data routing, then value increases during storing step.If the PE state of data routing is when enabling during the condition program, value keeps original value and can not change.
After if program (if-processing) statement is carried out, according to a plurality of back and forth the PE states of the value of at least one part according to the path storage.If return phase comprises numerical value and surpasses when limiting (threshold), then the PE in specific data path is an illegal state, otherwise the PE in specific data path is an enabled state.If surpassing, value limits then this value of change (for example, reducing).
If the condition program block can comprise a plurality of programs (if-processing) statement.In this manual, if storage, manipulation and return phase in order to carry out each in a plurality of program statements.
The condition program block can comprise other program (else-processing) statement.If maneuvering sequence also comprises the PE state of the routine change data routing of program statement according to whether and comes to change (for example, conversion) or do not change value carrying out other program statement.
For example, if if the PE state that data routing is stored is the routine change PE state of enabled state and program statement is illegal state, then maneuvering sequence comprises that change is worth and represents enabled state.If do not change the PE state if the PE state that data routing is stored is the program of enabled state and program statement, then maneuvering sequence comprises that change is worth and represents illegal state.If do not change the PE state if the processor illegal state that data routing is stored is the program of enabled state and program statement, then maneuvering sequence comprises that the value of keeping represents illegal state.
Another object of the present invention is to, instruction is with branch computing (branch operation) next storage and maneuvering sequence in conjunction with more than one PE state.
Other advantage of the present invention comprises the PE state of realizing following the trail of exactly (with correctly replying) data routing with minimum hardware spending (hardware overhead), comprises a plurality of Nested conditions computings even work as the condition program block.Especially, follow the trail of the PE state of each data routing with single register, so can eliminate for the required multiple register of the tracking of keeping the PE state.In addition, when the beginning of condition program block, process and end, promptly store, handle and return a plurality of PE states according to the path.Come to reduce the speed that software overhead (software overhead) also can increase program widely with branch computing in conjunction with the storage of an above PE state and the step of conversion.
Other advantage of the present invention is represented by following description, accompanying drawing and claim.
Description of drawings
Fig. 1: the block flow diagram of single instruction multiple data path processor;
Fig. 2: the PE state of the data routing of single instruction multiple data path processor keeps program flow diagram during the condition program; And
Fig. 3: the program list that utilizes SAVE_PE, RESTORE_PE and FLIP_PE instruction.
Wherein, identical Reference numeral is represented components identical.
Embodiment
With reference to figure 1, single instruction multiple data path processor (SIMD) 10 comprises instruction cache 12, steering logic unit 14, and serial data path 16 and a plurality of parallel data path are denoted as 18a, 18b, 18c, 18 ..., 18n.Parallel data path 18 write memories 20.Each data routing 18 all is attached to PE position 22.Specifically, parallel data path 18a is attached to PE position 22a, and parallel data path 18b is attached to PE position 22b, below analogizes.When PE enabled, the parallel data path that is linked enabled and parallel data path writes data item.For example, when PE 22a enabled, parallel data path 18a write data item; When PE 22b enabled, parallel data path 18b write data item.When if PE 22n enables, parallel data path 18n writes data item.When PE forbade, the parallel data path that is linked was forbidden and parallel data path can't write data item.
During computing, steering logic unit 14 is from instruction cache 12 reading command.Serial data path 16 is sent in instruction provides instruction to parallel data path 18.Unless the enable bit of individual processor is under an embargo, otherwise each parallel data path 18 reads simultaneously and writes simultaneously.
When program code (for example, if that program block comprises is more than one-then-other program (if-then-else-processing) statement) instruction make single instruction multiple data path processor 10 between program code during the executive condition program block, must calculate the present PE state of each data routing, if so any PE state of data routing is modified the term of execution of the condition program block, the PE state just can be replied when finishing the condition program block.The condition program block often comprises a plurality of condition sequential operations, and some of them condition program block is carried out when other condition sequential operation.In order to guarantee preferred computing, the PE state of each data routing of storage before entering each Nested conditions computing, and the PE state of answer storage after finishing conditional operation.
As discussed above, the condition sequential operation is wherein a kind of be if-then-other conditional operation.If when-then-other program during the PE state of data routing when changing, interesting phenomenon takes place.Particularly, when the PE of data routing state when forbidding, comprise if-then-operational stage of other program block between, the PE state of data routing changes over enabled state never again.The present invention utilizes this phenomenon and follows the trail of the PE state of each data routing by the indication (indication) that provides and revise the PE state.
Sum up tout court, when data routing entry condition program block, become a value to represent the present PE state of data routing (show enable or illegal state by the PE position of data routing) its PE state indicative of settings, and store this value (for example, in the parallel register relevant) with data routing.Therefore present PE state storage Cheng Qifei directly indicates.If-then-other program block during, this value is done necessary renewal according to the PE state of data routing during the condition program.If when data routing finish-then-during other program block, if this value in order to the PE replying state of data routing to as enter-then-the PE state of data routing before other program block.As a result, correctly track the PE state of data routing,, after each conditional operation, still reply (certainly, finally finishing after all conditions handle square) accurately even when having passed through a plurality of Nested conditions sequential operation.Expense (overhead) is reduced to minimum because single register is in order to the indication (that is, value) of storage PE state, rather than the PE status information that all provides different registers to store data routing for each the Nested conditions computing in the piece.
If Fig. 2 were illustrated in-then-would keep the program 50 of state of the data routing of single instruction multiple data path (SIMD) processor 10 in other the exemplary condition program block.At first, the indication of the PE state of data routing (be kept among Fig. 1 among one of them parallel register R) is initialized to is limit value (threshold) (step 52).For the purpose of discussing below, be used as limit value with-1.If (in other words, when storage PE state) if the PE state of data routing is the state of forbidding (step 54), then increases this value (step 56) when program block begins to calculate.Otherwise, be worth constant (as step 58).
If during program, if judge the PE state (step 59) of revising data routing according to the result of program.When if condition program block (conditional processing block) comprises other program block (else-processing block) (step 60), programmed decision PE state in translation data path whether before carrying out other program; When the condition program block does not comprise other program, skips steps 62 (step 64) then.During step 62, if if carrying out-then-other program block before the PE state in enable data path, then program 50 is inverted the PE state of (invert) data routing according to the PE state of storage (in other words, if carrying out-then-the PE state of data routing before other program block).Yet, if if carrying out-then-other program block before the PE state in forbidden data path, it still is under an embargo, so program 50 will not change it.
Finish behind other program block (or not comprising " other (else) " at the condition program block) if under the condition of the program block during statement, program 50 is replied the PE state (in other words, the current PE state of the data routing before data routing entry condition program block) of storage.If the value of indication is less than 0, then program 50 enables PE state (step 66); Otherwise, the PE state in forbidden data path.At last,, refer to be worth qualification here, then reduce the value (step 68) of indicating above-1 if should be worth more than or equal to 0.
The condition program block may comprise other condition program statement.For example, if if it may comprise with nested relation arrange extra-then-other program statement or program statement.If this is really true, then come the plurality of step of executive routine 50 by the condition program state that they provided.
For realizing the program 50 of Fig. 2, during program compiler, three instructions are inserted in the coding and decoding so that carry out in single instruction multiple data path processor 10 by compiler (compiler).These three instructions are:
SAVE_PE(P)
RESTORE_PE(P)
FLIP_PE(P)
Wherein P refers to the parallel register that the PE state in order to the storage data routing in single instruction multiple data path processor 10 is indicated.During program compilation, compiler before if program block begins (in other words, just " if " before the program statement) insert instruction SAVE_PE (P) (with the step 54-58 of executive routine 50) earlier, and if behind program block, insert instruction RESTORE_PE (P) (with execution in step 66 and 68).Other program block if program comprises in the program block, promptly, if-then-other program block, compiler before other program block begins (in other words, just before " other " program statement) insert instruction FLIP_PE (P) (with execution in step 60 and 64) earlier, and finish the back at other program block and insert instruction RESTORE_PE (P).
If data routing was that (in other words, PE=0), instruction SAVE_PE (P) increases and to be stored in its initial value among the register P and to be-1 indication illegal state at that time.Otherwise instruction can't be changed the value of indication.As a result, whether the value of test in register less than 0, and whether so can determining, the PE state in past data path is the state that enables or forbid.
Instruction RESTORE_PE (P) carries out two functions.If the value of PE state indication is greater than-1 (in other words, the PE state of the data routing of storage is an illegal state), the PE in instruction RESTORE_PE (P) setting data path is an illegal state.Otherwise be enabled state.If value then instructed RESTORE_PE (P) also to reduce the value of the indication of the PE state that is stored in register P more than or equal to 0 o'clock.Otherwise instruction RESTORE_PE (P) can not change the value of indication of the PE state of storage.In this example, the value of indication can not reduce to and be lower than-1.
Instruction SAVE_PE (P) is that and instruction RESTORE_PE (P) occurs together always.At last, if regardless of PE state when carrying out program block whether (or) change, if enable the PE state if the data routing before the beginning of program block is in, it still reverts back to the PE state that enables if then finish the back at program block.
For example, think, if data routing is in the PE state that enables when entering program block.The value of institute's store status indication is-1.The value of the state indication of both neither change storages of instruction SAVE_PE (P) and instruction RESTORE_PE (P).Therefore, if the value after program block finishes still is-1, and if data routing is designated as the PE state that enables when leaving program block.
In other words, if if data routing is under an embargo when entering program block, instruction SAVE_PE (P) causes the value of state indication to increase to 0 by-1.When if program block finishes, instruction RESTORE_PE (P) value of making subtracts back-1.Yet, because value is greater than 0, if the PE of data routing is configured to illegal state after leaving program block.
Instruction FLIP_PE (P) if be used for-then-" other " of other program block partly.The computing of instruction FLIP_PE (P) is the PE state according to the data routing of the present PE state of data routing and storage.Briefly, if " if " the execution forbidden data path of statement (in other words, making relevant PE position into 0 by 1), then instruct FLIP_PE (P) enable data path (in other words, changeing back 1) once again with the PE position.Yet when if program block begins, data routing is enabled (in other words, the PE=1 of storage), and if program block execute the back data routing still be enabled, the instruction FLIP_PE (P) data routing is forbidden (in other words, PE being changed over 0).At last, if the PE state of data routing of storage for forbidding (PE=0), if then after executing program block, will continue the forbidden data path.In this example, instruct FLIP_PE (P) that data routing will be kept and forbid (PE=0).The computing of instruction FLIP_PE (P) is summarised in following table:
| The PE of storage | " if " afterwards PE | PE after FLIP |
| ????0 | ????0 | ????0 |
| ????0 | ????1 | ????X |
| ????1 | ????0 | ????1 |
| ????1 | ????1 | ????0 |
Correspond to Fig. 3, if table 100 expression utilizes instruction SAVE_PE, RESTORE_PE and FLIP_PE to be example at the condition program block 101 that comprises two sequential operations 102 and 104 and other program blocks 106.In this example, if if sequential operation 104 is nested in sequential operation 102 and other sequential operation 106.This table comprises the coding and decoding (assembly code) 110 that stub code 108 (stub of program code 108) and single instruction multiple data path compiler are produced.The register of four data paths DP0 of this table 100 diagram coding and decoding 110 and manipulation single instruction multiple data path processor 10, DP1, DP2, DP3.In this table, P1 and P2 are illustrated in the parallel register of storing data respectively during the executive condition program block and being used.P3 is the register of the value of storage PE state indication, and PE is the register (22 among Fig. 1) in order to the PE position of storing each data routing.
In this example, the executive condition program block 101 before, data routing DP0, DP1 and DP2 enable and DP3 forbids.Shown in row 111.
As described above, if compiler inserted instruction SAVE_PE (P3) 112 before first program block 102, at second (nested) if insert instruction SAVE_PE (P3) 114 before the program block 104, if the place of leaving at second program block inserts RESTORE_PE (P3) 116, begin the place at other program block 106 and insert instruction FLIP_PE (P3) 118, and insert instruction RESTORE_PE (P3) 120 in other program block 106 endings.
Shown in row 122, the data value that is stored in register P1 is initialized to 1,0 ,-1 and-1 respectively.Shown in row 124, originally register P2 does not use.The initialized PE state of the data routing that row 111 is as shown above.The computing of 112 SAVE_PE (P3) 112 is instructed in row 127 diagrams.Because DP0-DP2 does not increase their initial value-1 at present for enabling so these data routings are stored in the value of P3 (row 126).But because DP3 is for forbidding that instruction sAVE_PE (P3) 112 makes the value of the DP3 that is stored in P3 increase to 0.
The computing of row 128 expression if statements 102.Especially, if P1 more than or equal to 0 and the present state of data routing for enabling, then the PE state of data routing is for enabling.Because the P1 of DP0 and DP1 more than or equal to 0 and PE for enabling (row 111), so the PE in these two data paths is for enabling.Because the P1 of DP2 and DP3 is not more than or equal to 0, so PE is for forbidding.
Be expert at 130, the P2 of DP0 and DP1 is set at 1.Because DP2 and DP3 are for forbidding, so the content of the P2 of these data routings does not change.
If row 132 is illustrated in and instructs the computing of SAVE_PE (P3) 114 in the program block 104.(as row 128 expressions) for enabling because the present PE state of DP0 and DP1, instructs 114 values that can't increase these data routings that are stored in register P3.Yet instruction 114 increases the value of DP2 and the DP3 be stored in P3, and its former because these data routings are for forbidding.
The computing of row 134 expression if statements 104.DP0 is still for enabling, but DP1 changes to and forbids.DP2 and DP3 are still for forbidding.
Shown in row 135, in next computing, the value that is stored in the DP0 of P2 changes to 2, so because DP1 forbids that the value of DP1 still is 1.
If row 136 and 138 expressions are positioned at the operation result of instruction RESTORE_PE (P3) 118 of the end point of program block 104.Again call the execution of (recall) instruction RESTORE, if the value of state indication less than 0 then enable data path (PE is set as 1), just otherwise forbid, if the value of indication is greater than 0 then reduce the value of state at present.Apply mechanically these rules in this example, data routing DP0 because instruction SAVE_PE (P3) 114 stored enable (as-1 value that P3 stored of row 132) state still for enabling (PE=1).Because DP1 is in enabled state before entering if statement 104, so instruction RESTORE_PE (P3) 116 replys data routing DP1 for enabling the PE state.Because DP2 and DP3 are for forbidding, so they keep forbidding (shown in row 132) before if statement 104.In addition, the DP0 and the present value-1 of DP1 that are stored in P3 are not changed, and the DP2 and the present value of DP3 that are stored in P3 are reduced to-1 and 0 respectively.Row 128 and 136 relatively is if if clearly the value of the value of PE state when leaving program block 104 of DP0-DP3 when entering program block 104 is identical.
The influence of the PE state of 118 pairs of PE positions of row 140 FLIP_PE of presentation directives (P3).Indicate at this, other statement 106 is appearance with if statement 102.Therefore, the PE state of data routing has correlativity with the PE state that instructs SAVE_PE (P3) 112 (shown in row 127) to be stored.Because the DP0 of storage and the PE state of DP1 are for enabling, and DP0 and DP1 are current for enabling, so instruct FLIP_PE (P3) 118 to forbid these data routings.The PE state of DP0 and DP1 is changed into 0 (shown in row 140) as a result.
On the other hand, the PE state that DP2 stored is for to enable (shown in the value-1 of row 127), and the present PE state of DP2 is to forbid (shown in the PE=0 of row 138).Therefore, instruction FLIP_PE (P3) 118 enables DP2 (shown in the PE=1 of row 140).
The PE state of the data routing DP3 that is stored as instruction SAVE_PE (P3) 112 (shown in row 127) when forbidding, then still (shown in the PE=0 of row 138) forbidden in maintenance.Therefore, instruction FLIP_PE (P3) 118 keeps DP3 for forbidding.Shown in the PE=0 of row 142.
Because have only data routing DP2 for enabling at present, the certain operations in other statement 106 is only carried out by data routing DP2.Shown in row 142.
Row 144 and 146 is illustrated in the result of the REsTORE_PE (P3) 120 that executes instruction when condition program block 108 finishes.Because the value of the indication of the PE state that DP0-DP2 is present is-1 (shown in row 138), instruction RESTORE_PE (P3) 120 specifies DP0-DP2 for to enable PE state (shown in the PE=1 of row 144), and does not change the value (shown in row 146) of indication.That is, DP0 and DP1 revert back to enabled state, and DP2 still remains enabled state.On the other hand, because DP3 does not enable, instruction RESTORE_PE (P3) 120 maintains the state of forbidding (shown in the PE=0 of row 144) with DP3, and the P3 value of DP3 is reduced to-1 (shown in row 146) by 0 (shown in row 138).
By row 111 and 144 relatively, the value of the value when clearly the state of DP0-DP3 finishes when condition program block 108 during with entry condition program block 108 is identical.
During the condition program, can come in conjunction with storage PE state and setting PE position with branch computing.Openly in the application of (copending) this viewpoint is being discussed in more detail in the lump.Lay down a definition with following instruction:
if(SAVE_PE(PE)，PE＝Pa＝0)go?to?X
This instruction process " if " all work that need of statement.According to the principle of above-mentioned discussion, SAVE_PE (PE) with the present PE state storage of data routing in register Pb.Set the PE position according to the content of register Pa, and if equal 0 then branch instruction will guide to purpose X.For example, if all PE positions all are set as 0, the branch instruction of data routing is walked around remaining piece of (in other words, skipping) condition program block, is the work that enables to carry out any condition program block because there is not a data routing.
Similarly, the FLIP instruction comes combination with a branch instruction, comes for example with following instruction:
if(FLIP_PE(Pb))?go?to?X
This instruction will be inverted the PE position according to the principle of above-mentioned discussion, and if they all are not set then branch instruction will guide to purpose X.Mode according to this, if they all are positioned at when forbidding the PE state, then data routing will be walked around " other " handling procedure afterwards.
Whether determine to produce the function of one of them or two branch instructions by program code.This is meant that if get one of them branch instruction, then ratio is very fast with skipping work and program run by definition.If the programmer wants program that arranged identical working time, no matter whether the condition (for example, if program code must satisfy real-time restriction (deadlines)) of branch is provided, he or she will set decision bits (DET) in a plurality of registers of processor.If set DET, even the PE state of all data routings when forbidding, does not have a branch instruction to be performed.
The preferred embodiments of the present invention without departing from the spirit and scope of the present invention, can be made changes and improvements.In addition, other embodiment is all in the claim scope.
Claims (24)
1. one kind in order to keep the PE status method of data routing during the condition program, comprising:
The state storage that before above-mentioned condition program present little processing of above-mentioned data routing is enabled becomes the indication in this path; And
During above-mentioned condition program, handle above-mentioned indication, to be reflected in the variation of above-mentioned little processing enabled state of contingent above-mentioned data routing during the above-mentioned condition program.
2. the method for claim 1 wherein also comprises:
After the condition program, reply the state that above-mentioned little processing of the above-mentioned data routing of storage enables according to the above-mentioned indication of at least one part.
3. method as claimed in claim 2 wherein also comprises:
In a plurality of data routings of the SIMD that carries out above-mentioned condition program each is carried out return phase.
4. the method for claim 1, wherein above-mentioned condition program comprises if program statement, and above-mentioned storing step comprises the value that above-mentioned indication is stored as the above-mentioned present microprocessor state of the above-mentioned data routing of expression.
5. method as claimed in claim 4, wherein above-mentioned maneuvering sequence comprise according to stating the microprocessor state on the above-mentioned data routing during the above-mentioned condition program and change above-mentioned value.
6. method as claimed in claim 5, wherein above-mentioned maneuvering sequence comprises:
If the above-mentioned microprocessor state of above-mentioned data routing is when forbidding during storing step, then will increase above-mentioned value.
7. method as claimed in claim 4, wherein maneuvering sequence comprises:
If during the condition program, when the above-mentioned microprocessor state of above-mentioned data routing does not change, then will not change the initial value of value.
8. method as claimed in claim 4 wherein also comprises:
If after carrying out above-mentioned program statement, reply the above-mentioned microprocessor state of above-mentioned data routing according to the above-mentioned value of at least one part.
9. method as claimed in claim 8, wherein return phase comprises:
When if above-mentioned value surpass to limit, then specify above-mentioned data routing for forbidding the PE state, otherwise specify above-mentioned data routing for enabling the PE state.
10. method as claimed in claim 9 wherein also comprises:
If above-mentioned value surpasses when limiting, change above-mentioned value.
11. comprising, method as claimed in claim 10, wherein above-mentioned change reduce above-mentioned value.
12. method as claimed in claim 8, wherein the condition program block comprises:
If a plurality of above-mentioned conditional statements, and also comprise, if above-mentioned storage, manipulation or return phase carried out in each above-mentioned program statement.
13. method as claimed in claim 4, wherein the condition program block comprises, other program statement, above-mentioned maneuvering sequence also is included in to be carried out before above-mentioned other program statement, if whether the program of the above-mentioned program statement of foundation changes the above-mentioned PE state of above-mentioned data routing, judge to change above-mentioned value.
14. method as claimed in claim 13, if wherein the PE state of the above-mentioned storage of above-mentioned data routing is if that the said procedure of enabled state and above-mentioned program statement is changed into illegal state with above-mentioned PE state, above-mentioned steering program comprises and changes above-mentioned value to represent above-mentioned enabled state.
15. method as claimed in claim 13, if wherein the PE state of the above-mentioned storage of above-mentioned data routing is if that the said procedure of enabled state and above-mentioned program statement does not change above-mentioned PE state, above-mentioned steering program comprises and changes above-mentioned value to represent above-mentioned illegal state.
16. method as claimed in claim 13, if wherein the PE state of the above-mentioned storage of above-mentioned data routing is an illegal state, above-mentioned steering program comprises keeps above-mentioned value to represent above-mentioned illegal state.
17. computer instruction set in order to maintain the PE state of the data routing during the condition program, comprises the instruction that makes above-mentioned data routing produce following effect:
Before the condition program, with the indication that is this path of the present PE state storage with above-mentioned data routing; And
During above-mentioned condition program, handle above-mentioned indication, to be reflected in the variation of above-mentioned little processing enabled state of contingent above-mentioned data routing during the above-mentioned condition program.
18. method as claimed in claim 17 wherein also comprises instruction, makes above-mentioned data routing after above-mentioned condition program, replys the PE state of the above-mentioned storage of above-mentioned data routing according to the above-mentioned indication of at least one part.
19. method as claimed in claim 17, wherein above-mentioned condition program comprises if program statement, and above-mentioned instruction also comprises makes above-mentioned data routing store above-mentioned indication, in order to the value of the PE state of the above-mentioned storage of representing above-mentioned data routing.
20. method as claimed in claim 19 wherein also comprises instruction, if make above-mentioned data routing after above-mentioned program statement executes, replys the PE state of the above-mentioned storage of above-mentioned data routing according to the above-mentioned value of at least one part.
21. method as claimed in claim 19, wherein above-mentioned condition program block comprises other program block, above-mentioned instruction set comprises that also instruction makes above-mentioned data routing, if whether the program of the above-mentioned program statement of foundation changes the above-mentioned PE state of above-mentioned data routing, before carrying out above-mentioned other program statement, change or do not change above-mentioned value.
22. the single instruction multiple data path processor comprises a plurality of data routings, each above-mentioned data routing has the ability of the PE state of keeping this path, therefore makes above-mentioned data routing by carrying out more than one instruction during the condition program:
The state storage that before above-mentioned condition program present little processing of above-mentioned data routing is enabled becomes the indication in this path; And
During above-mentioned condition program, handle above-mentioned indication, to be reflected in the variation of above-mentioned little processing enabled state of contingent above-mentioned data routing during the above-mentioned condition program.
23. the performed computer instruction set of data routing during the condition program comprises that instruction makes above-mentioned data routing:
Before above-mentioned condition program, make the present PE state storage of above-mentioned data routing become indication;
Set up the above-mentioned PE state of above-mentioned condition program; And
If when the PE state of above-mentioned foundation did not satisfy the condition of above-mentioned instruction, branch instruction was walked around above-mentioned cond.
24., comprise also that wherein instruction makes above-mentioned data routing as claim 23 a described instruction set:
If when the incident of choosing takes place, be inverted the PE state of above-mentioned foundation; And if above-mentioned inverted PE state is when satisfying the condition choose, branch instruction is walked around above-mentioned cond.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US72399400A | 2000-11-28 | 2000-11-28 | |
| US09/723,994 | 2000-11-28 |
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| CN1486465A true CN1486465A (en) | 2004-03-31 |
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| CNA01821987XA Pending CN1486465A (en) | 2000-11-28 | 2001-11-09 | Handling conditional processing in a single instruction multiple datapath processor architecture |
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| EP (1) | EP1348167A2 (en) |
| CN (1) | CN1486465A (en) |
| AU (1) | AU2002241759A1 (en) |
| DE (1) | DE01988453T1 (en) |
| TW (1) | TWI236622B (en) |
| WO (1) | WO2002046885A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100383728C (en) * | 2005-08-25 | 2008-04-23 | 应广科技股份有限公司 | Program address arithmetic organ framework capable of implementing waiting and delaying orders |
| CN107491288A (en) * | 2016-06-12 | 2017-12-19 | 合肥君正科技有限公司 | A kind of data processing method and device based on single instruction multiple data stream organization |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6970985B2 (en) | 2002-07-09 | 2005-11-29 | Bluerisc Inc. | Statically speculative memory accessing |
| US20050114850A1 (en) | 2003-10-29 | 2005-05-26 | Saurabh Chheda | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
| US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
| US8607209B2 (en) | 2004-02-04 | 2013-12-10 | Bluerisc Inc. | Energy-focused compiler-assisted branch prediction |
| GB2411745B (en) | 2004-03-02 | 2006-08-02 | Imagination Tech Ltd | Method and apparatus for management of control flow in a simd device |
| US20080126766A1 (en) | 2006-11-03 | 2008-05-29 | Saurabh Chheda | Securing microprocessors against information leakage and physical tampering |
| US8923510B2 (en) * | 2007-12-28 | 2014-12-30 | Intel Corporation | Method and apparatus for efficiently implementing the advanced encryption standard |
| GB2470782B (en) | 2009-06-05 | 2014-10-22 | Advanced Risc Mach Ltd | A data processing apparatus and method for handling vector instructions |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5616248A (en) * | 1979-07-17 | 1981-02-17 | Matsushita Electric Ind Co Ltd | Processing system for interruption |
| US4434461A (en) * | 1980-09-15 | 1984-02-28 | Motorola, Inc. | Microprocessor with duplicate registers for processing interrupts |
| GB2211638A (en) * | 1987-10-27 | 1989-07-05 | Ibm | Simd array processor |
| JPS63245529A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Register saving and restoring device |
| US6282628B1 (en) * | 1999-02-24 | 2001-08-28 | International Business Machines Corporation | Method and system for a result code for a single-instruction multiple-data predicate compare operation |
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2001
- 2001-11-09 DE DE0001348167T patent/DE01988453T1/en active Pending
- 2001-11-09 WO PCT/US2001/050992 patent/WO2002046885A2/en not_active Application Discontinuation
- 2001-11-09 CN CNA01821987XA patent/CN1486465A/en active Pending
- 2001-11-09 EP EP01988453A patent/EP1348167A2/en not_active Withdrawn
- 2001-11-09 TW TW90127897A patent/TWI236622B/en not_active IP Right Cessation
- 2001-11-09 AU AU2002241759A patent/AU2002241759A1/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100383728C (en) * | 2005-08-25 | 2008-04-23 | 应广科技股份有限公司 | Program address arithmetic organ framework capable of implementing waiting and delaying orders |
| CN107491288A (en) * | 2016-06-12 | 2017-12-19 | 合肥君正科技有限公司 | A kind of data processing method and device based on single instruction multiple data stream organization |
| CN107491288B (en) * | 2016-06-12 | 2020-05-08 | 合肥君正科技有限公司 | Data processing method and device based on single instruction multiple data stream structure |
Also Published As
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|---|---|
| WO2002046885A3 (en) | 2002-08-22 |
| TWI236622B (en) | 2005-07-21 |
| WO2002046885A9 (en) | 2003-08-07 |
| EP1348167A2 (en) | 2003-10-01 |
| AU2002241759A1 (en) | 2002-06-18 |
| DE01988453T1 (en) | 2004-04-22 |
| WO2002046885A2 (en) | 2002-06-13 |
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