CN1485858A - Device and method for selecting power down exit - Google Patents
Device and method for selecting power down exit Download PDFInfo
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- CN1485858A CN1485858A CNA031472761A CN03147276A CN1485858A CN 1485858 A CN1485858 A CN 1485858A CN A031472761 A CNA031472761 A CN A031472761A CN 03147276 A CN03147276 A CN 03147276A CN 1485858 A CN1485858 A CN 1485858A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Abstract
A semiconductor integrated circuit and a memory device capable of selecting power-down exit speed and power-save modes and method thereof are provided. The memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.
Description
Technical field
The present invention relates to be used to control the apparatus and method of semiconductor storage unit, particularly circuit or have is used for can select power to descend to withdraw from the memory device of the circuit of pattern control store and control store operation.The application requires the right of priority of the provisional application 60/395,276 of on July 12nd, 2002 application, and it is whole openly to be incorporated herein by reference.
Background technology
The operating speed and the capacity of semiconductor storage unit increase constantly, and it will be combined in the memory device such as the memorizer control circuit of clock synchronization unit.The clock synchronization unit be used to produce with such as the synchronous internal clock signal of the external timing signal of system clock.Internal clocking is used to synchronously drive the memory device such as SDRAM and DDR-SDRAM.The clock synchronization unit can be phaselocked loop (PLL), delay lock loop (DLL) or working cycle correcting circuit.
The PLL circuit generally comprises phase detectors, charge pump, loop filter, and voltage controlled oscillator (being called " VCO " later on).By the phase place (being VCO output) that compares external timing signal and internal clock signal, phase detectors produce fluctuating (the up or down) signal based on difference between its phase place, and this fluctuating signal is delivered to loop filter.Charge pump produces the constant output voltage according to this fluctuating signal, and this constant output voltage is delivered to loop filter.The output voltage of loop filter filtering charge pump is to eliminate the control voltage that radio-frequency component and output are used to control VCO.The frequency that the VCO input control voltage is directly proportional therewith with output.As a result, the PLL circuit makes output frequency and incoming frequency synchronous, with the phase place of synchronous inside and outside clock signal.
In the DLL circuit, when the phase place of synchronous outside and internal clock signal, the phase place of DLL circuit delay external timing signal.DLL is used in the DRAM device publicly.An exemplary DLL circuit is being authorized the U.S. Pat N5 of Lee, and is open in 614,855.Another exemplary DLL circuit changes the length of lag line, and clock signal is passed this lag line.Use is used for selectively starting the coarse delay chain can realize the lag line change with the tapping point of thin delay chain.It is poor with detected phase that phase detectors are coupled to lag line.
Other phase place or working cycle are proofreaied and correct the register form that (DCC) circuit can be the phase-delay value of the inside and outside clock signal of storage.Phase-delay value is stored when power descends (power-down) and is loaded when withdrawing from power decline, to lock inside and outside clock signal.In each above-mentioned clock synchronization circuit, the operation of clock synchronization circuit and clock signal is fanned out to a large amount of power of the necessary driving buffer depletion of SDRAM internal circuit.
For preserving power, when not needing access sdram, SDRAM can be placed in the power drop mode.Memory device, mode register set and power decline circuit that Fig. 1 to 3 explanation is traditional.
Fig. 1 is illustrated in the mode register set of using in Fig. 2 memory device (MRS).MRS has address field A0-A12, has wherein stored the information that is used to control the SDRAM operator scheme (for example burst length, train of impulses type (BT), CAS stand-by period, and test pattern).This information is sent from CPU (central processing unit) (CPU), is operated in different mode to guide memory device.Usually, burst length, train of impulses type, CAS stand-by period and test pattern use field A0-A2, field A3, field A4-A6 and field A7 respectively.Field A8-A12 is preserved for using from now on (RFU), and they are set to " 0 " usually during normal running.
Fig. 2 represents traditional memory device, and it comprises parts: the storage core 100 with memory cell array; Have address field and the mode register 250 basic as operation mode information that Fig. 1 illustrates; Address decoder 270 and 280 is used to produce the DLL circuit 230 of internal clocking ICLK; Clock, address and data buffer; With commands buffer and demoder 240.Order from CPU or memory controller is received by commands buffer and demoder 240.These orders processed and the relevant parts that are distributed to such as mode register 250 are with visiting storage core 100.External clock ECLK is received by clock buffer 210, and the clock ECLK1 that is cushioned is imported into DLL circuit 230 by DLL enable circuits 220.DLL circuit 230 produces the internal clocking ECLK that is used to drive storage core 100.Storage core 100 can be placed in power and descend or standby mode, and here, the storage unit that storage core is 100 li is not accessed, and saves electric power.The power that sends from commands buffer and the demoder 240 order PWDN that descends is used to memory device is placed going into (input) or going out (withdrawing from) state of power drop mode.This is to be finished by the circuit that Fig. 3 represents.As shown, external timing signal ECLK is cushioned by clock buffer 210, and is delivered to DLL circuit 230 by door 224, produces the internal clocking ICLK that is synchronized to ECLK here, to drive storer.When hope places the power drop mode with memory device, forbid logic gate 224 in the effective order (power input drop mode) of PWDN (for example logical one), it is invalid that it makes from the internal clock signal ICLK of DLL circuit 230 outputs.Do not have clock signal, storage core 100 can not be worked, and it is placed in " power decline " pattern, saves power consumption.
In conventional memory device and above-mentioned power drop mode operation, notice that although internal clock signal ICLK is disabled by the clock ECLK1 that forbids being cushioned, DLL circuit 230 is not turned off on DLL enable circuits 220 as Fig. 1 to 3 explanation.Therefore, further power saving if desired, DLL circuit 230 also can be turned off.Should be appreciated that the explanation of DLL circuit also is applicable to other clock synchronization circuit here, such as PLL and circulation correcting circuit.As explanation early, DLL or PLL comprise such as phase detectors, some parts of charge pump and VC0.Turn-off clock synchronization circuit and realized sizable electric power saving.But,, need the more time to reach the phase locking or synchronously between inside and outside clock by turn-offing PLL or DLL.Usually, approximately need at least six (6) clock period to make internal clock signal and external timing signal synchronous.Therefore, have at electric power and save and from the power drop mode, wake up or withdraw from the compromise selection between the seeking time wanted.
From the power drop mode, wake up or withdraw from device is brought back to normal running from power decline or standby mode.After power decline exits command, before can suitably operating normal running, device needs some time.Normal running can be valid function (perhaps effective order), read operation (read command) or write operation (write order) etc.
Therefore, wish to have the memory device that to select a plurality of battery saving modes.
Summary of the invention
A kind of circuit that is used to control storer with the memory cell array of arranging with row and column, this circuit comprises: at least one address decoder is used for this decode address that decode address field and output are used for addressable memory; And mode register, being used for memory module registers group (MRS) data, these data are used at least one based on a plurality of operator schemes of address field predetermined memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern.
This circuit also preferably includes: clock generator is used for producing and the external timing signal clock signal synchronous, with to the storer timing; With the generator enable circuits, be used for receiving directly or indirectly the order that descends of external timing signal and power, with based on this power decline command selection enable external timing signal is outputed to clock generator.The generator enable circuits also receive be used for that enable power selectively descends order withdraw from mode select signal (PD), this withdraws from mode select signal (PD) and is used to select at least one power to descend to withdraw from pattern.
These a plurality of power pattern that withdraws from that descends comprises and wakes the pattern of withdrawing from a slow speed up and wake the pattern of withdrawing from fast up, wherein, from receiving first number within the clock period and wake the pattern of withdrawing from a slow speed up from receiving second number within the clock period that wakes the pattern of withdrawing from fast up, memory operation is in normal mode, and wherein second number is less than first number.Preferably, first number is at least 5 and second number and is at least 2.
The clock enable circuits receives and withdraws from mode select signal (PD) and output auxiliary power dropping signal (SPD), so that the circuit power beyond the storage unit descends.Circuit beyond the storage element comprises the clock generator part at least.Address field comprises A0 to A12, withdraws from mode select signal (PD) corresponding to A12.
Storer is SDRAM or DDR SDRAM.Clock generator is phaselocked loop, delay lock loop, working cycle correcting circuit.Address field and PWDN order provide from Memory Controller.
The storage system that is used to control the storer with the memory cell array of arranging with row and column also is provided, and this storage control system comprises: at least one address decoder is used for this decode address that decode address field and output are used for addressable memory; And mode register, being used for memory module registers group (MRS) data, these data are used at least one based on a plurality of operator schemes of address field designated memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern; And memory controller, be used to provide the signal and the address field that are used for producing MRS.Also comprise: clock generator is used for producing and the external timing signal clock signal synchronous, with to the storer timing; With the generator enable circuits, be used for receiving directly or indirectly the order that descends of external timing signal and power, with based on this power decline command selection enable external timing signal is outputed to clock generator.
The generator enable circuits also receive be used for that enable power selectively descends order withdraw from mode select signal (PD), this withdraws from mode select signal (PD) and is used to select at least one power to descend to withdraw from pattern.
The circuit that is used to control the storer with the memory cell array of arranging with row and column also is provided, and this circuit comprises: at least one address decoder is used for this decode address that decode address field and output are used for addressable memory; And logical circuit, be used to receive signal based at least one of a plurality of operator schemes of address field predetermined memory, wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern.
This circuit also comprises: clock generator is used for producing and the external timing signal clock signal synchronous, with to the storer timing; With the generator enable circuits, be used to receive external timing signal and power decline order, with based on this power decline command selection enable external timing signal is outputed to clock generator, wherein the generator enable circuits also receive be used for that enable power selectively descends order withdraw from mode select signal (PD), this withdraws from mode select signal (PD) and is used to select at least one power to descend to withdraw from pattern.
The method that is used to control the storer with the memory cell array of arranging with row and column also is provided, and this method comprises: decode address field and output are used for this decode address of addressable memory; And memory module registers group (MRS) data, these data are used at least one based on a plurality of operator schemes of address field predetermined memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern.
This method also comprises step: produce the internal clocking that is synchronized to external clock by clock generator, this internal clocking is used for the storer timing; Withdraw from one of pattern with descend based on power order and this a plurality of power declines and forbid clock generator.
This method also comprises step: an address bit of address field is assigned as is used to select a plurality of power to descend to withdraw from the mode select signal that withdraws from of one of pattern.Preferably, address bit be A0 to the A8 of A12 address field to A12 (RFU field) any one.
Description of drawings
Fig. 1 represents traditional mode registers group (MRS).
Fig. 2 represents conventional memory device.
Traditional clock enable circuits in Fig. 3 presentation graphs 2 memory devices.
Fig. 4 represents the memory device according to the embodiment of the invention.
Fig. 5 represents the mode register set according to the embodiment of the invention.
Fig. 6 represents the circuit that is used for control store according to the embodiment of the invention.
Fig. 7 A represents to withdraw from according to the power decline of the embodiment of the invention sequential chart of pattern operation.
Fig. 7 B represents to withdraw from according to another power decline of the embodiment of the invention the sequential chart of pattern operation.
Fig. 8 represents memory device in accordance with another embodiment of the present invention.
Embodiment
According to the embodiment of the invention, when storer when the power drop mode falls back on normal mode, wakeup time and power consumption that can selection memory.Normal mode can be effective order, read command or write order.This selection can descend based on the power of storage in mode register (MRS) and withdraw from information.If power-saving is preferred in SDRAM, for example in mobile product, but then select to wake up more slowly the pattern of saving power.If storer (for example SDRAM) is employed in the high-performance calculation device, it is preferred waking up at a high speed here, then selects to wake up fast power decline and withdraws from pattern.
Fig. 4 represents the memory device according to the embodiment of the invention.Memory device 10 comprises storage core 100, and it is the DRAM with the memory cell array of arranging with row and column.DRAM is SDRAM or DDR SDRAM preferably.Row address buffer and demoder 270 provide row address and column address with column buffer and demoder 280 during memory read/write operations.Data to storage core 100 are transfused to by data buffer 290, and address buffer 260 destination address fields are preferably A0-A12, and the address is offered row address buffer and demoder and column buffer and demoder and mode register 350.Commands buffer and demoder 240 receive the decode order from external source according to present embodiment, and by the peripheral circuit (not shown) decoded order are offered storage core 100.The decoded order of commands buffer and demoder 240 comprises the mode register set (MRS) that is used to be input to mode register 350 and is used to be coupled to the power decline PWDN order of DLL enable circuits 320.DLL circuit 230 is clock synchronization circuits, is used to produce the internal clocking ICLK that is used for driving storage core 100.Power decline PWDN order is used to preferably by forbidding internal clocking ICLK, placing standby mode that storage core power is descended storage core 100.DLL circuit 230 can be to adopt feedback and such as PLL, DLL, any clock synchronization circuit of phaselocked loops such as DCC.Here DLL is used to illustrate the preferred embodiments of the present invention.Clock buffer 210 receives and buffering external clock ECLK, and provides the clock signal ECLK1 that is cushioned to DLL enable circuits 320.
According to a preferred embodiment of the invention, power decline is withdrawed from mode select signal (PD) and is provided for DLL enable circuits 320 by mode register 350, withdraws from pattern to provide selectable a plurality of power to descend.These a plurality of patterns of exiting command preferably include quick awakening mode and power-saving or awakening mode at a slow speed, and wherein awakening mode preferably offers the user from the power drop mode with comparatively fast waking up of SDRAM in two (2) to four (4) clock period fast.Power-saving or wake the pattern of withdrawing from a slow speed up at least five (5) but be preferably and give the further power-saving of user in six (6) to ten (10) clock period but require more time from withdrawing from of descending of SDRAM power.Power descends and to withdraw from mode select signal PD and output to DLL enable circuits 320 from mode register 350 it is used for optionally controlling DLL enable circuits 320 and DLL enable circuits 230.
Fig. 5 is illustrated in the use of the address field A0-A12MRS in the mode register 350.According to present embodiment, the A12 of address field A0-A12 is used to provide power to descend and withdraws from mode select signal PD.Being preserved for of mode register 350 uses one of (RFU) field to be made into corresponding to A12 from now on.According to present embodiment, signal to waking the pattern of withdrawing from fast up at logical zero or the PD of A12, logical one signals and withdraws from pattern for waking up at a slow speed or economizing on electricity.Be preferably signal although those skilled in the art understand A12 easily, can use any other address bit of address field corresponding to PD.For the high performance device such as desktop PC, manufacturer or user can select to wake up fast the pattern of withdrawing from.Wake up at a slow speed or economize on electricity that withdraw from can be by such as the manufacturer of the mobile device of PDA or user-selected.
Fig. 6 represents to be used for according to the embodiment of the invention circuit of control store.Clock buffer 210 receives and buffering external clock ECLK, and the clock ECLK1 that is cushioned is offered DLL enable circuits 320.Power decline enters/withdraws from PWDN and receives by the logical circuit in the DLL enable circuits 320.Power decline is withdrawed from mode select signal PD and is imported into logic gate 322, and it finishes operating with non-(NAND) of PWDN and PD, with output DLL_EN signal.The DLL_EN signal is imported into another logical circuit, is in the case and door 324.With another input of door 324 be clock ECLK1 through buffering.The DLL_EN signal also is coupled to DLL circuit 230.For the purpose of illustration, power " entering " order that descends is to signal by the PWDN that is in " 1 ", and the PWDN that is in " 0 " signals and is power decline " withdrawing from ".When PD was " 0 ", it was selected to wake the pattern of withdrawing from fast up, when PD is " 1 ", woke (economize on electricity) at a slow speed up and withdrawed from selected.When PD and PWDN both were in " 1 ", signaling entered and wakes the pattern of withdrawing from up at a slow speed for power descends, and the DLL_EN signal be " 0 ", the external clock ECLK1 of inhibit gate 324 and obstruction buffer stock, and ECLK2 is maintained at level "0".Internal clocking ICLK is not produced by DLL circuit 230.Storage core 100 is placed in " power decline " or " standby " pattern.According to a preferred embodiment of the invention, the DLL_EN signal also is used to turn-off the circuit in the DLL circuit 230, further reduces the overall power of memory device.According to another embodiment, the DLL_EN signal also is used as auxiliary power decline (SPD) signal, to send the signal such as other internal circuit shutoff of impact damper and driver, further saves electric power (being power saving) thus.For SDRAM withdraws from from this power descends selection and pattern, DLL circuit 230 requires the long period (for example six (6) cycles) to obtain phase-locked and to produce inner ICLK.According to present embodiment, when PWDN was " 0 ", in power decline " withdrawing from " pattern, internal clocking ICLK was switched on always, has nothing to do and withdraw from model selection PD with power decline.When PWDN is high " 1 ", perhaps descending at power enters pattern, and PD is when being in " 0 ", and fast power descends, and to withdraw from pattern selected, and internal clocking ICLK is switched on, and DLL circuit 230 is being opened always.In this power decline exit structure, power descends, and to withdraw from be (for example being two (2) clock period) faster.The DLL_EN signal preferably is not used to turn-off at other circuit that wakes up fast in the pattern of withdrawing from such as clock and data buffer.Those skilled in the art see that easily the logic gate of using 322 and 324 can be replaced by its boolean (Boolean) equivalence in DLL enable circuits 320, and effectively/forbid that logic can be inverted, to realize as DLL is enabled 320 identical functions that illustrate.And, any feedback circuit of DLL circuit 230 representative, it requires lock-up cycle finishing such as at PLL, DLL, synchronous among the DCC (working cycle corrections) etc.Although two (2) clock period and six (6) cycles are respectively applied for fast and pattern is withdrawed from economize on electricity, in the present embodiment, those skilled in the art easily see, waking the pattern of withdrawing from fast up can be two (2) to four (4) clock period, it can be at least five (5) that pattern is withdrawed from economize on electricity, and six (6) are to eight (8) clock period or ten (10) clock period.
Fig. 7 A is illustrated in power and descends and to withdraw from, at a slow speed or the sequential chart of the memory device in the economize on electricity awakening mode.At time C1, the PD signal is converted to " 1 " by mode register 350 from address A12.After the time C3, run into the PDWN order that is in " 1 ", send out power decline entering signal.Within the identical clock period, DLL_EN is converted to " 0 ", forbids internal clocking ICLK and DLL circuit 230.After time C6, descend when exiting command (PWDN is converted to " 0 ") when having received power, DLL_EN reaches " 1 ", and DLL circuit 230 is enabled, so that external timing signal and internal clock signal ICLK is synchronous.During this cycle, it can be six (6), and eight (8) or ten (10) clock period, storer can not be accessed, is synchronized to the ECLK of time C12 up to internal clocking ICLK.
With reference to figure 7B, promptly wake the sequential chart of the pattern of withdrawing from fast up, from mode register 350, read at time C1 at the address of logical zero A12, and PD is in " 0 " always.The power decline entering signal PWDN that is in " 1 " is run into after time C3.In this structure, DLL_EN is maintained at " 1 " and the clock signal of generation from DLL circuit 230 is maintained at lock-out state.Internal clocking ICLK is held effectively, to drive storage core 100.Therefore, at time C6, exit command PWDN when reaching " 0 " when power descends, the effective order of storer, read command or write order can begin in two (2) clock period of time C8.
Fig. 8 represents memory device in accordance with another embodiment of the present invention.In the present embodiment, be to drive as memory device 10 illustrated in fig. 4 by memory controller 20.Order, address field and the external timing signal that before externally provides are provided by memory controller 20.Memory controller 20 can be any known controller that is used to control SDRAM.
According to the embodiment of the invention, when storer when the power drop mode is withdrawn into normal mode, wakeup time and power consumption that can selection memory.This selection can descend based on the power of storage in mode register (MRS) and withdraw from information.If it is preferred that the electric power among the SDRAM is saved, such as in mobile product, then selection wakes up more slowly but is the pattern of power saving.If storer (for example SDRAM) is employed in and wakes up at a high speed is in the high-performance of preferred computer, then selects to wake up fast power decline and withdraw from pattern.
Although embodiments of the invention have been described, they only are illustrative, do not limit the spirit and scope of the present invention.Present embodiment not only can be applied to SDRAM, and can be applied to memory device or the SIC (semiconductor integrated circuit) with DLL circuit.Although power descends the information that withdraws from by example be stored among the field A12 of mode register (MRS), this information can be stored in any other address field based on user-defined MRS.And, will understand, although the wakeup time of the DLL circuit of storing among the MRS is set to two (2)/six (6) clock period, can change this wakeup time.Power descends and withdraws from the operation that information can be used to not only control phaselocked loop (PLL) circuit, and controls the operation of Active Terminal circuit (on Die (circuit small pieces) terminal (ODT)) among the SDRAM.Therefore, without departing from the spirit and scope of the present invention, can carry out various improvement and variation.
Claims (24)
1. circuit that is used to control storer with the memory cell array of arranging with row and column, this circuit comprises:
At least one address decoder is used for the decode address field, and output is used for the decode address of addressable memory; And
Mode register is used for memory module registers group (MRS) data, and these data are used at least one based on a plurality of operator schemes of address field designated memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern.
2. circuit as claimed in claim 1 also comprises:
Clock generator is used to produce the internal clock signal synchronous with external timing signal, with to the storer timing; With
The generator enable circuits is used for receiving directly or indirectly the order that descends of external timing signal and power, with based on this power decline command selection enable external timing signal is outputed to clock generator.
3. circuit as claimed in claim 2, wherein the generator enable circuits also receive be used for that enable power selectively descends order withdraw from mode select signal (PD), this withdraws from mode select signal (PD) and is used for selecting descend at least one of the pattern that withdraws from of power.
4. circuit as claimed in claim 2, wherein these a plurality of power pattern that withdraws from that descends comprises and wakes the pattern of withdrawing from a slow speed up and wake the pattern of withdrawing from fast up.
5. circuit as claimed in claim 4, wherein, waking first number that the pattern of withdrawing from begins at a slow speed up within the clock period and from receiving second number within the clock period that wakes the pattern of withdrawing from fast up from receiving, memory operation is in normal mode, and wherein second number is less than first number.
6. circuit as claimed in claim 5, wherein first number is at least 5, the second numbers and is at least 2.
7. circuit as claimed in claim 2, wherein the generator enable circuits receives and to withdraw from mode select signal (PD) and to export supplemental capacity dropping signal (SPD), so that descend except the circuit power of storage unit.
8. circuit as claimed in claim 7, wherein the circuit except storage unit comprises the clock generator part at least.
9. circuit as claimed in claim 3, wherein address field comprises A0 to A12, withdraws from mode select signal (PD) corresponding to A8 any one to the A12 bit.
10. circuit as claimed in claim 1, wherein storer is SDRAM.
11. circuit as claimed in claim 1, wherein storer is DDR SDRAM.
12. circuit as claimed in claim 2, wherein clock generator is a phaselocked loop.
13. circuit as claimed in claim 2, wherein clock generator is a delay lock loop.
14. circuit as claimed in claim 2, wherein clock generator is the working cycle correcting circuit.
15. circuit as claimed in claim 2, wherein address field and power descend to ordering provides from Memory Controller.
16. a storage system that is used to control the storer with the memory cell array of arranging with row and column, this storage control system comprises:
At least one address decoder is used for the decode address field, and output is used for this decode address of addressable memory;
Mode register is used for memory module registers group (MRS) data, and these data are used at least one based on a plurality of operator schemes of address field designated memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern; With
Memory controller is used to provide the signal and the address field that are used for producing MRS.
17. system as claimed in claim 16 also comprises:
Clock generator is used to produce the internal clock signal synchronous with external timing signal, with to the storer timing; With
The generator enable circuits is used for receiving directly or indirectly the order that descends of external timing signal and power, with based on this power decline command selection enable external timing signal is outputed to clock generator.
18. system as claimed in claim 17, wherein the generator enable circuits also receive be used for that enable power selectively descends order withdraw from mode select signal (PD), this withdraws from mode select signal (PD) and is used for selecting descend at least one of the pattern that withdraws from of power.
19. a circuit that is used to control the storer with the memory cell array of arranging with row and column, this circuit comprises:
At least one address decoder is used for the decode address field, and output is used for this decode address of addressable memory; And
Logical circuit is used for receiving the signal based at least one of a plurality of operator schemes of address field designated memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern.
20. circuit as claimed in claim 19 also comprises:
Clock generator is used to produce the internal clock signal synchronous with external timing signal, with to the storer timing; With
The generator enable circuits is used to receive the order that descends of external timing signal and power, with based on this power decline command selection enable external timing signal is outputed to clock generator.
21. circuit as claimed in claim 20, wherein the generator enable circuits also receive be used for that enable power selectively descends order withdraw from mode select signal (PD), this withdraws from mode select signal (PD) and is used for selecting descend at least one of the pattern that withdraws from of power.
22. a method that is used to control the storer with the memory cell array of arranging with row and column, this method comprises:
Decode address field and output are used for this decode address of addressable memory; And
Memory module registers group (MRS) data, these data are used at least one based on a plurality of operator schemes of address field designated memory, and wherein these a plurality of operator schemes comprise that a plurality of power descend and withdraw from pattern.
23. method as claimed in claim 22 also comprises step:
Produce the internal clock signal that is synchronized to external timing signal by clock generator, this internal clock signal is used for the storer timing; With
Based on descend order and should a plurality of power declines withdraw from one of pattern and forbid clock generator of power.
24. method as claimed in claim 22 also comprises step:
An address bit of address field is assigned as withdraws from mode select signal, be used for selecting descend of the pattern that withdraws from of a plurality of power.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39527602P | 2002-07-12 | 2002-07-12 | |
| US60/395,276 | 2002-07-12 | ||
| US10/281,342 | 2002-10-28 | ||
| US10/281,342 US6650594B1 (en) | 2002-07-12 | 2002-10-28 | Device and method for selecting power down exit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1485858A true CN1485858A (en) | 2004-03-31 |
| CN100424784C CN100424784C (en) | 2008-10-08 |
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|---|---|---|---|
| CNB031472761A Expired - Lifetime CN100424784C (en) | 2002-07-12 | 2003-07-11 | Device and method for selecting power down exit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6650594B1 (en) |
| EP (1) | EP1381053B1 (en) |
| JP (1) | JP4195835B2 (en) |
| KR (1) | KR100521365B1 (en) |
| CN (1) | CN100424784C (en) |
| TW (1) | TWI236022B (en) |
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2002
- 2002-10-28 US US10/281,342 patent/US6650594B1/en not_active Expired - Lifetime
- 2002-12-06 KR KR10-2002-0077282A patent/KR100521365B1/en active IP Right Grant
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2003
- 2003-04-14 EP EP03252365A patent/EP1381053B1/en not_active Expired - Lifetime
- 2003-06-17 JP JP2003171704A patent/JP4195835B2/en not_active Expired - Fee Related
- 2003-07-11 CN CNB031472761A patent/CN100424784C/en not_active Expired - Lifetime
- 2003-07-11 TW TW092118994A patent/TWI236022B/en not_active IP Right Cessation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7487315B2 (en) | 2005-09-14 | 2009-02-03 | Via Technologies, Inc. | Accessing apparatus capable of reducing power consumption and accessing method thereof |
| CN1779849B (en) * | 2005-10-09 | 2011-04-20 | 威盛电子股份有限公司 | Access device with power consumption decreasement and access method thereof |
| CN101903953B (en) * | 2007-12-21 | 2013-12-18 | 莫塞德技术公司 | Non-volatile semiconductor memory device with power saving feature |
| TWI498920B (en) * | 2008-06-24 | 2015-09-01 | Hynix Semiconductor Inc | Clock driver device and semiconductor memory apparatus having the same |
| CN102081965A (en) * | 2011-02-21 | 2011-06-01 | 西安华芯半导体有限公司 | Circuit for generating inner write clock of dynamic random access memory (DRAM) |
| CN102081965B (en) * | 2011-02-21 | 2013-04-10 | 西安华芯半导体有限公司 | Circuit for generating inner write clock of dynamic random access memory (DRAM) |
| CN112863560A (en) * | 2019-11-26 | 2021-05-28 | 爱德斯托科技有限公司 | Memory device, method of controlling memory device, and host device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4195835B2 (en) | 2008-12-17 |
| US6650594B1 (en) | 2003-11-18 |
| CN100424784C (en) | 2008-10-08 |
| TWI236022B (en) | 2005-07-11 |
| JP2004047066A (en) | 2004-02-12 |
| EP1381053A3 (en) | 2006-05-24 |
| EP1381053B1 (en) | 2013-02-13 |
| KR20040007203A (en) | 2004-01-24 |
| EP1381053A2 (en) | 2004-01-14 |
| TW200414217A (en) | 2004-08-01 |
| KR100521365B1 (en) | 2005-10-12 |
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