CN1481616A - Designs of integrated circuits for high-speed signals and methods therefor in CMOS circuits - Google Patents
Designs of integrated circuits for high-speed signals and methods therefor in CMOS circuits Download PDFInfo
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- CN1481616A CN1481616A CNA028033205A CN02803320A CN1481616A CN 1481616 A CN1481616 A CN 1481616A CN A028033205 A CNA028033205 A CN A028033205A CN 02803320 A CN02803320 A CN 02803320A CN 1481616 A CN1481616 A CN 1481616A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
Abstract
Techniques for designing an electronic circuit system including multiple transistors and passive components are presented. According to one aspect of the techniques, some or all of the transistors and passive components are systematically adjusted to minimize artifacts resulting from system-level interactions among these functional building blocks. The adjustment is based on a ratio of electrically equivalent channel geometry (EECG) of each of the adjusted the transistors and passive components.
Description
Background of invention
The present invention relates to common data communication field.Specifically, the present invention relates to the universal design technology of complementary metal oxide semiconductors (CMOS) (CMOS) integrated circuit (IC) of up-to-date series.Therefore, it directly uses master control d type flip flop (MS-DFF), frequency divider, Bang Bang phase discriminator (BBDP), frequency detecting (FD), phase place and frequency detecting (PFD), voltage controlled oscillator (VCO) and the phase-locked loop (PLL) that comprises such as the optical switch IC that is used for data communication.Use the existing quite a long time of optical fiber at present in voice communications versus data communications, this is because the fabulous signal quality that its high bandwidth and its anti-electromagnetic interference are produced causes.Hope preferably can be above 1000G bps by the intrinsic light data rate of the modulated single-mode laser bundle that optical fiber transmitted.
Yet, do not reach the optical communication system on the pure meaning, in fact the attainable frequency-bandwidth limited of optical fiber telecommunications system is in the photosignal conversion and the relevant electronic hardware of necessity.Along with the use of COMS ICs, can realize low manufacturing cost, low operating power consumption, low supply voltage requires and the such advantage of current densities that can be said to be, also can realize medium speed's performance simultaneously.In order to have the maximal rate that realizes CMOSICs on the Circuits System level of better output signal quality, the U.S. Patent application of opening 09/947643 provided to similar each other topological structure of cordwood system type in the transistorized electrical equivalent raceway groove of the whole CMOS geometry (Electrically Equivalent ChannelGeometry, i.e. EECG) of the Circuits System that comprises CMOS transistor and resistance carry out the method that system regulates.Utilize this method, process when realizing IC, can realize being approximately the maximum functional clock frequency of 12GHz when the CMOS silicon wafer that uses 0.18um.The basic building block piece that the patent application in the 22 days April in 2002 of opening has in addition provided basic field-effect transistor (FET) circuit of the 2 grades of serial current mode logic doors (CML) with inductance element that are used for the optical communication electronic circuit system is can realize the driving force of more high capacity under the situation of the more high workload frequency of 50GHz at most.
Therefore, the objective of the invention is resistance and inductive circuit element are integrated into CMOS IC system, keep the technology of output signal quality preferably simultaneously to obtain higher working clock frequency.
Brief summary of the invention
The present invention relates to the high-speed cmos ICs that includes resistance and inductive circuit element and the corresponding universal design technology of up-to-date series.
One of purpose of the present invention has just provided the universal design technology of a series of ICs, and these ICs also comprise resistance and inductive circuit element except including source transistor, also keeps output signal quality preferably simultaneously.
During other purposes and aforementioned purpose can obtain in implementing the following description of the present invention and be embodied in by embodiment shown in the drawings.
Brief description of drawings
After the reference description of following preferred version, the present invention will be more readily understood, and purpose of the present invention will be clearer and more definite also.For the ease of understanding, will be described hereinbelow in detail with reference to the accompanying drawings.This:
Fig. 1 has provided the circuit structure that removes 2 type dividers with current mode conversion according to the present invention, wherein used resistance and inductive circuit element;
Fig. 2 A has provided the logic function block block diagram that removes 2 type dividers of Fig. 1;
Fig. 2 B has provided the logic function block block diagram that removes 16 type dividers that removes 2 type dividers that utilizes Fig. 1;
The form that Fig. 3 quantifies has provided the detailed data figure that 2 type divider building blocks design that removes that removes 16 type dividers to Fig. 2 B;
4 signal qualities of being exported except that 2 type dividers removing 16 type dividers that provided Fig. 2 B that Fig. 4 to Fig. 7 is continuous;
Fig. 8 has provided the MS-DFF circuit structure with current mode conversion, has wherein used resistance and inductive circuit element;
Fig. 9 A has provided the logic function block block diagram of the MS-DFF of Fig. 8;
Fig. 9 B has provided the MS-DFF that the utilizes Fig. 9 A logic function block block diagram as the typical BBPD of its logic means piece;
The form that Figure 10 quantifies has provided the detailed data figure that the MS-DFF building block to the BBDP of Fig. 9 B designs;
Figure 11 has provided the detailed data figure of the signal quality that BBPD exported of Fig. 9 B;
DETAILED DESCRIPTION OF THE PREFERRED
In a preferred embodiment of the invention, then a plurality of details are set forth for the more thorough the present invention that understands.Yet, to those skilled in the art, do not having can to implement the present invention under the situation of these specific detail yet.In other cases, well-known method, process, element and circuit are not described in detail to avoid the unnecessary elusive aspect of the present invention that makes.These describe in detail and to be embodied in directly or indirectly with the similar logical block of the operation that is coupling in the signal handling equipment on the network basically and to meet sign.These explanations and sign be that there is a practical experience this area or those of ordinary skill for their purport of work is effectively conveyed to the employed means of others skilled in the art.
Here " embodiment " who is mentioned or " embodiment " are meant that described in conjunction with the embodiments particular characteristics, structure or feature comprise at least one embodiment of the present invention.The phrase " in one embodiment " that occurs in each place of specification needn't refer to all identical embodiment, also needn't refer to the mutually disjoint independent or alternative of other embodiment.In addition, the order of functional block in the flow chart or that be used for representing the one or more embodiment of the present invention is not intrinsic any specific order of expression, neither mean that the present invention is subject to this.
Fig. 1 has provided the circuit structure that removes 2 type dividers with current mode conversion.In this embodiment, providing supply voltage AVDD is 1.8V, although also can use for example other such values of 2.5V.AGND represents " analogue ground ", and VCS provides to the bias voltage of transistor Mc1 and Mc2 grid with the flow through respective numbers of above-mentioned transistorized source electric current of adjustment.By DIVIDER1, with CLK11 with
CLK12Between the frequency partition of differential signal become Qh17 with
QhHalf of 18 differential signal.Then by output buffer 15 come buffer memory differential signal Qh17 and Qh18 with become QL13 with
QL14 differential signal is not described in detail this here to avoid making the elusive aspect of the present invention.Various active nmos pass transistors are appointed as Mc1, Mc2, M1, M2... and M16.Four pull-up resistors are appointed as R3, R4, R13 and R14.Each of two resistance R L1 and RL0 is all carried out the such simple operations of voltage level conversion, and this is for the present invention and inessential.U. S. application as 22 days April in 2002 of opening is described, additional inductance component L 3, L4, L13 and L14 and transformer T34 and T134 that its coupling coefficient is respectively K34 and K134 can be started DIVIDER1 to realize higher operating frequency provides higher load driving ability simultaneously.In addition, the U. S. application No.09/947643 that opens provided to similar each other topological structure of cordwood system type in the transistorized EECG of all CMOS carry out the method that system regulates.Therefore, the present invention want to similar other topological structures of cordwood system type in some or all active and related electrical parameters passive electric circuit element carry out adjusting on the function.Utilization has four first embodiment that remove 16 type dividers that remove 2 type dividers and is explained.
Fig. 2 A has provided the logic function block block diagram that removes 2 type dividers of Fig. 1.Fig. 2 B has provided and has utilized that Fig. 2 A's remove the logic function block block diagram that remove 16 type divider DIVIDER60s of 2 type dividers as its logic means piece.Specifically, a plurality of logic means pieces are marked as DIVIDER20, DIVIDER30, DIVIDER40 and DIVIDER60.To those skilled in the art, readily appreciate that INPUT CLOCK21 divided by 2 (2) with differential signal QL-as the DIVIDER20 output
QL=DOUT1.Equally, with INPUT CLOCK21 divided by 4 (4) with differential signal QL-as the DIVIDER30 output
QL=DOUT2.With INPUTCLOCK21 divided by 8 (8) with differential signal QL-as the DIVIDER40 output
QL=DOUT3.At last, with INPUT CLOCK21 divided by 16 (16) with differential signal QL-as the DIVIDER50 output
QL=DOUT4.
To those skilled in the art, well-known is the IC design level of handling in given wafer process, is mainly determined the conductibility of MOS transistor by following parameter:
W/L, wherein W=channel width and L=passage length.
For convenience's sake, following parameter is defined:
Electrical equivalent raceway groove geometry (EECG)=W/L.
For the relevant and adjustable electrical quantity on function of whole elements of describing the building block in the Circuits System more easily, (EECG) is defined as follows with the electrical equivalent component parameters:
Its resistance value of the EECP=of resistance; Its inductance value of the EECP=of inductance element;
And the vector that the EECP=of the transformer that inductance element is coupled is made up of the coupling coefficient between single inductance value and inductance element;
Its capacitance of the EECP=of capacity cell; And
Its EECG of the EECP=of MOS transistor.
Suppose above-mentioned definition and, in following table 1A, table 1B, table 1C and table 1D, obtain and provided these four the quantitative design detailed data figure that remove 2 type building blocks of DIVIDER20, DIVIDER30, DIVIDER40 and DIVIDER50 that remove 16 type DIVIDER60 as result of the present invention.
The EECP that has provided according to the following embodiment, the DIVIDER20 that show 1A designs to understand the project of some form:
The design of EECP:
Resistance R 3=25 ohm
Coupling coefficient between K134=L13 and L14=0.5 (no unit)
Transistor Mc1 has 260 EECG (no unit)
Transistor Mc1 has 160 EECG (no unit)
Therefore, by following provided " EECP ratio " accordingly:
25∶15∶180∶180∶0.5∶260∶160＝1.667∶1.000∶12.000∶0.033∶17.333∶10.667
State in realization in the process of EECP ratio, the EECP that selects R14 is as common divisor.Should be noted that this selection is arbitrarily, as long as the final ratio of EECP is described in the proper range of basic principle of the present invention being easy to.But, for the consistency that illustrates,, preferably keep identical selection, with the calculating of the EECP ratio that is used for other all Circuits System building blocks in case R14 selects at the particular elements piece.It should be noted that when lacking the EECP of capacity cell usually in the above-mentioned table what should know to those skilled in the art is that EECP to a plurality of capacity cells regulates being included within the present invention undoubtedly.This is to exist intrinsic capacity cell to cause owing to any the transistorized grid in the building block, source electrode and between draining, and the EECP of these capacity cells changes according to the adjusting that EECG carried out to each special transistor in considering.
Table 1E has sketched the design brief of removing 16 type DIVIDER60.DIV1 (DIVIDER20), DIV2 (DIVIDER30), DIV13 (DIVIDER40), and these four of DIV4 (DIVIDER50) remove in the 2 type building blocks, four row " ratio of EECP " are all inequality, and they are further by graphical presentation shown in Figure 3.The frequency of supposing INPUT CLOCK21 is 50GHz, and then the corresponding output waveform of DIVIDER20, DIVIDER30, DIVIDER40 and DIVIDER50 is respectively shown in Fig. 4,5,6 and 7.Except DIVIDER50 (Fig. 7) has the slight signal distortion, remaining output waveform (Fig. 4, Fig. 5 and Fig. 6) does not show tangible distortion.
Table 1E has provided the EECP design brief of DIVIDER60
EECP EECP EECP EECP
DIV1 DIV2 DIV3 DIV4R3 1.667 1.500 0.667 1.000R4 1.667 1.500 0.667 1.000R13 1.000 1.000 1.000 1.000R14 1.000 1.000 1.000 1.000L3 16.667 14.167 0.000 0.000L4 16.667 14.167 0.000 0.000L13 12.000 12.500 0.000 0.000L14 12.000 12.500 0.000 0.000K34 0.033 0.008 0.000 0.000K134 0.033 0.008 0.000 0.000MC1 17.333 4.000 0.800 0.720MC11 17.333 4.000 0.800 0.720M1 10.667 2.000 0.333 0.320M2 10.667 2.000 0.333 0.320M11 10.667 2.000 0.333 0.320M12 10.667 2.000 0.333 0.320M3 8.000 2.500 0.267 0.400M4 8.000 2.500 0.267 0.400M5 11.333 3.000 0.300 0.600M6 11.333 3.000 0.300 0.600M13 9.333 2.333 0.267 0.400M14 9.333 2.333 0.267 0.400M15 11.333 2.667 0.300 0.600M16 11.333 2.667 0.300 0.600
According to another embodiment of the invention, Fig. 8 and Fig. 9 A typical circuit structure that provided MS-DFF70 with current mode conversion with and the logic function block block diagram.In this embodiment, providing supply voltage AVDD is 1.8V, although also can use for example other such values of 2.5V.Output clock signal be CLK71 and
CLK72.Output data-signal be D73 and
D74.By output buffer 75 (not shown) for the non-essential details of the present invention come the differential signal 76a of output before the buffer memory and 77a be output into right differential signal (Qh76,
Qh77), and (QI78,
QI79).Various active NMOS are appointed as Mc1, Mc2, M1, M2... and M16.Four pull-up resistors are appointed as R3, R4, R13 and R14.With similar before, additional inductance component L 3, L4, L13 and L14 and transformer T34 and T134 that its coupling coefficient is respectively K34 and K134 can be started MS-DFF70 to realize higher operating frequency provides higher load driving simultaneously.Equally, present embodiment want to similar other topological structures of cordwood system type in whole active and EECP passive electric circuit element of the system that comprises active and passive block regulate.The Bang Bang phase detectors that utilization has three MS-DFF building blocks are explained.
Fig. 9 B has provided the MS-DFF70 that the utilizes Fig. 9 A logic function block block diagram as the typical BBPD80 of its logic means piece.Specifically, a plurality of logic means pieces are marked as MS-DFF81, MS-DFF82 and MS-DFF83.Input signal comprises VCO85 and DATA-IN86.Output signal comprise PHASE88 and
PHASE89.To those skilled in the art, it is evident that PHASE88 and
PHASE89 change according to relation leading between two input signal VCO85 and DATA-IN86 or that lag behind.For convenience's sake, the differential signal that also can be defined as follows:
ΔPHASE＝PHASE-
PHASE
With similar before, when utilizing the circuit structure identical as building block with MS-DFF70 with current mode conversion, according to the present invention, the system level design of BBPD80 especially for institute in the optical communication generally the high VCO frequency of use produced high level output signal quality.According to the mode identical with the DIVIDER60 of first embodiment, utilize following table 2A, table 2B, table 2C to illustrate that frequency is 40GHz, the DATA-IN86 data transfer rate BBDP80 for 41.66G bps VCO85: table 2A has provided the EECP design of MS-DFF81
The prosperous 4.667K34 0.5 of prosperous 4.667L14 700 skins of prosperous 4.667L13 700 skins of prosperous 4.667L4 700 skins of 150 ohm of 1.000L3 700 skins of 150 ohm of 1.000R14 of 150 ohm of 1.000R13 of 3 150 ohm of 1.000R4 of EECP element EECP unit ratio R has provided the EECP design of MS-DFF82 without the 0.467 table 2B of unit without the 0.467M16 of unit 70 without the 0.600M15 of unit 70 without the 0.600M14 of unit 90 without the 0.467M13 of unit 90 without the 0.467M6 of unit 70 without the 0.600M5 of unit 70 without the 0.600M4 of unit 90 without the 1.333M3 of unit 90 without the 1.333M12 of unit 200 without the 1.333M11 of unit 200 without the 1.333M2 of unit 200 without the 1.733M1 of unit 200 without the 1.733MC11 of unit 260 without the 0.003MC1 of unit 260 without the 0.003K134 of unit 0.5
The prosperous 3.333K34 0.5 of prosperous 3.333L14 500 skins of prosperous 3.333L13 500 skins of prosperous 3.333L4 500 skins of 150 ohm of 1.000L3 500 skins of 150 ohm of 1.000R14 of 150 ohm of 1.000R13 of 3 150 ohm of 1.000R4 of EECP element EECP unit ratio R has provided the EECP design of MS-DFF83 without the 0.600 table 2C of unit without the 0.600M16 of unit 90 without the 0.467M15 of unit 90 without the 0.467M14 of unit 70 without the 0.600M13 of unit 70 without the 0.600M6 of unit 90 without the 0.467M5 of unit 90 without the 0.467M4 of unit 70 without the 1.333M3 of unit 70 without the 1.333M12 of unit 200 without the 1.333M11 of unit 200 without the 1.333M2 of unit 200 without the 1.733M1 of unit 200 without the 1.733MC11 of unit 260 without the 0.003MC1 of unit 260 without the 0.003K134 of unit 0.5
The prosperous 0.000K34 0 of prosperous 0.000L14 0 skin of prosperous 0.000L13 0 skin of prosperous 0.000L4 0 skin of 160 ohm of 1.000L3 0 skins of 160 ohm of 1.000R14 of 160 ohm of 1.000R13 of 3 160 ohm of 1.000R4 of EECP element EECP unit ratio R without the 0.000K134 of unit 0 without the 0.000MC1 of unit 240 without the 1.500MC11 of unit 240 without the 1.500M1 of unit 100 without the 0.625M2 of unit 100 without the 0.625M11 of unit 100 without the 0.625M12 of unit 100 without the 0.625M3 of unit 120 without the 0.750M4 of unit 120 without the 0.750M5 of unit 180 without the 1.125M6 of unit 180 without the 1.125M13 of unit 120 without the 0.750M14 of unit 120 without the 0.750M15 of unit 180 without the 1.125M16 of unit 180 without unit 1.125
Same, according to one embodiment of the invention, table 2D has sketched the design brief of BBDP80.In MS-DFF81, MS-DFF82 and these three MS-DFF building blocks of MS-DFF83, three row " ratio of EECP " are all inequality, and they are further by graphical presentation shown in Figure 10.Figure 11 has provided the corresponding output waveform of Δ PHASE.In addition, except slight signal pulsation 91, output wave presents the phase-detection performance of approximate ideal.Table 2D has provided the design brief of the EECP of BBDP80
EECP EECP EECP
Ratio ratio ratio element MS-DFF81 MS-DFF82 MS-DFF83R3 1.000 1.000 1.000R4 1.000 1.000 1.000R13 1.000 1.000 1.000R14 1.000 1.000 1.000L3 4.667 3.333 0.000L4 4.667 3.333 0.000L13 4.667 3.333 0.000L14 4.667 3.333 0.000K34 0.003 0.003 0.000K134 0.003 0.003 0.000MC1 1.733 1.733 1.500MC11 1.733 1.733 1.500M1 1.333 1.333 0.625M2 1.333 1.333 0.625M11 1.333 1.333 0.625M12 1.333 1.333 0.625M3 0.600 0.467 0.750M4 0.600 0.467 0.750M5 0.467 0.600 1.125M6 0.467 0.600 1.125M13 0.600 0.467 0.750M14 0.600 0.467 0.750M15 0.467 0.600 1.125M16 0.467 0.600 1.125
Therefore, utilize the present invention, can be independent regulate under the situation that has the such interference effect of the interaction that is similar between output loading and the functional building block that is connected, also can realize high level output signal quality with the quantitative design of passive electric circuit element all of each building block of BBDP80 are active.In addition, these act on the high VCO frequency that especially shows such as the high speed optical communication that is proposed here.
As the situation of above-mentioned two embodiment, carry out system by and EECP active element passive and regulate and to realize high-quality output signal all of the single building block of an electronic circuit system.This is for particularly important such as use high clock frequency in optical communication, has well embodied the such influence of interaction between the building block of output loading and functional connection in optical communication.Invention has been described to utilize preferred embodiment.Yet, to those skilled in the art under the situation that does not break away from the spirit and scope of the present invention, be easy to preferred embodiment is made amendment and improved to be fit to other application.For example, the present invention also can be used for utilizing in the so more general electronic circuit of the transistor of field-effect transistor (FET), the Circuits System of using bipolar transistor or other types.The 3rd advantage of the present invention is Circuits System design technology of the present invention, system-level the influencing each other between various building blocks is reduced to minimum, and this it is evident that to carry out the geometry in particular that wafer process makes irrelevant with being used for relevant IC to 0.25um, 0.18um or 0.09um.In fact, along with the development of the processing of wafer geometry can be carried out the nature upgrading to technology of the present invention, because above-mentioned processing is decided rate and can be realized that corresponding high speed operation constantly carries out miniaturized along with very famous mole.Some related application comprise that data rate is 2.5G bps (OC48), 10G bps (OC192), 40G bps (OC768), the optical communication of Gigabit Ethernet, 10 Gigabit Ethernet, Bluetooth technology (2.4GHz) and WLAN, but these application are not limited thereto.At high data rate, the present invention can be used for the hardware infrastructure of multimedia messages highway.
Therefore, should be appreciated that scope of the present invention is not limited to the disclosed embodiments.On the contrary, it can cover various modifications and the similar structures based on the same operation principle.Therefore, the scope of claim is consistent with the wideest explanation to comprise above-mentioned all modifications and similar structures.
Claims (21)
1. be used for the electronic circuit system that high-speed data signal is handled, this system comprises:
A plurality of independently adjustable member pieces, wherein each building block comprises:
The active element and a plurality of CMOS (complementary metal oxide semiconductors (CMOS)) transistor that interconnect on one group of function, wherein said CMOS transistorized each have adjustable EECP value (electrical equivalent component parameters), described EECP further be defined as with transistorized channel width of each CMOS and passage length between the electrical equivalent raceway groove geometry (EECG) that equates of ratio;
Each of described active element has adjustable EECP value, and described EECP further is defined as the traditional element value of each active element; And
The vector that is called as common factor (CF) is defined as the vector ratio between described active element collection and the transistorized EECP collection of described a plurality of CMOS;
Regulate according to a mode each thus, make each of a plurality of independent adjustable member pieces not share identical vector value to realize having one group of output signal of one group of characteristics of signals of wishing to a plurality of independent adjustable member pieces.
2. according to the electronic circuit system that high speed signal is handled that is used for of claim 1, wherein the speed of signal processing is greater than 10G bps;
3. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group comprises making by the caused deterioration effect of the interaction between the two or more building blocks on system-level and is reduced to minimum.
4. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group comprises the degree that reduces the output signal pulsation.
5. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group comprises the degree that reduces the output signal shake.
6. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group comprises the degree that reduces the output signal swing.
7. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group further comprises the dynamic range that increases output signal.
8. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group further comprises the linearity that increases output signal.
9. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group further comprises the precision that increases signal output waveform.
10. according to the electronic circuit system of claim 1, the desirable characteristics of signals of wherein said output signal group further comprises the precision that increases the phase of output signal angle.
11. according to the electronic circuit system of claim 1, wherein electronic circuit system is specific to select from include trigger, divider, register, counter, timer, memory, application-specific integrated circuit (ASIC) (ASIC), ALU (ALU), embedded controller, microprocessor, numeral and analog filter, phase place and frequency detector, frequency synthesizer, multiplier, signal modulator, multiplexer, demultiplexing device, phase-locked loop, data converter and multistage amplifier one group.
12. the method that the electronic circuit system that high speed signal is handled designs, the method comprising the steps of:
A plurality of independently adjustable member pieces are provided, and wherein each building block has similar circuit topological structure, and further comprises active element and a plurality of CMOS transistor that interconnects on one group of function;
Determine the transistorized adjustable EECP value of each described CMOS (electrical equivalent component parameters), described EECP further be defined as with transistorized channel width of each CMOS and passage length between the electrical equivalent raceway groove geometry (EECG) that equates of ratio;
Determine the adjustable EECP value of each described active element, described EECP further is defined as the traditional element value of each active element;
Distribute and to be called as common factor CF) vector, this vector is defined as the vector ratio between described active element collection and the transistorized EECP collection of described a plurality of CMOS; And
Regulate according to a mode each, make each of a plurality of independent adjustable member pieces not share identical vector to realize having one group of output signal of one group of desirable characteristics of signals to a plurality of independent adjustable member pieces.
13. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group comprises making by the caused deterioration effect of the interaction between the two or more building blocks on system-level and is reduced to minimum.
14. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group comprises the degree that reduces the output signal pulsation.
15. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group comprises the degree that reduces the output signal shake.
16. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group comprises the degree that reduces the output signal swing.
17. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group further comprises the dynamic range that increases output signal.
18. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group further comprises the linearity that increases output signal.
19. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group further comprises the precision that increases signal output waveform.
20. according to the method that electronic circuit system is designed of being used for of claim 12, the desirable characteristics of signals of wherein said output signal group further comprises the precision that increases the phase of output signal angle.
21. according to the method that electronic circuit system is designed of being used for of claim 12, wherein electronic circuit system is specific to select from include trigger, divider, register, counter, timer, memory, application-specific integrated circuit (ASIC) (ASIC), ALU (ALU), embedded controller, microprocessor, numeral and analog filter, phase place and frequency detector, frequency synthesizer, multiplier, signal modulator, multiplexer, demultiplexing device, phase-locked loop, data converter and multistage amplifier one group.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/947,643 | 2001-09-05 | ||
| US09/947,643 US6433595B1 (en) | 2001-09-05 | 2001-09-05 | Method of system circuit design and circuitry for high speed data communication |
| US10/137,988 US6559693B2 (en) | 2001-09-05 | 2002-05-02 | Integrated circuit designs for high speed signal processing |
| US10/137,988 | 2002-05-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1481616A true CN1481616A (en) | 2004-03-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA028033205A Pending CN1481616A (en) | 2001-09-05 | 2002-06-26 | Designs of integrated circuits for high-speed signals and methods therefor in CMOS circuits |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1449301A1 (en) |
| CN (1) | CN1481616A (en) |
| TW (1) | TW567670B (en) |
| WO (1) | WO2003023965A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359808C (en) * | 2004-04-21 | 2008-01-02 | 厦门优迅高速芯片有限公司 | High-speed current mode logic circuit |
| CN103107802A (en) * | 2011-11-10 | 2013-05-15 | 台湾积体电路制造股份有限公司 | Input/output circuit with inductor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4289979A (en) * | 1978-08-28 | 1981-09-15 | Burroughs Corporation | Transistorized master slave flip-flop having threshold offsets generated by circuit size variations |
| US4806796A (en) * | 1988-03-28 | 1989-02-21 | Motorola, Inc. | Active load for emitter coupled logic gate |
| US5196805A (en) * | 1992-01-31 | 1993-03-23 | Motorola, Inc. | Distributed differential amplifier arrangement |
| US5945847A (en) * | 1997-05-20 | 1999-08-31 | Lucent Technologies | Distributed amplifier logic designs |
-
2002
- 2002-06-26 WO PCT/US2002/020872 patent/WO2003023965A2/en not_active Application Discontinuation
- 2002-06-26 CN CNA028033205A patent/CN1481616A/en active Pending
- 2002-06-26 EP EP02746801A patent/EP1449301A1/en not_active Withdrawn
- 2002-08-07 TW TW91117822A patent/TW567670B/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359808C (en) * | 2004-04-21 | 2008-01-02 | 厦门优迅高速芯片有限公司 | High-speed current mode logic circuit |
| CN103107802A (en) * | 2011-11-10 | 2013-05-15 | 台湾积体电路制造股份有限公司 | Input/output circuit with inductor |
| CN103107802B (en) * | 2011-11-10 | 2015-10-28 | 台湾积体电路制造股份有限公司 | There is the input/output circuitry of inductor |
Also Published As
| Publication number | Publication date |
|---|---|
| TW567670B (en) | 2003-12-21 |
| EP1449301A1 (en) | 2004-08-25 |
| WO2003023965A2 (en) | 2003-03-20 |
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