TW567670B - Integrated circuit designs for high speed data - Google Patents

Abstract

Techniques for designing an electronic circuit system including multiple transistors and passive components are presented. According to one aspect of the techniques, some or all of the transistors and passive components are systematically adjusted to minimize artifacts resulting from system-level interactions among these functional building blocks. The adjustment is based on a ratio of electrically equivalent channel geometry (EECG) of each of the adjusted the transistors and passive components.

Description

567670 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention () Field of Invention i This invention is about the field of data communication. More specifically, the present invention relates to a generic design method for a new group of complementary metal-oxide-semiconductor (CMOS) integrated circuits (1C). Therefore, the direct response of this method includes various subsystems and system functions, such as master-slave D-type flip-flop (MS-DFF), frequency divider, bang phase detector (BBPD), frequency detection (FD), phase and frequency detection (PFD), voltage controlled oscillator (VC0), and phase-locked loop (PLL) in optical switches used for data communication. Background of the Invention To date, due to the high frequency bandwidth and excellent signal quality of optical fibers, which protect them from electromagnetic interference, optical fibers have been used for voice and data communications. The inherent optical data rate of a single-mode laser beam modulated by an optical fiber can easily exceed 1000 Gbits / second. However, due to the lack of a true optical communication system, the achievable optical communication system bandwidth has been limited due to the need for signal conversion in the optical and electronic range and related electronic hardware. The use of CMOS integrated circuits' can achieve advantages including low manufacturing costs, low operating power consumption, low supply voltage requirements, and very good circuit density, but its Lida achieves moderate rate performance. In order to fully realize the rate performance of CMOS integrated circuits and good output signal quality at the system level, US Patent No. 6,433,595 teaches a systematic adjustment of the electronic equivalent channel geometry (EECG) of some or all individual CMOS transistors. Method 'where CMOS transistors are similar in other aspects of topological construction. Page 4 This paper size applies Chinese National Standard (CNS) A4 specification (210x297) ............. Ψ ........, 玎 ......... 0 (Please read the precautions on the back before filling out this page) 567670 Printed block circle process for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Clock frequency teaching: The ultra-high level of the string transistor is good in the inductor and other components, and the invention description (. Using this method, when the integrated circuit is implemented with 0.18 micron (gm) CMOS silicon crystal, Maximum operating rate of 12 GHz. In addition, U.S. Patent Application No. 10/1 36,1 65 is the incorporation of 7G inductors into optical communication. The dual-connected polarization of electronic circuit systems used in telecommunications and current mode logic (CML) Based on the basic building blocks of field-effect (FET) circuits, In order to achieve a higher load driving efficiency at a frequency of up to 500 Ηζ. In the embodiment, a circuit may include other components, such as resistors and components. Therefore, in a 1C system, a method for designing it is needed. Technology to achieve two operating clock frequencies while maintaining the quality of the output signal. Purpose and summary of the invention: The present invention is a new high-speed CMOS integrated circuit directed at a low impedance and inductive circuit element. Groups, conversions, and corresponding generic design methods. One of the objects of the present invention is to provide a generic design method for k for an integrated circuit group, except for the active type. In addition to the electric sun and the sun, it also includes impedance and inductive circuit elements, which can maintain good output signal quality at the same time. · The purpose of the present invention and the above-mentioned object can be achieved by implementing the invention content described below. Example 0 indicated by the attached drawings: Brief description of the drawings: Page 5 .............. Lu: 6 Please read the notes on the back before filling in this tribute)-Order ·

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Can be understood more: = 34 'Scope of patent application and attached drawings, when. Figure 1 is based on the present invention-processing example shows a one-minute divider with current mode switching power month b ^ ^ ^ Circuit structure, which uses impedance and inductive circuit elements; Figure 2A shows the 1st 2B _ ^ bis / knife divider logic function block diagram; Figure 2B shows the use of one of the flute diagram for division The block diagram of the logic function of the divider of the 16th divider of the frequency divider; Figure 3 is a detailed illustration of the quantitative design of the two-division construction block of the divider of the 16th divider of Figure 2B; Figures 4 to " Describe the output signal quality of one of the two divider dividers of the sixteen divider divider shown in Figure 2B in turn. Figure 8 shows the circuit architecture without the current mode switching function. Two circuits are used: impedance and induction. Components; Figure 9A is a block diagram of the logic function of the heart shown in Figure 8; Figure 9B is a logic function block diagram of a typical bang phase detector (BBpD), which is based on MS shown in Figure 9A -DFF is its logical building block; Figure 10 is a detailed illustration of the MS-DFF construction of BBPD in Figure 9B Quantization block design; and FIG. 11 lines of output signal quality BBPD shown in FIG 9B depict first. Explanation of drawing number comparison: page 6 This paper size is applicable to China National Standard (CNS) A4 specification (2i0x297mm) (Please read the precautions on the back before filling this page)%. Staff of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 567670 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 A7 ---- ^ B7 All instructions () 1 Frequency divider 1 BU 12 Clock signal 1 3, 1 4 Output data signal 15 Buffer memory 17 signal Qh 18 signal QJl 20 frequency divider 21 input clock 30 frequency divider 50 frequency divider 60 frequency divider 70 D-type flip-flop 71, 72 input clock signal 73 '74 input data signal 75 round buffer Memory 76 '77 outputs differential signals 76a, 77a outputs differential signals before 78, 79 outputs differential signals 80 Bang phase detectors 81, 82, 83 D-type flip-flops 85 VCO input signals 86 data input signals 88 output signal PHASE 91 signal ripple

¾) Public top | Institute No. 1: Regulation 4 A S) N C Tendering State Appropriate Moderate Rule Paper 567670 A7

Those skilled in the art. Here, the "one embodiment" or "embodiment" refers to the technical characteristics interpolated in the example of the pointer, the stove broadcast seven, an implementation {please read the precautions on the back before filling this page) Construction or characteristics are incorporated into the present invention. The appearances of "^ to in embodiments" appearing in different places in this specification do not necessarily refer to the same embodiment, nor do they necessarily mean different embodiments that are mutually incompatible. In addition, the order of the blocks representing the process flowchart of the second or other embodiment of the present invention is not intended to imply any meaning: definite: order 'It also does not imply the limitations of the present invention. Figure 1 shows the circuit structure with the current mode switching function. 1. ^ Knife Divider Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. To facilitate the description of the present invention, the diagram is based on a circuit. In the embodiment, the supply voltage AVDD is 1.8 volts, but other voltages can also be used, for example, 2.5 volts ^ AGND is labeled as "analog ground", VC S is the gate applied to the transistors Mc 丨 and Mc2 The bias of the poles is used to establish the amount of source current corresponding to the gates. When passing through divider 1, the frequency of the differential signal between CLK 1 1 and CLK 12 is divided into half, and it becomes the differential signal between Qh 1 7 and Q_h 1 8. The differential signal between Qh 1 7 and 〇11l 18 is then temporarily stored through the wheel-out buffer memory 15 and becomes the differential signal between QL 13 and OL14; in order to avoid obscuring the argument of the present invention, the buffer Reservoir 15 is not shown in detail. Each active transistor (such as NMOS) is labeled as Mcl, Mc2, Ml, M2 ... and M16. The four boost resistors are labeled R3, R4, R13, and R14. Both resistors RL1 and RL10 perform a simple voltage magnitude conversion function. As described in US Patent Application No. 10 / 136,165, the added inductance components L3, L4, page 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 567670 5. Description of the invention () L13 and L14, together with the formed transformers T34 and T134 with coefficient coefficients K34 and K134, can reduce w, soil, η 砗 m, except for frequency 1 It achieves a higher operating frequency, and at the same time provides a higher load driving efficiency b. In addition, U.S. Patent Application No. 09 / 947,643 teaches a method to systematically adjust the electronic equivalent pass-through dual-channel geometry (EECG) of all individual CMOS transistors, in which each CMOS transistor is better in other ways. Topologically build blocks of similar circuit systems. Therefore, the present invention proposes to adjust the electrical parameters of each of the active and broken circuit elements of each or all of the functionally related 'components except for topologically similar building blocks. A first embodiment of a sixteen-point circuit system with four 28 * one-size building blocks will now be described. Figure 2A shows the first! Figure 2 shows the logic function block diagram of the divide-by-2 divider. Figure 2B is a block diagram of the logic function of a sixteen-divider divider 60, which uses the two-divider divider shown in Figure 2A as its logical building block. Specifically, &, the repeated logical building blocks are labeled as frequency divider 20, frequency divider 30, frequency divider 40, and frequency divider 50. Those skilled in the art can easily know that the input clock (INPUT CL0CK) 21 will be divided into two (2) and become a differential signal ql at the output of the divider 20 = DOUT1.

Similarly, INPUT CLOCK21 will be divided by four (4) at the output of divider 30 to become a differential signal ql = DOUT2. INPUT

The frequency of CLOCK 21 will be divided by eight at the output of the divider 4 to become a differential signal QL-= DOUT3. Finally, the frequency of INPUT CLOCK 21 will be sixteen minutes (16) at the wheel source of the divider 50 and become a differential signal 01-QI = DOTTT4 〇 It is well known in this technical field that the 1C design for a given wafer process Page 9 This paper applies the Chinese National Standard (CNS) A4 Regulation (210X297 mm) .............. Soil: (Please read the precautions on the back before filling this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 670

2. Description of the invention (In terms of capacitance of a ° -transistor is mainly determined by the following parameters: W / L 'where W = channel width and L = channel length. For simplicity, the following parameters are defined. Electronic equivalent Channel Geometry (EECG) = W / L. In order to facilitate the description of a building block containing a circuit system, some or% ± * 4 All 7L components are functionally related and adjustable electronic parameters, hereby jyg The electronic equivalent component parameters (EECP) are as follows: EECP of the resistor = resistance value of the resistor; EECP of the inductive component = = inductance value of the inductive component; EECP of the transformer formed by the light-weight inductive component = includes individual inductance values The vector of the coupling coefficient between the inductor and the inductive element; the EECP of the capacitive element == the inductance value of the capacitive element; and the EECP of the transistor = the EECG of the MOS transistor. Given the above definition, according to the results obtained by the present invention, one can obtain The four dichotomy blocks of frequency divider 20, frequency divider 30, frequency divider 40 and frequency divider 40 are shown in the following Table 1A, Table 1B, Table 1 C and Table 1D: (Please read the note on the back first (Please fill in this page again) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives Table 1 A EECP Design of Frequency Divider 20 EECP Components EECP Unit Ratio R3 25 Ohm 1.667 R4 25 Ohm 1.667 R13 15 Ohm 1.000 R14 15 Ohm 1.000 L3 250 Pico Henry 16.667 Page 10 Paper Size Applicable to China National Standard (CNS) A4 Regulations (210X 297 Gongchu) 567670 A7 B7 V. Description of Invention () Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs L4 250 Pico Henry 16.667 L13 180 Pico Henry 12.000 L14 180 Pico Henry 12.000 K34 0.5 dimensionless 0.033 K134 0.5 dimensionless 0.033 MCI 260 dimensionless 17.3 3.3 MCI 1 260 dimensionless 17.333 Ml 160 dimensionless 10.667 M2 160 dimensionless 10.667 Mil 160 dimensionless 10.667 M12 160 dimensionless 10.667 M3 120 dimensionless 8.000 M4 120 dimensionless 8.000 M5 170 dimensionless 11.333 M6 170 dimensionless 11.333 M13 140 dimensionless 9.333 M14 140 dimensionless 9.333 M15 170 dimensionless 11.333 M16 170 dimensionless 11.333 Table EECP Design EECP Ratio of IB Divider 3 0_Page 11 This paper size applies to China National Standard (CNS) A4 specifications ( 210X297mm) .............. Soil: (Please read the notes on the back before filling out this page) Order · 567670 A7 B7 V. Description of Invention () Intellectual Property Bureau of the Ministry of Economic Affairs Industrial and consumer cooperative printed components EECP unit R3 90 ohms 1.500 R4 90 ohms 1.500 R13 60 ohms 1.000 R14 60 ohms 1.000 L3 850 pico Henry 14.167 L4 850 pico Henry 14.167 L13 750 pico Henry 12.500 L14 750 pico Henry 12.500 K34 0.5 dimensionless 0.008 K134 0.5 dimensionless 0.008 MCI 240 dimensionless 4.000 MCI 1 240 dimensionless 4.000 Ml 120 dimensionless 2.000 M2 120 dimensionless 2.000 Mil 120 dimensionless 2.000 M12 120 dimensionless 2.000 M3 150 dimensionless 2.500 M4 150 Dimensionless 2.500 M5 180 Dimensionless 3.000 M6 180 Dimensionless 3.000 M13 140 Dimensionless 2.333 M14 140 Dimensionless 2.333 Top 1 --------........ ^ ......... (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 567670 A7 B7 V. Description of invention () M15 160 Dimensionless 2, .667 M16 160 Dimensionless 2, .667 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative, 1C EECP design of frequency divider 40 EECP component EECP unit ratio R3 200 ohm 0.667 R4 200 ohm 0.667 R13 300 ohm 1.000 R14 300 ohm 1.000 L3 0 Pico Henry 0.000 L4 0 Pico Henry 0.000 L13 0 pico Henry 0.000 L14 0 pico Henry 0.000 K34 0 dimensionless 0.000 K134 0 dimensionless 0.000 MCI 240 dimensionless 0.800 MCI 1 240 dimensionless 0.800 Ml 100 dimensionless 0.333 M2 100 dimensionless 0.333 Mil 100 Dimensionless 0.333 M12 100 Dimensionless 0.333 Page 13 -------- ·: ":% -'........ Order ......... (Please first Read the notes on the reverse side and fill in this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 567670 A7 B7 V. Description of the invention () Printed by the Consumer Property Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs M3 80 None Factor 0.267 M4 80 Factorless 0.267 M5 90 Factorless 0.300 M6 90 Factorless 0.300 M13 80 Factorless 0.267 M14 80 Factorless 0.267 M15 90 Factorless 0.300 M16 90 Factorless 0.300 Table 1D Frequency Divider EECP design of 5 EECP EECP unit ratio R3 250 Ohm 1.000 R4 250 Ohm 1.000 R13 250 Ohm 1.000 R14 250 Ohm 1.000 L3 0 Pico Henry 0.000 L4 0 Pico Henry 0.000 L13 0 Pico Henry 0.000 L14 0 Pico Henry 0.000 K34 0 Dimensionless 0.000 K134 0 No reason Times 0.000 MCI 180 Dimensionless 0.720 --------....... Order ......... # (Please read the notes on the back before filling this page) Section 14 The paper size of this page applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 567670 A7 B7 V. Description of the invention () MCI 1 180 dimensionless 0.720 Ml 80 dimensionless 0.320 M2 80 dimensionless 0.320 Mil 80 None Factor 0.320 M12 80 Factorless 0.320 M3 100 Factorless 0.400 M4 100 Factorless 0.400 M5 150 Factorless 0.600 M6 150 Factorless 0.600 M13 100 Factorless 0.400 M14 100 Factorless 0.400 M15 150 Factorless 0.600 M16 150 Dimensionless 0.600 (Please read the notes on the back before filling in this page) Printed by Shelley Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economy 20 EECP design, Provide some listed items to help clarify: Design of EECP: Resistor R3 = 25 ohm · Resistor R14 = 15 ohm Inductive element L13 = 180 pico Henry (10-12 Henry) Inductive element L14 = 180 pico Henry (10- (12 Henry) K134 = Coupling coefficient between L13 and L14 = 0.5 (dimensionless) EECG of transistor Mcl is 260 (dimensionless) Page 15 This paper applies Chinese National Standard (CNS) A4 (210X297) (%) 5. Description of the invention () The EECG of the transistor M1 is 160 (dimensionless). Therefore, the corresponding "EECP ratio" is as follows: 25: 15: 18〇: 18〇: 0.5: 260: 160 1.667.1 .GGG ·· 12.GGG: 12.GG (): G.G33: 1 7.3 33: 1〇 · 667 When the above EECP ratio is served, it has been selected

Used as a common frequency divider. It is worth mentioning e ^ EEC. To the last m, the choice is arbitrary, and the CP ratio falls within the applicable range. Naneng can simply use the principle of the present invention. . It should be noted that although the EEcp of the capacitive element is not listed in the above I, if you are familiar with this term, you can know that each of the different capacitive elements < coffee? Tune in η This is due to the inner 70 pieces of the gate, source, and non-electrode and any of the main body of Zhao in the building block, as well as this ::: 元: ... will follow the special L: :: and-both have two V: r a divider 2 °, 3 °, 4 °, m ~ used for a frequency divider (such as 2.) a group ratio 疋 is different from that used for another frequency divider The _group ratio $ money rate used here. For example, in an array Shixuan 糸 0_common factor (CF), it is defined as or vector ratio (set all ratios in-rank). Accordingly, according to the feature of the present invention, the formation of CF for one of a frequency divider (such as 20) is different from that of a CFe table for another-frequency divider (such as 60). IE is implemented according to the present invention. Example, an overview of the design of eight μ60. In DIV1 (frequency divider 20), DIV: (frequency divider V: wide ΓΓΓ frequency divider 4G) and job (frequency divider called four: divide the block ... the four lines of "spoiler p ratio" are all different, which Figures for further steps are shown on page 16 567670 A7 B7 V. Description of the invention () (Please read the note on the back 1 before filling out this page) Figure 3. INPUT CLOCK 21 with a frequency of 50 GHz, divider 20. The output waveforms corresponding to frequency divider 30, frequency divider 40, and frequency divider 50 are shown in Figure 4, Figure 5, Figure 6, and Figure 7, respectively. Except for frequency divider 50 (Figure 7 ) The output waveform is slightly distorted except for the winter signal, and the rest of the output waveforms (Figure 4, Figure 5, and Figure 6) have no visible distortion. Table 1E Overview of the EECP design of the divider 60 EECP EECP EECP EECP ratio Ratio Ratio Ratio Element DIV1 DIV2 DIV3 DIV4 R3 1.667 1.500 0.667 1.000 R4 1.667 1.500 0.667 1.000 R13 1.000 1.000 1.000 1.000 1.000 R14 1.000 1.000 1.000 1.000 L3 16.667 14.167 0.000 0.000 L4 16.667 14.167 0.000 0.000 L13 12.000 12.500 0.000 0.000 L14 12.000 12.500 0.001 0.008 0.000 0.000 K134 0.033 0.008 0.000 0.000 MCI 17.333 4.000 0.800 0.720 MCI 1 17.333 4.000 0.800 0.720 Ml 10.667 2.000 0.333 0.3 20 Printed by Shelley Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs, page 17 This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) 567670 A7 -----B7 V. Description of the invention () M2 10.667 2.000 0.333 0.320 Mil 10.667 2.000 0.333 0.320 M12 10.667 2.000 • 0.333 0.320 M3 8.000 2.500 0.267 0.400 M4 8.000 2.500 0.267 0.400 M5 11.333 3.000 0.300 0.600 M6 11.333 3.000 0.300 0.600 Ml 3 9.333 2.333 0.267 0.400 M14 9.333 2.333 0.267 0.400 M15 11.333 2.667 0.300 0.600 M16 11.333 2.667 0.300 0.600 According to another embodiment of the present invention, FIGS. 8 and 9A show D-type forward and reverse with a current mode switching function Device (MS-DFF) 70 typical f-channel architecture and its related logic function block diagram. In this embodiment, the supply voltage AVDD is 1.8 volts, but other voltages such as 2, .5 volts may be used. The input clock signals are CLK 71 and CLK 72. The input data signals are D 73 and D 74. The pre-output differential signals 76a and 77a are then temporarily stored through the output buffer memory 75 to become output differential signal pairs (Qh 76, QJl 77) and (QI 78, OL 79). Different active NMOS transistors are labeled Mcl, Mc2, Ml, M2 ... and M16. The four boost resistors are labeled R3, R4, R1 3, and R1 4. As before, the added inductive elements L3, L4, L13 and L14, together with the transformers T34 and T134 with their respective coupling coefficients K34 and K134, can (please read the precautions on the back before filling this page). Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Consumer Cooperative ___ The first paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm), allowing MS-DFF 70 i * 5, 丨 # > to achieve two operating frequencies and load-driven performance . Same as -L ^, b 獒, the same, this embodiment proposes the circuit system construction F M ^ ⑬ β I except for topologically similar structure & part or all of the active and passive circuit components EECP. An example of a circuit with three MS_DFF building blocks is also described here. Figure 9B is a logical functional block diagram of a typical BbpD 80. The BBPD is based on $ Ms_dff 70 in Figure 9A. z Specifically, duplicate logical building blocks are labeled MS-DFF 8ι, MS-DFF 82, and MS_DFF 83. The input signals include vC85 and DATA-IN 86. Output signals include pHASE88 and PHASF RQ. Those skilled in the art can easily know that the logic state of PHASe 88 and PHASF RQ will change with the leading or trailing phase relationship between the two input signals of VCO 85 and DATA-IN 86. For simplicity, the following differential signals are also defined: △ PHASE = PHASE-PHASE. As before, although using the same MS-DFF 70 circuit architecture with current mode switching function, BBPD 80 system level design, by virtue of the advantages of the present invention Generate high-quality output signals, especially high VCO frequencies commonly used in optical communications. As in the first example of the frequency divider · 60, when the VCO 85 frequency = 40 GHz and the data rate of DATA-IN 86 = 41.66 Gbit / sec, the results for BBPD 80 are as follows: 2A, Table 2B, and Table 2C: Page 19 of this book. The size of the week. China: 3 companies # 准 (CNS) A qiange: ^ 670670 • Λ / Β7 V. Instructions () Wisdom of the Ministry of Economic Affairs FECP Employee Consumer Cooperative Printed Form 2A MS-DFF 81 EECP Design Element EECP Unit EECP R3 150 Ohm 1.000 R4 150 Ohm 1.000 R13 150 Ohm 1.000 R14 150 Ohm 1.000 L3 700 Pico Henry 4.667 L4 700 Pico Henry 4.667 L13 700 Pico Henry 4.667 L14 700 Pico Henry 4.667 Κ34 0.5 dimensionless 0.003 Κ134 0.5 dimensionless 0.003 MCI 260 dimensionless 1.733 MCI 1 260 dimensionless 1.733 Ml 200 dimensionless 1.333 M2 200 dimensionless 1.333 Ml 1 200 dimensionless 1.333 M12 200 dimensionless 1.333 M3 90 dimensionless 0.600 M4 90 dimensionless 0.600 M5 70 dimensionless 0.467 M6 70 dimensionless 0.467 Page 20 ΛΛΛ. Ν ^ -Τ55Λ «* α3β · at- / ** j ^ r- ^. v · _ r 2 -m. 上-· Produce TVTT " »^^ ·· Shoulder--r—.. Ϋχ ^ αοΛίΛ 只 · Only a ruler. ¾¾ 3 T country and country (3'3) A4 specifications (2U:; .., (Please read the note on the back first) Matters are refilled on this page)

567670, 37 Fifth Ministry of Economic Affairs, Intellectual Property Bureau employee consumer cooperative prints and issues instructions: M13 9 0 dimensionless 0.600 M14 90 dimensionless 0.600 M15 70 dimensionless 0.467 M16 70 dimensionless 0.467 Table 2B MS-DFF 82 of EECP design element EE CP unit EECP ratio R3 150 Ohm 1.000 R4 150 Ohm 1.000 R13 150 Ohm 1.000 R14 150 Ohm 1.000 L3 500 Pico Henry 3.333 L4 500 Pico Henry 3.333 L13 500 Pico Henry 3.333 L14 500 Pico Henry 3.333 K34 0.5 Dimensionless 0.003 K134 0.5 Dimensionless 0.003 MCI 260 Dimensionless 1.733 MCI 1 260 Dimensionless 1.733 Ml 200 Dimensionless 1.333 M2 200 Dimensionless 1.333 Mil 200 Dimensionless 1.333 Page 21 567670 A7 B7 V. Description of the invention () Economy Printed by the Shell and Consumer Cooperative of the Ministry of Intellectual Property Bureau M12 200 dimensionless 1.333 M3 70 dimensionless 0.467 M4 70 dimensionless 0.467 M5 90 dimensionless 0.600 M6 90 dimensionless 0.600 M13 70 dimensionless 0.467 M14 70 dimensionless 0.467 Ml 5 90 dimensionless 0.600 M16 90 dimensionless 0.600 Table 2C EECP design elements EECP MS-DFF 83 EECP unit EECP ratio R3 160 Ohm 1.000 R4 160 Ohm 1.000 R13 160 Ohm 1.000 R14 160 Ohm 1.000 L3 0 Pico Henry 0.000 L4 0 Pico Henry 0.000 L13 0 Pico Henry 0.000 L14 0 Pico Henry 0.000 K34 0 Dimensionless 0.000 K134 0 Dimensionless 0.000 ---- ----- V7 丨 丨 丨% -......... Order ........- by (Please read the precautions on the back before filling this page) Page 22 Applicable to China National Standard (CNS) A4 specification (210X297 mm) 567670 A7 B7 V. Description of the invention () MCI 240 dimensionless 1.500 MCI 1 240 dimensionless 1.500 Ml 100 dimensionless 0. 625 M2 100 dimensionless 0 625 Mil 100 dimensionless 0., 625 M12 100 dimensionless 0 ·, 625 M3 120 dimensionless 0 ·, 750 M4 120 dimensionless 0, 750 M5 180 dimensionless 1, .125 M6 180 dimensionless Times 1, .125 M13 120 Dimensionless 0 .750 M14 120 Dimensionless 0 • 750 M15 180 Dimensionless 1 • 125 M16 180 Dimensionless 1 • 125 (Please read the notes on the back before filling out this page) Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Similarly, Table 2D summarizes the implementation according to one of the inventions. 80 of the BBPD design overview. It should be noted that among the three MS-DFF building blocks such as MS-DFF 81, MS-DFF82, and MS-DFF83, the three rows of "EECP ratios" are all different, which is further illustrated in Figure 10. △ PHASE's corresponding output waveform is shown in Figure 11. Similarly, with the exception of some signal ripples 9 1, the output waveform exhibits perfect phase detection characteristics. Page 23 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 567670 A7 B7 V. Description of the invention () Table 2D Overview of the EECP design of BBPD 80 EECP ratio printed by the Shell Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs EECP ratio EECP ratio element MS-DFF81 MS-DFF82 MS-DFF83 R3 1.000 1.000 1.000 R4 1.000 1.000 1.000 R13 1.000 1.000 1.000 R14 1.000 1.000 1.000 L3 4.667 3.333 0.000 L4 4.667 3.333 0.000 L13 4.667 3.333 0.000 L14 4.667 3.333 0.000 K34 0.003 0.003 0.000 K134 0.003 0.003 0.000 MCI 1.733 1.733 1.500 MCI 1 1.733 1.733 1.500 Ml 1.333 1.333 0.625 M2 1.333 1.333 0.625 Mil 1.333 1.333 0.625 M12 1.333 1.333 0.625 M3 0.600 0.467 0.750 M4 0.600 0.467 0.750 M5 0.467 0.600 1.125 (Please read the note on the back first 1 (Fill in this page again) Page 24 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 567670, invention description (M6 Ml 3 M14 Ml 5 Ml 6 0.467 0.600 0.600 0.467 0.467 0.600 0.467 0.467 0.600 0.600 1.125 0.750 0.750 1.125 1.125 Shellfish Consumption of Intellectual Property Bureau, Ministry of Economic Affairs The printing company printed so 'Using the present invention, the quantitative design of the active 1 passive circuit of each building block of BBPD 80 is individually adjusted so as to output load and interaction between building blocks such as functional connections In the case of the adverse effect of the high-quality output signal can be obtained. In addition, these effects will be more obvious at high VC0 frequency, such as the high vco frequency used in high-speed optical communications described here. As described above Two examples. By systematically adjusting the EECP of all passive and active components in individual building blocks of an electronic circuit system, we can obtain high-quality output signals. This effect is particularly important for applications with high clock frequencies; for example In optical communications, these effects are even more pronounced in the output load and interactions between functionally connected building blocks. The invention has been described with reference to preferred embodiments. However, for those skilled in the art, the preferred embodiments can be easily adjusted, modified, and adapted to other applications without departing from the spirit and scope of the present invention. For example, the invention can be applied to more generalized electronic circuits using field effect transistors (FETs), bipolar transistors, or other forms of transistors. The description provided by the present invention is familiar to those skilled in the relevant arts who can understand that the circuit design method of the present invention and the geometry of the specific wafer process (please read the note on the back 1 before filling this page) Page 25 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 567670 A7 B7 V. Description of the invention () The structure is completely irrelevant, regardless of whether the relevant integrated circuit manufacturing system uses 0.25 micron, 0. 18 micron or 0.09 micron process are all The method of the invention can be applied. The method of the present invention can be continuously scaled down and expanded naturally according to the well-known Moore's Law (M ο 〇re's L aw) as the geometric structure of the wafer process is obtained, and a relatively high operating speed "some related Applications include: optical communication at data rates of 2.5 Gbit / sec (OC48), 10 Gbit / sec (OC192) and 40 Gbit / sec (OC768), Gigabit Ethernet, 10 Gigabit Ethernet, Bluetooth (2.4 GHz) technology and wireless local area network (LAN) (5.2 GHz), etc., but not limited to the above. According to the present invention, a hardware base frame for high-speed data processing is possible. Therefore, it should be understood that the present invention is not limited to the disclosed embodiments. Conversely, the present invention actually covers various changes and similar configurations based on the same operating principles. Therefore, the scope of patent application should be interpreted in the broadest sense to cover all such changes and similar configurations. (Please read the precautions on the back before filling out this page) Order Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Page 6 2 This paper size applies to China National Standard (CNS) A4 (210x297)

Claims (1)

567670 (Please read the notes on the back of -M before filling in this page) -.- nr ^ Six T 廿 said that the block has a similar circuit topology, the circuit topology also includes: /, 70 passive components and several metal oxides Functional interconnection set of CMOS transistors, in which each C_transistor is provided with an adjustable value of the electronic equivalent element parameter (EECP). The Ε (: ρ is further defined as an electronic equivalent Channel geometry (EECG), which is equal to the ratio of channel width to channel length of individual CMOS transistors; each of these passive components is provided with an adjustable value of EECP, and each EECP is further defined as one of the individual passive components. The component value; and a vector called a common factor (CF), which is defined as the vector ratio between the set of passive components and the EECP set of the CMOS transistors; and each of the four construction regions that are individually adjusted The adjustment method of the block is such that the CFs of the individual building blocks that are individually adjusted will not share the same vector value, so as to obtain a set of output signals with the required signal characteristics. Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. apply for patent The electronic circuit system described in the first item of the scope, wherein the signal processing rate exceeds 10 Gbit / sec. 3 · The electronic circuit system described in the first item of the patent application scope, wherein the required signal characteristics of the above output signals include a reduction in the system level Adverse effects caused by the interaction of two or more building blocks above. Page 27 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 567670 A8 B8 C8 D8 6. Scope of patent application 4. The electronic circuit system as described in the scope of application for patent M, wherein the required signal characteristics of the above-mentioned output signals include a reduction in the degree of signal continuity. 5. The electronic circuit system as described in the scope of application for patents above i. The required signal characteristics of the signal include reducing the degree of jitter of the wheel-out signal. 0. The electronic circuit system described in the scope of application for patent application 帛 i. The required signal characteristics of the above output signal also include the reduction of the degree of unwanted output signal oscillation. 7. The electronic circuit system described in item 1 of the scope of patent application, wherein the required signal characteristics of the above output signals further include Increase the dynamic range of the output signal. 8. The electronic circuit system as described in item 1 of the scope of patent application, in which the required signal characteristics of the output signal printed by the above-mentioned Intellectual Property Office of the Intellectual Property Bureau, Shellfisher Consumer Cooperative, include increasing the linearity of the output signal. Features. 9. The electronic circuit system as described in item 1 of the scope of patent application, wherein the required signal characteristics of the above output signals further include an increase in the accuracy of the output signal waveform. ___ page 28 The national standard of this paper is used weekly. (CNS) A4 specification (210 X 297 public Chu) " '" " — 567670 A8B8C8D8 6. Application for patent scope 10 · Electronic X .. ~ ~ system as described in the scope of patent application 专利 i, where the above output The required signal characteristics of the signal also include increased accuracy. H-position angles 11. The electronic circuit system described in the patent application, wherein the above electronic circuit system is specially selected from a group consisting of a flip-flop, a frequency divider, a register and a counter , Timer 'memory, special application integrated circuits (ASICs), arithmetic and logic units (alu), embedded controllers, microprocessors, digital and analog filters, phase frequency detectors, frequency synthesizers, multipliers And signal modulators, multiplexers and demultiplexers, phase-locked loops, data converters and multi-stage amplifiers. Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 12. A method of designing electronic circuit systems for high-speed signal processing, which at least includes: providing a plurality of individually adjusted building blocks, each of which is a building block It has a similar circuit topology. The circuit topology further includes a functional interconnection set of passive components and several CMOS transistors. For each CMOS transistor, find the adjustable value of the electronic equivalent device parameter (eecp). The EECP system is defined. Is an electronic equivalent channel geometry (EECG), which is equal to the ratio of the channel width to the channel length of an individual CMOS transistor; for each of these passive components to find the adjustable value of EECP, the EECP is defined as an individual passive component One of the known component values; page 29 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)--------- ^ --------- ί Jing «Read the precautions on the back before filling this page] A8B8C8D8 567670 VI. Designation of the scope of patent application-a vector called common factor (CF), which is defined as the vector between the group of passive components and the EECp # combination of the material crystalRatio; and adjust each building block that is individually adjusted, and the adjustment method is such that the CF of each building block that is individually adjusted will not share the same amount, so as to obtain a set of rotation signals with the required signal characteristics. . 13. The method for designing an electronic circuit system as described in item 12 of the application scope, wherein the required signal characteristics of the above output signals include reducing the effects caused by the interaction of two or more building blocks on the system surface. Bad response. 14. The method for designing an electronic circuit system as described in item 12 of the scope of patent application, wherein the required signal characteristics of the above output signal include reducing the degree of output signal ripple. 15. The method for designing electronic circuit systems as described in item 12 of the scope of patent application, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, where the required signal characteristics of the above output signals include reducing the degree of jitter of the wheel-out signal. 16. The method for designing an electronic circuit system as described in item 12 of the scope of the patent application, wherein the required signal characteristics of the above-mentioned output signal further include reducing the degree of unwanted output signal oscillation. Page 30 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 issued) 567670 A8 B8 C8 D8 6. Application for patent scope 17. Method of designing electronic circuit system as described in item 12 of patent scope 'The required signal characteristics of the above-mentioned output signals also include an increase in the dynamic range of the output rfl signal. 18. The method of designing an electronic circuit system as described in item 12 of the scope of the patent application, wherein the required signal characteristics of the above output signals further include an increase in the linear characteristics of the output signals. 1 9. The method of designing electrical circuits and sub-circuit systems as described in item 丨 2 of the scope of patent application, wherein the required signal characteristics of the above-mentioned output signals further include increasing the accuracy of the waveform of the output signals. ^ The method of designing an electronic circuit system described in Fang Cheng's patent application scope 帛 12, where the required signal characteristics of the above output signal also includes the accuracy of increasing the signal phase angle. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 21. Designing the electronic circuit system as described in item 12 of the scope of patent application, wherein the above-mentioned electronic circuit system is specially selected from a group, which includes : Flip-Flop, Frequency Divider, Register and Counter, Timing Device Memory, Special Application Integrated Circuit (ASIC), Arithmetic and Logic List (ALU), Embedded Controller J, Microprocessor, Digital and Analog filter phase frequency detector, frequency talker " only hand-to-mouth generator, multiplier and signal multiplexer and demultiplexer, lock, ^ phase phase, data converter and multi-stage amplifier Yuan -------------· 丨 —---- 丨 Order --- 丨! ί · 线 I {Please read the precautions on the back of the page before filling in this page} Device size page 31 This paper size is applicable to Chinese National Standard (CNS) A4 specifications B8 C8 D8 567670 6. Application for patent scope 22.— An integrated circuit for high-speed signal processing, the integrated circuit includes at least: a first differential circuit for receiving an input signal having a frequency, a second differential circuit, and The first differential circuit is coupled, and each of the first and second differential circuits includes a plurality of transistors, two resistors, and two inductance elements, and the two inductance elements are each connected to the two resistors. For one, each transistor has an electronic equivalent channel geometry (EECG) value to control a current flowing through each transistor, and each of the transistor, the resistor, and the inductive element Has an electronic equivalent element parameter (EOE); wherein a ratio of each of the transistor, the resistor, and the inductive element is determined as one of the transistor, the resistor, and the mother of the inductive element The EECP divided by any one selected from The EECP of each transistor, the resistor, and the inductive element; the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the ratio of each of the transistor, the resistor, and the inductive element with reference to the input signal The frequency is adjusted so that a first set of ratios differs from a second set of ratios, the first set of ratios including the ratio of each of the transistor, the resistor, and the inductive element in the first differential circuit Is different from a ratio of the second group including the ratio of each of the transistor, the resistor, and the inductance element in the second differential circuit. 23. The integrated circuit as described in item 22 of the scope of patent application, in which the above __3rd paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) " 一 —--- oq88 9g ABCD 567670 VI. Patent application scope Transistor, the resistor and the inductance element inherently generate one or more electrical components, which in turn produce different parasitic effects 〇24 · If the scope of patent application No. 23 The integrated circuit according to the item, wherein the parasitic effect is optimized by adjusting one or both of the ratios of the first group and the second group. 25. The integrated circuit as described in item 23 of the scope of patent application, wherein the parasitic effect described above is optimized to minimize possible aftereffects in one of the outputs from the first or second differential circuit. 26. The integrated circuit according to item 22 of the scope of patent application, wherein the two inductive elements in the first differential circuit are disposed adjacent to each other to form a first transformer, and the second differential The two inductive elements in the circuit are arranged adjacent to each other to form a second transformer 27_ The integrated circuit described in item 26 of the scope of patent application, wherein the above-mentioned first group ratio includes a ratio of the first transformer The second set of ratios includes one of the second transformers. 28. The integrated circuit as described in item 26 of the scope of patent application, wherein the EECG of each transistor in the first and second differential circuits is designated as the EECP in the first and second differential circuits. Every transistor Zhao Zhige page 33_ This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---- Ill ------------- Order 丨丨-丨 — 丨 · line (please «read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 567670 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and applied for patent scope EECP {Please «read the precautions on the back, and then fill in this page） 29. The integrated circuit described in item 22 of the scope of patent application The transistor system in the first and second differential circuits is a CMOS transistor, a bipolar transistor, or a field effect transistor. 3 〇 · An integrated circuit system for high-speed signal processing, the integrated circuit system at least includes: at least a first and a second building block, each of the two building blocks includes: several A transistor, a resistor, and an inductive element, each of which has an electric-equivalent channel geometry (EECG) value to control a current flowing through each of the transistors, and the transistor, the resistor, and Each of the inductive components has an electronic equivalent element parameter (EECP); wherein a ratio of each of the above-mentioned transistor, resistor, and inductive element is determined as the transistor, the resistor, and The EECP of the mother of the inductive element is divided by any EECP selected from each of the transistor, the resistor, and the inductive element; and when the first building block receives an input signal having a frequency The ratio of each of the transistor, the resistor, and the inductive element in the first building block is adjusted with reference to the frequency, so that one or more capacitive elements are inherently formed to produce a parasitic effect. 3 1 · The integrated circuit system as described in item 30 of the scope of the patent application, wherein the above-mentioned parasitic effect is used to apply one of the first building blocks L ____ page 34 This paper standard applies to the country of China Standard (CNS) A4 specification (21 × X 297 mm) 567670 A8B8C8D8 6. The possible effect of the patent application scope will be reduced to the lowest after printing effect. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 32. If the scope of patent application is the third one… The integrated circuit system at μ 丨, where the above-mentioned frequency is very high, so the parasitic effect library is used from Feng to maintain the lowest amount of epigenetic effects from one of the first building blocks. 33. The integrated circuit system described in item 32 of the scope of patent application, wherein the first and second building blocks are coupled, and the second adjustable building block receives the output from the first building block, In the second building block, the ratio of each of the transistor, the resistor, and the inductive element can be adjusted so that a second output signal has a minimal amount of epigenetic effects in the second building block. 3 4 · The integrated circuit system described in item 30 of the scope of patent application, wherein any one of the first and second building blocks described above includes a first differential circuit coupled to a second differential circuit Each of the differential circuits includes transistors, resistors, and a transformer formed by two of the inductive elements. 35. The integrated circuit system described in item 34 of the scope of patent application, wherein the ratio of each of the at least some of the transistors, the resistor, and the inductive element in the first building block is different The ratio of each of the transistor, the resistor and the inductive element in the second building block. Please read the notes on the back of this page before filling in δ. Page 35 of this page The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 567670 ΛΟ B8 C8 D8 VI. Scope of patent application% A design method of an integrated circuit processed by a signal mirror, the method includes at least the following steps: determining a frequency of an input signal, the signal is received in a first differential circuit, and one of the first differential circuits is provided. A second differential circuit, each of the first and first differential circuits including a plurality of transistors, two resistors, and two inductive elements, each of which is connected to each of the two resistors One, each transistor has an electronic equivalent channel geometry (EECG) value to control a current flowing through each transistor; determines the transistor, the resistance in the first and second differential circuits Electronic Equivalent Element Parameters (EECP) of each of the resistor and the inductive element; determine one of each of the transistor, the resistor, and the inductive element ', where the ratio is determined as the transistor , The EECP of each of the resistor and the inductive element divided by any EECP selected from the transistor, the resistor and each of the inductive element; and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The ratio of each of the transistor, the resistor, and the inductive element is adjusted with reference to the frequency adjustment so that one or more capacitive elements are inherently generated to form various parasitic effects. 37. The method as described in claim 36, wherein the parasitic effect is used to minimize the possible post-echo effect of the output from one of the first and second differential circuits. Page 36 This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) 567670 6. The scope of patent application A The method as described in item "Scope of patent application", wherein the two inductance elements 该 # in the first differential circuit are arranged with each other to form a = transformer ′ in the second differential circuit. The two inductance elements are arranged adjacent to each other to form a second transformer. 39. As described in item 38 of the scope of patent application, a set of ratios includes the -transformer ratio, and the second set of ratios includes the -transformer. The ratio of one of the two transformers. 40. The method according to item 36 of the scope of patent application, wherein each transistor UEcg in the second differential circuit of the first disc is designated 内 in the first and first differential circuits. EECP of each transistor 41. The π II core is described in item 36 of the patent application scope, wherein the transistor systems in both the first and second differential circuits are cm 0s transistor , Bipolar transistor, or field-effect transistor.: Please read «Read the notes on the back before filling in this page） Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 567670 铖 3 Han EECP 7076 6 5 Positive charge repair Figure 4 No. 5 No.5, Linoa PDJDjoE0Jo = NIHoloCNH u5oalrzH0os usrdli: Purple Life Doll # ^ «CNin〇a PDJOJOJEajou« Viewing Girl FioloCNil KCTinoaliKiHoog = bnolisrB Life + 2.4η 2.6η Time (&n; nHTOIE) 567670 Month f 0 Figure 6 椒 ¥ pepper coinoa pssoLuai 〇 = Join ZHOSCSI.9 " enoalrzHoolo = srd ^^ Ht + PD 』sol £ ai 0 = ^^ (^^ 7 S3 s · ε = IwnoalrzHS s = bldli: 轵 余 4 Figure 2.4η 2.6π 2.8η TIME 567670 The invention: f (VCO) = 40 GHz »f (DATA-IN) = 41 · ό Gbit / sec Xibu Department load = 0 femtofarad fiUJsvudv 1.4η 1.6η 1.βη Time (HnHTIME) 2n Figure 11