CN1479925A

CN1479925A - Boundary addressable memory

Info

Publication number: CN1479925A
Application number: CNA018201822A
Authority: CN
Inventors: 亚历克斯・E・汉德森; 亚历克斯·E·汉德森; ・克罗夫特; 沃尔特·克罗夫特
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2000-11-07
Filing date: 2001-11-07
Publication date: 2004-03-03
Anticipated expiration: 2021-11-07
Also published as: CA2428982C; CA2428982A1; WO2002043069A2; AU2002239502A1; CN1329923C; WO2002043069A3

Abstract

A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM word module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.

Description

Boundary addressable memory

Related application

The application according to 35 U.S.C § 119 (e) require Alex.E.Henderson and WalterE.Croft application on November 7th, 2000, name is called the U.S. provisional application No.60/246 of " Boundary AddressableMemory ", 795 right of priority, its content all is incorporated herein by reference at this.

Technical field

Present invention relates in general to semiconductor memory, more specifically to boundary addressable memory (Boundary Addressable Memory, BAM) equipment.

Background technology

In computer network, the machine network is divided into the small data piece that is called bag usually from the data that a network equipment is sent to another network equipment as calculated.Packet filtering is the network equipment, such as the basic demand of router, upper strata switch, fire wall, Bandwidth Broker and similar devices.

Content Addressable Memory (CAM) equipment is the known semiconductor equipment that is used for carrying out data screening in the categorizing system.CAM allows the content of search and coupling storer and needn't specify one or more concrete storage unit from the memory search data.Usually an example that uses the application of CAM equipment is that the search routing table is so that check the destination address of coupling, such as Internet agreement (IP) destination address, so that can route data to the appropriate purpose address.After identifying match address, the filter criteria that requires usually to use other determines whether match address drops in a certain scope.The scope verification is the application in the computer network, such as the range of port number in the verification Ethernet mac header and effective length and types value.Yet, realize that the scope verification that is used for nonbinary CAM requires a plurality of inlets.Having a plurality of inlets makes connect up very costliness and space utilization efficient low.In addition, the memory device of similar CAM comes the search matched data by checking the whole zone in a plurality of cycle memory reservoirs, thereby increases the stand-by period.

Therefore, need be used to carry out the memory device of arithmetic scope verification.

Summary of the invention

The present invention has overcome the defective and the restriction of the prior art with boundary addressable memory (BAM) equipment that is used for carrying out the verification of categorizing system arithmetic scope.Advantageous particularly of the present invention because its usable range verification is carried out arithmetic relatively, rather than carry out similar CAM equal comparison (equality comparison).The verification of arithmetic scope is provided for mating the method that is less than or equal to the input value of higher limit more than or equal to the lower limit of storage simultaneously.

BAM equipment of the present invention comprises the array of BAM word modules (word module).Each BAM word modules comprises a plurality of BAM unit.In a preferred embodiment of the invention, each BAM unit comprises the storage unit of n position of storage cap value and the storage unit of n position of storage lower limit.The BAM unit further comprises the arithmetic upper limit comparer relatively between the n position that is used to carry out the n position of higher limit and import data.The BAM unit also comprises the arithmetic lower limit comparer relatively between the n position that is used to carry out the n position of lower limit and import data.

In a preferred embodiment of the invention, occurring in the BAM equipment search by following mode has and is less than or equal to the lower limit of import data and more than or equal to the BAM word of the higher limit of importing data.The n position of input data is offered upper limit comparer and lower limit comparer simultaneously.Upper limit comparer compares the n position of the higher limit of the n position of input signal and storage.Simultaneously, the lower limit comparer n position that will import the lower limit of the n position of data and storage compares.Bit by bit execution relatively and from the highest command bit (highest order bit) propagates into minimum command bit always.Therefore, the BAM word asserts whether (assert) expression input data are less than or equal to higher limit and more than or equal to lower limit, or whether the input data are more than or equal to higher limit and be less than or equal to the signal of lower limit.

The coupling logic gate receives being less than or equal to of each BAM word modules and more than or equal to output, and the output that receives of response, generates matched signal.In one embodiment of the invention, matched signal is represented to import data and is dropped in the scope by higher limit and lower limit appointment.In another embodiment, matched signal is represented to import data and is dropped on outside the scope by higher limit and lower limit appointment.

These and other features of the present invention and advantage become better understood by the detailed description of considering following the preferred embodiments of the present invention.During describing, continually with reference to the accompanying drawings.

Description of drawings

The boundary addressable that Fig. 1 is made up of a plurality of BAM word modules is stored (BAM) array

The high level block diagram of embodiment.

The high level block diagram of the embodiment of the BAM word modules of the embodiment of Fig. 1 that Fig. 2 is made up of a plurality of BAM unit.

Fig. 3 is the high level block diagram of embodiment of a BAM unit of BAM word modules of the embodiment of Fig. 2.

Fig. 4 is that the gate leve of upper limit segment of the BAM unit of Fig. 3 is realized.

Fig. 5 is that the transistor level of upper limit segment of the BAM unit of Fig. 3 is realized.

Fig. 6 is that the lower limit gate leve partly of the BAM unit of Fig. 3 is realized.

Fig. 7 is that the lower limit transistor level partly of the BAM unit of Fig. 3 is realized.

Fig. 8 is the high level block diagram that equals circuit (look ahead equalcircuit) in advance of the embodiment of Fig. 4 and 6.

Fig. 9 is with the be stacked block diagram of lead-circuit of Fig. 8 of realizing of upper limit comparer and lower limit comparer.

Figure 10 is that the transistor level of the upper limit segment of low-power BAM unit is realized.

Figure 11 is that the transistor level of the lower limit part of low-power BAM unit is realized.

Figure 12 is the BAM unit sequential chart of the embodiment of Figure 10 and 11.

Embodiment

With reference now to Fig. 1,, the figure shows high level block diagram according to the embodiment of border addressable storage (BAM) array 100 of embodiment of the present invention.BAM array 100 comprises a plurality of BAM word modules 102 (a)-102 (n), wherein the quantity of BAM word modules 102 in (n) expression array 100.Each BAM word modules 102 (a)-102 (n) is by a plurality of BAM unit 50 (a)-(n) form, and the example of BAM unit at length illustrates in Fig. 3.Each storage cap position, BAM unit 50 (a)-(n) and lower limit are shown in following Fig. 3-7.Each upper limit and lower limit are the arbitrary values that is used for carrying out the scope verification in the BAM array 100.Each BAM word modules 102 (a)-102 (n) can be provided by storage in the input data that provide on the signal wire 70 and each the BAM unit 50 (a)-(n) at BAM word modules 102 (a)-102 (n) corresponding upper limit and the arithmetic between the lower limit compare.Each BAM word modules 102 (a)-102 (n) be preferably in signal wire 62 (a)-62 (n) go up output be less than or equal to signal and signal wire 64 (a)-64 (n) go up output more than or equal to signal.Coupling logic gate 15 (a)-15 (n) is come respectively being less than or equal to signal and more than or equal to signal, and going up the generation matched signal at each signal wire 75 (a)-75 (n) on each BAM word modules 102 (a)-102 (n) received signal line 62 (a)-62 (n) and 64 (a)-64 (n).In one embodiment of the invention, matched signal is not more than and concludes when being stored in the higher limit in the BAM word 102 (a)-102 (n) and being not less than lower limit that it is high when input data that provide on signal wire 70 are provided for it.In another embodiment of the present invention, matched signal concludes when the input data that provide on the signal wire 70 are not less than higher limit and are not more than lower limit that when it is illustrated in it is high.Not shownly being used for reading higher limit and lower limit and it is write the bit line of each BAM word 102 (a)-102 (n), because they are conventional, and is that those skilled in the art understands.

With reference now to Fig. 2,, the figure shows a BAM word modules 102 (n).BAM word modules 102 (n) comprises a plurality of BAM unit 50 (a)-(n).The present invention is embodied as 32 BAM word modules in a preferred embodiment, thereby it will have 32 BAM unit 50.Yet, those skilled in the art will recognize, BAM word modules 102 (n) can be any size.As shown in Figure 2, BAM word modules 102 (n) is divided into a plurality of BAM unit 50 (a)-(n), be used for carrying out the input value that provides on the signal wire 70 and be stored in the n position of higher limit of each BAM unit 50 (n) and the n position of lower limit between arithmetic relatively.

In a preferred embodiment, a highest significant position is estimated in each BAM unit 50 (a)-(n) at every turn.In each BAM unit 50 (a)-(n), carry out relatively and propagate into minimum command bit from the highest command bit with the form of daisy chain.Each BAM unit 50 (a)-(n) is coupled to wired OR signal wire 62,64.If any one is high in BAM unit 50 (a)-(n), concludes so on

signal wire

62,64, to be high signal, and hang up comparison low command bit.With logic gate 15 (n) be coupled to be used to receive smaller or equal to signal smaller or equal to signal wire 62.Further logic gate 15 (n) is coupled to be used to receive more than or equal to signal more than or equal to line 64.In a preferred embodiment of the invention, the matched signal of logic gate 15 (n) on execution AND function in two inputs is asserted signal wire 75 (n) simultaneously.Logic gate 15 when smaller or equal to and be more than or equal to signal and assert when high to go up and be " height " at its each signal wire 75 (n).In one embodiment of the invention, when concerning at least one BAM unit 50 (a)-(n), when input signal is not more than higher limit and is not less than lower limit simultaneously, smaller or equal to and be height more than or equal to signal.In another embodiment of the present invention, when concerning at least one BAM unit 50 (a)-(n), when input signal was not less than higher limit and is not more than lower limit simultaneously, these two signals were " height ".Otherwise logic gate 15 (n) concludes that going up at its output 75 (n) is " false " or " 0 ".

With reference now to Fig. 3,, it shows the preferred embodiment of the BAM unit 50 (n) of BAM word 102 (n) as shown in Figure 2.This exemplary BAM unit 50 (n) comprises a plurality of typical six layer transistor

SRAM storage unit

52 and 54, upper limit comparer 56 and lower limit comparer 58.Upper limit bit line 9 is to be used to read higher limit and it is write the bit line of the routine of sram cell 52.Lower limit bit line 11 is to be used for reading lower limit and it is write the bit line of the routine of sram cell 54.Bit line driver 12 is pushed to

sram cell

52,54 with higher limit and lower limit, and IN and IN N value are pushed to comparer 56,58.Upper limit comparer 56 is coupled to sram cell 52 to receive higher limit from sram cell 52.Lower limit comparer 58 is coupled to sram cell 54 to be come from sram cell 54 lower acceptance values.Sensing equipment 55 is the conventional sensor amplifiers that are coupled so that read the content of the upper and lower bound position that is stored in the

sram cell

52,54.

In operation, BAM word 102 (a)-(n) according to embodiments of the invention search matched in BAM equipment 100 takes place in the following manner.The n position of input data on the input signal cable 70 is offered upper limit comparer 56 and lower limit comparer 58.Upper limit comparer 56 compares the n position of input signal with the corresponding positions that is stored in the higher limit among the SRAM 52.Simultaneously, lower limit comparer 58 compares the n position of input signal with the corresponding positions that is stored in the lower limit among the SRAM 54.To offer upper limit comparer 56 and on signal wire 67, will equal signal and offering lower limit comparer 58 from the signal that equals of higher command bit on the signal wire 60.Each that provides on signal wire 60,67 equals each command bit that signal indication is higher than the n position of importing data and equals to be stored in corresponding positions among the

SRAM

52,54.

In the preferred embodiment, in each BAM unit 50 (a)-(n), carry out relatively and propagate into minimum command bit from the highest command bit always with the form of daisy chain.If the comparative result of carrying out in BAM unit 50 (n) is " equaling ", promptly, each command bit that is higher than the n position of importing data equals to be stored in the corresponding positions among the

SRAM

52,54, and lower limit comparer 58 is asserted high in outputing signal to next BAM unit 50 on the signal wire 90.Equally, upper limit comparer 56 is asserted high in output signal to next BAM unit 50 on the signal wire 99.If the comparative result of carrying out in BAM unit 50 (n) be " being less than or equal to ", then upper limit comparer 56 assert on the signal wire 62 high signal (as shown in Figure 2) and forbid relatively hanging down command bit.Equally, if the comparative result of in BAM unit 50 (n), carrying out be " more than or equal to ", so lower limit comparer 58 assert in signal wire 64 (as shown in Figure 2) high signal and forbid relatively low command bit.Those skilled in the art will recognize, carry out relatively in each the BAM word modules 102 (a)-(n) in BAM array 100 simultaneously.

With reference now to Fig. 4,, the gate leve that the figure shows the upper limit segment of the BAM unit of describing in conjunction with Fig. 3 50 (n) is realized.The upper limit segment of BAM unit 50 (n) comprises upper limit comparer 56 and sram cell 52.In one embodiment of the invention, with upper limit comparer 56 as be used for carrying out " smaller or equal to " relatively NAND gate circuit 10, be used for carrying out " equaling " biconditional gate circuit 20 relatively, and be used to carry out the AND operation and be used on each signal wire 90, will equaling output signal and export to the AND gate circuit 30 of next BAM unit 50 and realize.In a preferred embodiment, AND gate circuit 30 is realized as NAND gate circuit 33 and phase inverter 35.(not shown) is realized AND gate circuit 30 as the AND gate circuit in another embodiment.

NAND gate circuit 10 has three inputs.The input signal cable 70 that is used to receive the n position of importing data is coupled in first input.Second input is coupled to is used for receiving the signal wire 60 equal signal (check bit signal).When to equal output signal be high, each command bit that its expression is higher than current input position equated with the corresponding positions of higher limit in being stored in SRAM 52.The signal wire 53 of the anti-phase output that is used to receive SRAM 52 is coupled in the 3rd input of NAND gate circuit 10.The drain coupled of NAND gate circuit 10 is arrived smaller or equal to signal wire 62.Should be the wired OR lines smaller or equal to signal of asserting that it is exported smaller or equal to signal wire 62.

Biconditional gate circuit 20 has two inputs.First input of biconditional gate circuit 20 is coupled to input signal cable 80 so that the anti-phase n position of receiving inputted signal.Second input of coupling biconditional gate circuit 20 is so that receive the anti-phase output of SRAM 52 on signal wire 53.Unit on the output assertion signal wire 25 of biconditional gate circuit 20 equals (cell equal) signal.

AND gate circuit 30 has two inputs.First input is coupled to and is used to receive the signal wire 60 that equals signal.The unit that second input is coupled to the output (unit equals signal) that is used to receive XNOR gate circuit 20 equals signal wire 25.AND gate circuit 30 is asserted the output signal that equals on the signal wire 90.Should be appreciated that simultaneously and to carry out " smaller or equal to " and the comparison of " equaling " signal.

In a preferred embodiment, carry out relatively with following manner.

1, signal equates

The n position of the input data that provide on input signal cable 70 and the n position of storage are (both all have logical one or logical zero value) that equates.On signal wire 62, equal the input signal height.NAND gate circuit 10 receives the following signal in its input: the output of the SRAM 52 on the input signal on the signal wire 70, the signal wire 53; And equal signal on the signal wire 60.NAND gate circuit 10 is carried out the NAND functions and is asserted high signal on the signal wire 62.

When carrying out relatively with NAND gate circuit 10, the comparison of the output of the SRAM 52 on the biconditional gate circuit 20 received signal lines 53 and the rp input signal on the signal wire 80 and execution " equaling " line.Because the input signal of SRAM 52 and output equate that XNOR gate circuit 20 asserts that the high unit on signal wire 25 equals signal.If it is (both all have logical value " 1 " or " 0 ") that equate that this unit equals these two signals of signal indication, the comparative result to this discrete cell is " equating " so.Unit on the AND gate circuit 30 received signal lines 25 equals the high AND function of carrying out in input signal and on these two signals on signal and the signal wire 60.AND gate circuit 10 is asserted on signal wire 90 to high in output signal.This is high represents that in output signal (equal out signal) all are " equating " in preceding BAM unit, and current relatively be " equating ".Therefore, make to equal output signal and become and equal input signal and will relatively propagate into next significance bit (BAM unit 50), up to the input signal on signal wire 70 less than be stored among the SRAM 52 higher limit or greater than higher limit.

2, smaller or equal to

When the input signal on the signal wire 70 is logical zero and SRAM 52 when being output as logical one, high on the NAND gate circuit 10 received signal lines 62, the low output of the SRAM 52 on the signal wire 53 and the low input-signal on the signal wire 70 in input signal.NAND gate circuit 10 after carrying out the NAND operation, assert on the signal wire 62 for higher primary school in equaling signal.

When carrying out relatively by NAND gate circuit 10, the comparison of rp input signal on the biconditional gate circuit 20 received signal lines 80 and the anti-phase output of the SRAM 52 on the signal wire 430 53 and execution " equaling " line.Biconditional gate circuit 20 is asserted after carrying out " together " function and is equaled signal for hanging down the unit on the signal wire 25.The low unit of AND gate circuit 30 on its input received signal line 25 equals the high AND function of carrying out in input signal and on these two signals on signal and the signal wire 60.AND gate circuit 30 is asserted and is the low output signal that equals on the signal wire 90.

As this result relatively, input signal is not greater than or equal to the storage signal that the output at SRAM 52 provides.Still being high and forbidding propagating all low command bits on the signal wire 62 smaller or equal to signal.Higher primary school on logic gate 15 (n) the received signal line 62 as illustrated in fig. 1 and 2 is in equaling signal.

3, greater than

Input signal on the signal wire 70 is a logical one, and the SRAM 52 on the signal wire 53 is output as logical one, and the input signal that equals on the signal wire 60 is a logical one.NAND 10 is carrying out the NAND function and is asserting low signal on the signal wire 62 on three signals.This signal indication input signal is greater than the position that is stored among the SRAM 52.Therefore, forbid propagating hanging down on all low command bits and the logic gate 15 received signal lines 62 smaller or equal to signal, as illustrated in fig. 1 and 2.

Table 1 example explanation is when the upper limit that the input position equals to store, and is not more than the upper limit of storage and the situation during greater than the upper limit of storage.

The comparison diagram that table 1. is carried out in the lower part of BAM unit 50 (n).

????IN	????IN_N	????SRAM	SRAM square wave (bar)	Equal input	The input of NAND door	Smaller or equal to	The input of XNOR door	The unit equals	The input of AND door	Equal output
????IN	????IN_N	????SRAM	SRAM square wave (bar)	Equal input	The input of NAND door	Smaller or equal to	The input of XNOR door	The unit equals	The input of AND door	Equal output	????0	????1	????0	??1	????1	??0，1，1	??1	??1，1	??1	??1，1	Equal to export=equal to import
????1	????0	????1	??0	????1	??1，1，0	??1	??0，0	??1	??1，1	Equal to export=equal to import	????0	????1	????0	??1	????1	??0，1，1	??1	??1，1	??1	??1，1	Equal to export=equal to import
????1	????0	????1	??0	????1	??1，1，0	??1	??0，0	??1	??1，1	Equal to export=equal to import	????0	????1	????1	??0	????1	??1，0，0	??1	??1，0	??0	??0，1	0
????1	????0	????0	??1	????1	??1，1，1	??0	??0，1	??0	??1，0	0	????0	????1	????1	??0	????1	??1，0，0	??1	??1，0	??0	??0，1	0

Should be appreciated that in the available many possible modes of the gate leve figure shown in Fig. 4 and on transistor level, realize.Fig. 5 shows the exemplary embodiment of gate leve figure of the upper limit segment of BAM unit 50 (n).As shown in Figure 5, the function of NAND door 10 realizes as transistor M1, M2 and M3.The function of XNOR door 20 realizes as transistor M4-M7 and M10.The function of AND door 30 realizes as transistor M8 and M9.

Transistor M1, M2 and M3 realization " smaller or equal to " logic line.The leakage level of M1 is connected to smaller or equal to line 62.The source electrode of M1 is connected to the drain electrode of M2.The source electrode of M2 is connected to the drain electrode of M3.Bit line 9 writes sram cell 52 with higher limit.The M2 grid receives the anti-phase output of sram cell 52.Rp input signal on the M3 received signal line 80.The source electrode of M3 is connected to VSS ground.

The function of the XOR gate 20 that the XNOR door 20 among the embodiment of replacement Fig. 4 is realized realizes as M4, M5, M6 and M7.These transistors are carried out " equaling " line relatively.The source electrode of M4 is connected to the drain electrode of M5.The drain electrode of M4 is connected to the drain electrode of M6.The source electrode of M5 is connected to VSS ground.The source electrode of M6 is connected to the drain electrode of M7.The source electrode of M7 is connected to VSS ground.

Replace the function of the NOR door 30 that the AND door 30 of the embodiment of Fig. 4 realizes to realize at this as transistor M8 and M9.These transistors are carried out " equaling output " logic.The drain electrode of M8 is connected to the drain electrode of M9.M10 is used for the transistor of pre-service transistor M4, M5, M6 and M7.M10 is connected to the drain electrode of M4 and the drain electrode of M6.The source electrode of M10 is connected to VDD.Should be noted that transistor M8 and M10 realize as the PMOS transistor.All the other all crystals pipes are realized as nmos pass transistor.

Embodiment shown in Fig. 5 advantageously allows BAM array 100 to carry out the scope verification in one-period.This cycle is divided into three phases: set up pretreatment stage, affirmation during all hypothesis or comparison phase and the update stage during invalid all supposition.

During the pretreatment stage in cycle, the best following signal of pre-service: the unit smaller or equal on signal, the signal wire 25 on the signal wire 62 equals the input signal on square-wave signal (bar signal) and signal wire 70 and 80.In a preferred embodiment, the input signal on the

precharging signal line

70 and 80 to low level so that make the power consumption conservation.Behind the precharge input signal, allow them to enter their original state.In the preferred embodiment, on the putative signal line 62 is high (logical one) smaller or equal to signal, and the input signal on the expression signal wire 70 is not more than the respective stored position among the SRAM 52.Unit on the PMOS transistor M10 preprocessed signal line 25 equals square-wave signal so that it is assumed to height (logical one), thereby the input signal that is illustrated on the signal wire 70 is not equal to bank bit.It will be apparent to one skilled in the art that and to use any PMOS transistor to come pre-service smaller or equal to the signal on the signal wire 62.In another embodiment, will be low value smaller or equal to Signal Pretreatment on the signal wire 62.Therefore, suppose that input signal is not less than the position that is stored among the SRAM 52.Equally, it is low level that the unit on the signal wire 25 is equaled the square-wave signal pre-service, thereby the expression bank bit equals to import the n position of data.

During the comparison phase behind the pretreatment stage, carry out all comparisons and the hypothesis of in the phase one, setting up or invalid or effective.

1, signal equates

Input signal on signal wire 70 and the position that is stored among the SRAM 52 equate.The transistor M1-M3 that carries out the NADN function asserts the high signal on signal wire 62.Therefore, represent that it is effective that input signal is not more than the initial supposition that is stored in the position among the SRAM 52.The transistor M4-M7 that carries out NOR door function exports low unit and equals square-wave signal on signal wire 25, thereby invalid these two signals are unequal initial supposition.Carry out the transistor M8 of AND function and M9 and export high unit equal output signal on signal wire 90, expression is imported n position that the n position of data equals to store and is " equating " in the result of preceding comparison.Therefore, to equal output signal and become and equal input signal and will relatively propagate into next BAM unit 50 (n) so that carry out comparison of next low command bit, the input signal on signal wire 70 greater than or be not more than the signal that the output at SRAM 52 provides.

2, smaller or equal to

Input signal on the signal wire 70 has the logical zero value, and the position that is stored among the SRAM 52 is logical one, and is height at the signal that equals on the incoming line 60.Transistor M1-M3 asserts after carrying out the AND function and is high signal on the signal wire 62, thereby makes initial supposition effective.Simultaneously, transistor M4-M7 exports high unit and equals square-wave signal on signal wire 25, shows that the unequal initial supposition of these two signals is effective thereby make.High high unit on input signal and signal wire 25 on M8 and the M9 received signal line 60 equals square-wave signal, and the low unit of output equals output signal on signal wire 90.

Therefore, will represent that on signal wire 62 input signal is not more than the higher primary school that is stored in the position among the SRAM 52 and offers as shown in Figure 1, 2 logic gate 15 (n) in equaling signal, and forbid propagating into low command bit.

3, greater than

Input signal has the logical one value, and the SRAM position of storage has the logical zero value, and provides on signal wire 60 and equal input signal.Transistor M1-M3 carries out the NAND function on three signals.As the result of NAND operation, M1-M3 asserts and be low signal on signal wire 62, thereby the initial supposition of expression is wrong, that is, input signal is greater than the position of storage.Logic gate 15 (a)-(n) as shown in Figure 1, 2 receives smaller or equal to the low signal on the signal wire 62.The comparison of hang-up all low command bits in BAM word modules 102 (n).

When invalid initial supposition, upgrade all pretreated in pretreatment stage signals in update stage, so that make their each values become " low " or become " height " from " low " from " height ".

With the upper limit segment of BAM unit 50 (n) in the comparison carried out, in the lower limit part of BAM unit 50 (n), carry out relatively.Describe these in detail relatively below in conjunction with Fig. 6 and 7.

With reference now to Fig. 6,, the gate leve that the figure shows the lower part of BAM unit 50 (n) is realized.The lower limit of BAM unit 50 (n) partly comprises lower limit comparer 58 and sram cell 54.The gate leve that should be noted that the lower part of BAM unit 50 (n) is realized with the realization of the upper limit segment of BAM unit 50 (n) similar.Be some differences between the gate leve of the lower limit part of the upper limit segment of BAM unit 50 (n) and BAM unit 50 (n) is realized below: the n position of the input signal on the NAND door 10 received signal lines 70, be stored in the antiphase in the sram cell 54 and equal input signal 67.58 execution of lower limit comparer " more than or equal to " relatively.Sram cell 54 storage lower limits.In operation, as realizing in a preferred embodiment, if the n position of input signal is not less than and is stored in the n position among the SRAM 54 and equals input signal 67 is really (promptly, each higher command bit equals its corresponding bank bit), will drag down and hang up any further propagation more than or equal to line 64 so.If opposite, the n position of input signal is not less than the n position of storage, still is high more than or equal to signal wire 64 so and all propagation of the extremely low command bit of hang-up.

With with " equaling " intimate mode of the upper part of BAM unit 50 (n) carry out BAM unit 50 (n) lower part " equaling " relatively.It is some differences below: the n position of input signal and be stored among the SRAM54 one on the XNOR door 20 received signal lines 70.In the gate leve of the upper limit segment of BAM unit 50 (n) is realized, the rp input signal on the XNOR door 20 received signal lines 80 and be stored in antiphase among the SRAM 54.

It is similar with table 1 that the comparison diagram of carrying out in the upper limit segment of BAM unit 50 (n) seems, but it demonstrates when the lower limit that input position equals to store, the lower limit that is not less than storage and the situation during less than the upper limit of storage.

With reference now to Fig. 7,, the transistor level that the figure shows the lower limit gate leve figure partly of BAM unit 50 (n) is realized.Except that having some differences, utilize the mode identical to realize the lower part of BAM unit 50 (n) with the upper part of BAM unit 50 (n).For example, the lower limit comparer 58 of the lower part of BAM unit 50 (n) is carried out more than or equal to comparing.At pretreatment stage, will be high more than or equal to signal wire 64 pre-service by PMOS transistor (not shown).Bit line 11 writes sram cell 54 with lower limit.Transistor M2 receives the position and the M6 that are stored among the SRAM 54 and receives anti-phase bank bit.Rp input signal on the M3 received signal line 80, and the input signal on the M5 received signal line 70." equaling " logic with the lower part of " equaling " logic realization BAM unit 50 (n) of the upper part that is similar to BAM unit 50 (n).

If make initial supposition invalid, then renewal equals square-wave signal line 25 more than or equal to signal wire 64 and unit during update stage, so that their values are separately become " low " or become " height " from " low " from " height ".Should be appreciated that can be by being pre-charged to them the pre-service that high or low value realizes signal.Similarly, can be by they being discharged into the renewal that high or low value realizes signal.

If result as a comparison, the n position of input signal equals the n position of lower limit, then will relatively propagate into next n position (BAM unit 50).Perhaps, the comparison in the hang-up residue BAM unit 50 also offers logic gate 15 (a)-(n) (as shown in Figure 2) with high or low more than or equal to signal on signal wire 64.

Fig. 8 is the block diagram that equals circuit 45 in advance of BAM word 102 (n) that is coupled to the embodiment of Fig. 2.In the preferred embodiment, BAM word modules 102 (a)-(n) (as illustrated in fig. 1 and 2) is 32 bit wides, thereby has 32 BAM unit 50.In one embodiment of the invention, lead-circuit 45 each estimations are four.Yet, it will be apparent to one skilled in the art that lead-circuit 45 once can estimate any amount of position.As shown in Figure 8, four upper limit segments of BAM unit 50 (n) or lower limit partly are connected to each other.Each BAM unit 50 (n) output unit on signal wire 25 equals output signal.In a preferred embodiment, lead-circuit 45 is AND doors of one 5 input, and it is formed by NAND door 33 and a phase inverter 35.Lead-circuit 45 is coupled to signal wire 25 so that equal output signal from four BAM unit 50 receiving elements.Further lead-circuit 45 is coupled to and equals input signal cable 60 so that reception equals input signal.Lead-circuit 45 determines whether four input signals that provide equal to be stored in respectively four higher limits or the lower limit in the sram cell 52 and 54 (not shown in Fig. 8) on signal wire 70, and output Fast equals output signal on signal wire 92 separately.The preferred realization of circuit 45 requires 8 propagation, and the Fast of following four BAM unit 50 equals output signal so that generate extremely on signal wire 92.

The advantage that equals lead-circuit 45 is to simplify each and equals the logic that output signal must be passed through.Thereby, be not to wait for the propagation of a series of changes, but no matter whether higher command bit equates that all each upper limit segment or four unit of generation, lower limit partial parallel ground to BAM unit 50 (n) equal signal from the highest command bit to minimum command bit.This velocity of propagation is that cost realizes with other 5 AND doors 45.Those skilled in the art will recognize, BAM equipment 100 can have the lead-circuit 45 more than 1.Therefore, Fig. 9 example explanation is used for propagating respectively 1 above Fast and equals two of output signal and equal lead-circuit 45a and 45b on signal wire 92a and 92b.

With reference now to Figure 10,, another transistor level of upper limit segment that the figure shows the low-power BAM unit 50 (n) of Fig. 3 is realized.The upper limit segment of BAM unit 50 (n) comprises sram cell 52, NAND door 10, XNOR door 20 and NOR door 30.NAND door 10 is realized as transistor M1, M2, M3 and M10.The drain electrode of M3 is connected to smaller or equal to line 62.The source electrode of M1 is connected to the drain electrode of M2.Transistor M10 is inserted between transistor M2 and the M3, so that the source electrode of M2 is connected to the drain electrode of M10.The grid of M2 is connected to the anti-phase output of sram cell 52.The source electrode of M3 is connected to VSS ground.XNOR door 20 is realized as transistor M4, M5, M6, M7, M11 and M12.Transistor M11 is inserted between transistor M4 and the M5.Transistor M12 is inserted between transistor M6 and the M7.The source electrode of M4 is connected to the drain electrode of M11.The drain electrode of M4 is connected to the drain electrode of M6.The source electrode of M5 is connected to VSS ground.The source electrode of M6 is connected to the drain electrode of M7.The source electrode of M7 is connected to VSS ground.M15 is a precharge transistor, is connected to the drain electrode of M4 and the drain electrode of M6.The source electrode of M10 is connected to VDD.Should be noted that with the PMOS transistor and realize transistor M15.Every other transistor is realized with nmos pass transistor.

In operation, when asserting that when equating gating 68, transistor M11 and M12 are for opening.On

signal wire

70 and 80, input signal offered transistor M5 and M7.Output with SRAM 52 on signal wire 53 offers transistor M4 and M6.Whether the n position of transistor M11-M12 and M4-M7 estimation input signal equals the signal that the output at SRAM 52 provides, and asserts that the unit on the signal wire 25 equals square-wave signal.Coupling NAND door 33 is so that the rp unit on the received signal line 25 equals the input signal that equals on square-wave signal (unit equals) and the signal wire 60.In the input of NAND door 33, provide and equal to make its anti-phase twice before the input signal 60.The output of NAND door 33 be before being illustrated in relatively for equate and in this BAM unit 50 (n) execution relatively be the output signal that equals that equates.

After execution equals comparison, assert smaller or equal to strobe pulse 66, thereby connect transistor 10.When transistor M10 when opening, determine whether the n position of input signal the signal that provides is provided on SRAM52.Therefore, in this embodiment, do not resemble and carry out all preferred embodiments relatively simultaneously, only when assert " equating " gating, " smaller or equal to " gating or " more than or equal to " just carry out all estimations during gating.At the embodiment shown in Figure 10 is favourable because use to equate gating allow on the signal wire 25 equal signal carrying out less than or before relatively, propagate by daisy chain.

Should be noted that in this preferred embodiment during pre-charging stage, the input signal that will provide is precharged as 0 on signal wire 70 and 80.Behind pretreatment stage, allow these signals to get back to their original state.In this embodiment, input signal does not need pre-service so that they can forward any state to during pre-charging stage.

The transistor body level of the lower limit part of the low-power BAM unit 50 (n) of Figure 11 presentation graphs 3 realizes.Realize the lower part of low-power BAM unit 50 (n) with the mode similar to the upper limit segment of low-power BAM unit 50 (n).Do not resemble the upper limit segment of BAM unit 50 (n), lower part is carried out more than or equal to comparing.

With reference now to Figure 12,, the figure shows the sequential chart of the low-power BAM unit 50 (n) of the relation between the signal of expression Figure 10 and 11 embodiment.At first, in pre-charging stage, preferably the unit that provides on signal wire 25 by transistor M15 precharge equals signal.By the precharge of PMOS transistor (not shown) smaller or equal to signal wire 62 with more than or equal to signal wire 64.Then, assert and equate gating 68.Equate that gating 68 is that expression needs to carry out all timing signals that equal to calculate.After carrying out all and equaling estimation, assert expression need to carry out " smaller or equal to " or " more than or equal to " relatively smaller or equal to gating 66 or more than or equal to gating 69.

Claims

1, a kind of boundary addressable memory (BAM) equipment comprises:

BAM word modules device, each BAM word modules is used for carrying out the input data and is stored between the higher limit of each BAM word and this input data and be stored in arithmetic comparison between the lower limit in each BAM word modules, and is used to respond this and relatively produces a plurality of output signals; And

Logic gate with input and output, the input of this logic gate that is coupled is so that receive the output of each BAM word modules, and the output of this logic gate that is coupled is so that generation expression input data are not more than higher limit and are not less than lower limit or import the matched signal that data are not more than lower limit and are not less than higher limit.

2, equipment as claimed in claim 1 is characterized in that: each BAM word modules further comprises a plurality of BAM unit, and wherein each BAM unit further comprises:

At least two storage unit are used for storage cap value and lower limit;

First comparer is used for input data and higher limit are compared, and this first comparer has input and output, and the input of this first comparer that is coupled receives input data and higher limit, and logic gate is coupled in the output of this first comparer;

Second comparer is used for input data and lower limit are compared, and this second comparer has input and output, and the input of this second comparer that is coupled is so that receive input data and lower limit, and logic gate is coupled in the output of this second comparer.

3, equipment as claimed in claim 1 is characterized in that: each storage unit is a sram cell.

4, a kind of boundary addressable memory (BAM) unit comprises:

The first pre-service logic is used for the first comparison signal pre-service to first state;

Be coupled to first logic of this first pre-service logic, this first logic has first input, second input, the 3rd input and output, the input signal cable that equals that is used to receive first check bit is coupled in first input, the signal wire that is used to receive bank bit is coupled in second input, the input signal cable that is used for receiving inputted signal is coupled in the 3rd input, first logic is used for the input position is compared with bank bit, and be used for based on the comparison, whether correctly confirm first comparison signal by first state of representing first comparison signal;

Be coupled to the second pre-service logic of first logic, be used for the second comparison signal pre-service to second state;

Be coupled to second logic of the second pre-service logic, it has first input, second input and output, the signal wire that is used to receive bank bit is coupled in first input, and second input is coupled to the input signal cable that is used for receiving inputted signal, second logic gate is used for input signal and storage signal are compared, and whether correctly confirms second comparison signal by first state of representing second comparison signal; And

The 3rd logic with first input, second input and output, the input signal cable that equals that is used to receive check bit is coupled in first input, the unit that is used to receive second comparison signal is coupled in second input equals signal wire, the 3rd logic gate is used to assert second check bit to next highest significant position in its output, represents whether correct whether second state of second comparison signal and first check bit be true.

5, unit as claimed in claim 4 is characterized in that: bank bit is the highest significant position of higher limit.

6, unit as claimed in claim 4 is characterized in that: bank bit is the highest significant position of lower limit.

7, unit as claimed in claim 4 is characterized in that: first logic is the NAND door.

8, unit as claimed in claim 4 is characterized in that: second logic is an XOR gate.

9, unit as claimed in claim 4 is characterized in that: the 3rd logic gate is the NOR door.

10, unit as claimed in claim 4 is characterized in that: the 3rd logic gate is the NOR door.

11, unit as claimed in claim 4 is characterized in that: the first state representation input signal of first comparison signal is smaller or equal to bank bit.

12, unit as claimed in claim 4 is characterized in that: the first state representation input signal of first comparison signal is not below or equal to bank bit.

13, unit as claimed in claim 4 is characterized in that: the first state representation input signal of first comparison signal is more than or equal to bank bit.

14, unit as claimed in claim 4 is characterized in that: the first state representation input signal of first comparison signal is not more than and equals bank bit.

15, unit as claimed in claim 4 is characterized in that: the second state representation input signal of second comparison signal equals bank bit.

16, unit as claimed in claim 4 is characterized in that: the second state representation input signal of second comparison signal is not equal to bank bit.

17, unit as claimed in claim 4 is characterized in that: first logic realizes as nmos pass transistor.

18, unit as claimed in claim 4 is characterized in that: second logic realizes as nmos pass transistor.

19, unit as claimed in claim 4 is characterized in that: the 3rd logic realizes as the PMOS transistor.

20, unit as claimed in claim 4 is characterized in that: the 3rd logic realizes as nmos pass transistor.

21, unit as claimed in claim 4 is characterized in that: the first and second pre-service logics all realize as the PMOS transistor.

22, a kind of method that is used for generating at boundary addressable memory (BAM) equipment matched signal comprises:

Input data and the higher limit that is stored in the BAM equipment are compared and generate first output whether expression input data are not more than this higher limit;

Input data and the lower limit that is stored in the BAM equipment are compared and generate second output whether expression input data are not less than this lower limit; And

Export and generate the matched signal whether expression input data are not more than this higher limit and are not less than this lower limit in conjunction with first output and second.

23, a kind of method that is used for generating at boundary addressable memory (BAM) equipment matched signal comprises:

Input data and the higher limit that is stored in the BAM equipment are compared and generate first output whether expression input data are not less than this higher limit;

Input data and the lower limit that is stored in the BAM equipment are compared and generate second output whether expression input data are not more than this lower limit; And

Export and generate the matched signal whether expression input data are not less than this higher limit and are not more than this lower limit in conjunction with first output and second.

24, a kind of boundary addressable memory (BAM) equipment comprises:

First comparison means is used for input data and the higher limit that is stored in BAM equipment are compared and generate first output whether expression input data are not less than this higher limit;

Second comparison means is used for input data and the lower limit that is stored in BAM equipment are compared and generate second output whether expression input data are not more than this lower limit; And

Coupling apparatus is used in conjunction with first output and second output and generates expression importing the matched signal whether data are not less than this higher limit and are not more than this lower limit.

25, a kind of boundary addressable memory (BAM) equipment comprises:

First comparison means is used for input data and the higher limit that is stored in BAM equipment are compared and generate first output whether expression input data are not more than this higher limit;

Second comparison means is used for input data and the lower limit that is stored in BAM equipment are compared and generate second output whether expression input data are not less than this lower limit; And

Coupling apparatus is used in conjunction with first output and second output and generates expression importing the matched signal whether data are not more than this higher limit and are not less than this lower limit.