CN1147864C

CN1147864C - Static random access memory

Info

Publication number: CN1147864C
Application number: CNB961112573A
Authority: CN
Inventors: 铃木东
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1995-08-31
Filing date: 1996-08-30
Publication date: 2004-04-28
Anticipated expiration: 2016-08-30
Also published as: TW306004B; KR100209542B1; CN1152176A; KR970012763A

Abstract

The invention curtails the total time required for writing, to increase the write margin by utilizing the late write system and to eliminate useless operation time for writing and reading. The memory has an address register which holds the write address in addition to an address register which holds the input address. The selection of address of each of the registers is controlled by a pass gate. The pass gates performs controls so that the readout address is quickly decoded in the readout cycle; the writing cycle passes a delay circuit in the decoding route of the writing address; a decoding route by which the address signal from the register is transferred in the writing cycle earlier by one than the first writing cycle is established at the time when the reading cycle is replaced by a writing cycle.

Description

Semiconductor storage

The present invention relates to semiconductor storage unit.Be particularly related to and synchronously carrying out accessing operation, address decoding system peripherals circuit in the time-delay writing mode that writes data next write cycle after determining to write the address with clock signal.

Figure 12 is synchronized model SRAM (Static Random Access Memory) circuit diagram in the past.Register (address register) 101 is arranged in code translator 100, accepts external timing signal, by the clock signal C K that produces in inside, storage give from the outside with address signal.Even register 102,103 is set similarly, synchronously to export control with clock signal C K for chip select signal/S, write signal/W.For DQ as I/O (input and output of data), be provided with the register 104 of data inputs usefulness and the register 105 of data output usefulness, synchronously transmit separately signal with clock signal C K.Output buffer 109 transmits control by signal/G, prevents the conflict of data.

From input signal/S ,/control circuit 106 of W, produce the signal SWE, the signal SAE of control sensor amplifier, the signal WP of control write transistor that correspondingly control the load circuit of bit line with each mode of write and read.The formation of address register 101 is not only in order to store 1 address signal, and always along with corresponding address selected cell in the register therewith.

Figure 13 is the sequential chart of an example in cycle of showing the read and write of SRAM in the past.And then will read to move to be called and read, write activity be called write.Sense data corresponding to address (Add) A1 that is read (R) by the cycle 1 was read out in the cycle 2, for example obtained at the rising edge in cycle 3 as the output data Q1 of the DQ of corresponding therewith I/O data.In the cycle 5, write.Corresponding address A3 writes data D3.In the cycle 5, write end.

Under the situation that multidigit constitutes,, take the shared mode of I/O of shared inputoutput buffer because inputoutput buffer is many.In this mode, clash in order not make output data Q2 and input data D3, there is the not cycle of assigned address, i.e. the DEAD cycle 4.Moreover, because the DEAD cycle 3 is the data readout intervals of reading the address A2 correspondence in (R) in cycle 2, therefore become the not cycle of assigned address naturally.Similarly, if carry out read and write, then, need the cycle 12 for data D8 is write address A8.

In the shared mode of I/O in the past, need at every turn that to fade to when writing action be the DEAD cycle that prevents data collision from reading to move.Because the DEAD cycle of the waste of this one-period, thereby increased in the overall processing time of storer.

Like this, in the past owing to the DEAD cycle, wasting the dead time in 1 cycle from reading to change to write when moving at every turn, thereby the problem that hinders storer action high speed is being arranged.

The present invention considers problem as described above and proposes that its objective is provides a kind of being implemented in to write and read the synchronized model static random access memory of going up the high speed motion that does not have waste actuation time.

The invention is characterized in, synchronously carry out access action having with clock signal, in the static random access memory (SRAM) of the time-delay writing mode that writes data next write cycle after determining to write the address, have following formation: will with the time kind pulse signal address signal that is taken into synchronously keep the 1st address holding circuit of output; In the address signal in being held in above-mentioned the 1st address holding circuit, will write the 2nd address holding circuit that address signal keeps output with above-mentioned clock pulse signal is taken into synchronously; Selection is stored in the address signal in above-mentioned the 1st address holding circuit and remains in a certain side's of the address signal in above-mentioned the 2nd address holding circuit the 1st changing method; In the switching of readout interval and write cycle, when becoming readout interval from write cycle, setting carries out high-speed coding is worked in coordination with establishment like that with the control of above-mentioned the 1st commutation circuit the 1st path to reading the address, and when readout interval becomes write cycle, in writing address decoding,, control the 2nd changing method of the establishment in this 1st path and the 2nd path through working in coordination with the 2nd path of setting up with the control of above-mentioned the 1st commutation circuit like that time delay.

In the present invention, shortened the T.T. that writes needs, made to write the tolerance limit increase by the 1st, the 2nd changing method utilization time-delay writing mode.And the circuit that also can become the read cycle minimum constitutes.

Fig. 1 is a circuit diagram of showing that the major part of synchronized model SRAM of the time-delay writing mode of example of the present invention constitutes.

Fig. 2 is the circuit diagram that is illustrated in major part of the present invention in a part of circuit of Fig. 1.

Fig. 3 is the 1st signal generating circuit that uses in a part of circuit of Fig. 2.

Fig. 4 is the 2nd signal generating circuit that uses in a part of circuit of Fig. 2.

Fig. 5 is the circuit diagram of instantiation of a part of circuit of exploded view 2.

Fig. 6 is the circuit diagram of the 1st instantiation of the EXNOR gate circuit in the exploded view 5.

Fig. 7 is the circuit diagram of the 2nd instantiation of the EXNOR gate circuit in the exploded view 5.

Fig. 8 is the circuit diagram of the instantiation of the interior address register of the code translator in the exploded view 2.

Fig. 9 is the sequential chart of the synchronized model SRAM of time-delay writing mode.

Figure 10 is illustrated among the SRAM of the SRAM that is suitable for time-delay writing mode of the present invention and mode in the past, the oscillogram that transmits to the data to bit line from word line activating for the access address.

Figure 11 is the sequential chart of problematic time-delay writing mode.

Figure 12 is the circuit diagram of the major part of synchronized model SRAM in the past.

Figure 13 is the sequential chart of an example of showing the read and write cycle of SRAM in the past.

Before explanation the present invention, at first explanation becomes the writing mode that time-delay writes that is called of prerequisite of the present invention.It is the mode of determining to write the address in the previous cycle of input data that so-called time-delay writes.

Fig. 9 is the sequential chart of time-delay writing mode, and is corresponding with the sequential chart of above-mentioned Figure 13.In Fig. 9, reading of the Q2 of I/O data DQ is identical with arranging the time of Figure 13 with writing of D3.For input in the cycle 4 with write data D3 corresponding write address A3, the DEAD cycle can be removed for 1 cycle and data collision is not taken place.Moreover Astr, Dstr among the figure narrate afterwards.So, compare with Figure 13 of mode in the past, the time-delay writing mode finished in the cycles 11, can be than Zao 1 end cycle of mode in the past.

Be exactly to propose as shown in Figure 9 the write cycle that time-delay writes, but under the situation that realizes it, several problems are arranged.In order to get this problem clear, investigate the problem that writes of relevant synchronized model SRAM in the past at this.

Figure 10 is the oscillogram that transmits to the data to bit line for the word line activating of access address in the mode that is illustrated in the past, the

cycle

4,5,6 of exploded view 9.And then, in order more also to have showed the oscillogram of time-delay writing mode of the present invention, but because aftermentioned, thereby do not consider now.

Mode was in a write cycle in the past, and the word line that selection should write makes its activation (SWL3, SWL4), and (D3, D4) is delivered to bit line (BL) with data.At the initial stage in cycle, the un-activation still of the word line in the cycle of front makes correct word line activating midway from the cycle.Represent with T0 this time delay, be the time kind signal CK the address signal determined of rising edge through code translator etc. to determining the needed time of word line.For this reason, just must wait until that to the transmission of the bit line that writes data correct word line is definite.T1 is that (SWL determines) determined in the switching of word line, the potential difference (PD) of paratope line opens to the action tolerance limit for prevent mistake from writing that write of beginning to the unit thus, T2 determines to the activation of the bit line that writes of unit from carrying out, to the simulated action time that finishes (making bit line current potential recovery former state).Thereby, in the cycle that the address is determined, be used to select T0 time delay of word line to can be described as the main cause that makes lengthening write cycle.

Its main points are time-delay writing modes with determining that the front one-period that writes data determines the address, and its address is remained to cycle below crossing over.Following limit is illustrated with reference to the sequential chart limit of the time-delay writing mode of Figure 11.The word line of determining in the cycle 4 that writes address A3 was opened in the cycle 4, and the word line that is kept to address A4 definite during cycle 5 open till (T0).In the cycle 5, the bit line current potential that is written to the data D3 that writes on the A3 of address is determined.As mentioned above, entering 5 o'clock cycles, opening, so can upload the respective signal of sending data D3 at bit line at once because write the word line of address A3.That is, relevant data to bit line transmit, and can not consider T0 time delay.T3 is the preceding time delay of potential difference (PD) of determining complementary bit lines, and T2 is the simulation actuation time that is determined to end (recovery) from the activation of bit line.The share record cycle of not considering T0 time delay shortens.

But if adopt the formation of above-mentioned time-delay writing mode, then the time that writes on the A3 of address is limited in T0-T3.For example, under the fast situation of the action of address decoding, just under the situation that T0 is little, in not with the D3 writing unit, next word line activating (WL 4), the problem that exists mistake to write.In addition, if anti-wrong here and delay that word line is risen strengthens, then read action aspect the cycle is increased.

This problem reason is reading action and writing in the action, and the decoding that word line rises postpones identical.Be conceived to this point, in the present invention, utilize the time-delay writing mode, increase needed T.T. when writing tolerance limit, improve write recovery, and prevent that mistake from writing, and then the read cycle is provided is that minimum circuit constitutes to dwindle to write.

Fig. 1 is the circuit diagram of major part of synchronized model SRAM (Static Random Access Memory) of showing the time-delay writing mode of example of the present invention.Be to have the address register 110 that keeps writing the address with the difference of address register 101 in the code translator of above-mentioned Figure 12.Selection is maintained at the address in the register 101 and is maintained at which of address in the register 110, by 3 controls of highway gate circuit.

When reading to move and 2 that write continuously with interior write cycle (record in the cycle except the initial record) in, along with activation in the signal/SCON side of

highway gate circuit

3,1 unit in specify the address of register 101 in the selection memory cell array 108.Initial record in writing unit is along with the activation of the signal SCON side of

highway gate circuit

3,1 unit in specify the address of register 110 in the select storage unit array 108.

In the time-delay writing mode, last not the writing of write cycle carried out in its cycle, and it writes the address and remains in advance in the register 110, write data in advance and remained in the register 104, if arrive next write cycle, then carries out in the initial cycle.

Read the decoding bus of address and 2 that write continuously switchings with the decoding bus that writes the address in interior write cycle, by 10 controls of highway gate circuit, by highway gate circuit 10 / conducting bus that the WRITE data side produces is the bus in reading to move.This write bus will be passed through delay circuit (4-1,4-2), and the decoding that writes only postpones the retardation of this delay circuit.

Register 110 is by obtaining inner write signal ^*The signal CK of the logic product of W and internal clock pulse signal CK ^*W control.Inner write signal ^*W is the signal from the logic product of the chip select signal/S on top and tracer signal/W, produces from control circuit 7.

Comparer 5 is specified in

register

101 and 110 address when consistent, and along with the activation by the signal FCMP side of highway gate circuit 6, the data in will maintenance register 104 are sent to highway gate circuit 6.This action makes the last partial data that writes of the write cycle that remains in the register 104, and becomes effectively under the situation about being fit in next read cycle.That is, do not wait until to write and from register 104, read the data that should be written into.In the cycle of clock pulse signal CK, keep output from the data of register 104, and deliver to DQ as output data as I/O from the output buffer 109 that transmits control by signal/G with register 105.

Common activation of reading to move along with signal/FCMP one side of highway gate circuit 6, be chosen in the register 101 by 1 unit in the memory cell array 108 of address appointment, in the moment of clock pulse signal CK, in register 105, keep the read data of output from sensor amplifier 107, and the output buffer 109 from transmitting control by signal/G, send to DQ as output data as I/O.

Register 8, with door 9 are control-signals generator of the register 104 that writes for time-delay.That is, when two square signals of input chip select signal/S, write signal/W activate, from the signal of control circuit 7 ^*W becomes " height " level, and at the negative edge of clock signal C K, its " height " level is held output, with door 9 in, at the rising edge of clock signal C K output " height " level, make the data that write in the register 104 keep output.

From input signal/S ,/control circuit 7 of W, produce remaining as inner write signal ^*The inside read signal of the reverse signal of W ^*The signal SWE of the load circuit of the control bit line of the mode of R, corresponding each write and read, control sensor amplifier and write the signal SAE and the signal WP of transistor 107 respectively.

Fig. 2 is the circuit diagram that the example of circuit 120 (circuit of the part that frame rises) is adjusted in the decoding that writes of the time-delay of exploded view 1.

Highway gate circuit

10 and 3 is that same circuit constitutes, and is that the transmission control gate that is connected in parallel is leaked in the source of P ditch MOS transistor and N ditch MOS transistor.To narrating afterwards respectively as the WRITE of control signal and the generative circuit of SCON.Delay circuit 4-1 regulates latching the time to register 110.Delay circuit 4-2 be for address signal through code translator etc. to determine the needed time of word line and select to keep this word line of determining time difference and be provided with.Can consider the various formations that are connected in series etc. of the phase inverter of these delay circuits 4-1,4-2 control threshold value.2 series circuits 43 of the phase inverter that is connected with delay circuit 4-1,4-2 continuation have as the function that drives impact damper.As mentioned above, the decoding bus that writes is compared with the decoding bus of reading, and only delayed circuit 4-1,4-2 postpone the switching of word line.

Above-mentioned register 110 is taken into the address signal (signal of node 51) of delayed circuit 4-1.In Fig. 2, register 110 usefulness 2 latch cicuit L1, L2 formation that is connected in series.Latch cicuit L1 is as follows.Time clock phase inverter IV1 is from the signal of the common gate input node 51 of P ditch MOS transistor 11, N ditch MOS transistor 12.In each grid input of P passage MOS transistor 13, N ditch MOS transistor 14, import the signal CK that narrates previously respectively ^*W and/CK ^*W (signal CK ^*The reverse signal of W), control the output of this phase inverter IV1.Output when time clock phase inverter IV1 is activated, after by phase inverter 25 counter-rotatings, the output that the signal and the homophase of node 51 are exported as time clock phase inverter IV2 is sent to node 52, simultaneously, is input to the common gate of P ditch MOS transistor 21, N ditch MOS transistor 22.Difference input signal/CK on each grid of P ditch MOS transistor 23, N ditch MOS transistor 24 ^*W and CK ^*W controls this phase inverter IV2.

Latch cicuit L2 other and latch cicuit L1 except signal controlling and latch cicuit L1 are opposite are same formations.Time clock phase inverter IV3 is from the signal of the common gate input node 52 of P ditch MOS transistor 11, N ditch MOS transistor 12.On each grid of P ditch MOS transistor 13, N ditch MOS transistor 14, import above-mentioned signal/CK respectively ^*W and CK ^*W controls the output of this phase inverter IV3.Output during time clock phase inverter IV3 effective, reversing by phase inverter 25, when the signal of node 52 and homophase output are sent to node 53 as the output of time clock phase inverter IV4, to the common gate input of P ditch MOS transistor 21, N ditch MOS transistor 22.Difference input signal CK on each grid of P ditch MOS transistor 23, N ditch MOS transistor 24 ^*W reaches/CK ^*W is to control the output of this phase inverter IV2.

If adopt the formation of above-mentioned register 110, if then signal CK*W descends, then in latch cicuit L1, phase inverter IV1 becomes activation, the signal of node 51 is sent to the input node 52 of latch cicuit L2 by phase inverter 25.At this moment, in latch cicuit L2, the non-activation of phase inverter IV3 activates the signal of exporting the cycle node 52 of fronts by phase inverter 25 by phase inverter IV4, transmits to maintain on the node 53.If signal CK*W rises, then in latch cicuit L1,, on the other hand,, thereby keep output to be transferred into the signal of the former node 51 on 52 because IV2 becomes activation because phase inverter IV1 becomes non-activation, thereby has blocked the signal of present node 51.And, because the activation of phase inverter IV3 in latch cicuit L2, thereby the signal of above-mentioned maintained node 52 is sent to node 53 by phase inverter 25.

Fig. 3 is illustrated in the circuit diagram that generates the signal generating circuit of signal WRITE in the highway gate circuit 10 of Fig. 2.For example be the time clock phase inverter IV3 that replaces latch cicuit L2 shown in Figure 2, constitute the circuit diagram of obtaining the time clock NAND gate circuit of logic by many inputs.The activation control of this circuit is clock signal/CK, CK.The NAND gate circuit corresponding with each reverse signal S, the W that latch selection signal/S, write signal/W output becomes and logic output by phase inverter 25, with it as signal WRITE.

In Fig. 3, if clock signal C K rises, then the NAND grid becomes activation, with present corresponding the exporting as signal WRITE with door output of signal S, W.If clock signal C K descends, then present signal S, W are blocked, and will be corresponding with former signal S, W export with door keeps as signal WRITE.

Fig. 4 is a circuit diagram of showing the signal generating circuit of the signal SCON in the highway gate circuit 3 that is created on Fig. 2.Constitute input latch circuit and select the latch cicuit L6 of the reverse signal W of the latch cicuit L5 of the reverse signal S of signal/S, input write signal/W.The formation of two latch cicuit L5, L6, the latch cicuit L2 with Fig. 2 is identical basically.And with the phase inverter 251 of latch cicuit L5 are the relations that are connected in parallel, latch cicuit L6 and output logic are anti-phase.Latch cicuit L5 does counter-rotating output to signal S, and the output " L " (low level) of activation control circuit 60 usefulness latch cicuit L6 constitutes the activation of signal path SP1, constitutes the activation of signal path SP2 with " H " of the output of latching L6 in the electricity.The circuit 65 of 2 series connection of phase inverter has as the function that prevents unsteady usefulness, and the 67th, delay circuit, the circuit 69 of 2 phase inverter series connection has the function that drives with impact damper.

Fig. 4 circuit operation is as follows.When becoming when reading action (signal W for " L ") from writing, highway gate circuit 62 is connected, and highway gate circuit 63 disconnects.Simultaneously, signal S becomes " L " from " H ", and signal SCON becomes " H " at high speed.On the other hand, when from reading to become when writing, highway gate circuit 62 is closed, and highway gate circuit 63 is connected.Simultaneously, signal S becomes " H " from " L ", only postpones the delay time of delay circuit 67, and signal SCON becomes " L ".Like this, signal SCON just becomes when the switching of read and write, makes when reading the address and deciphers at high speed, the control signal of additional delay decoding when making write address.

Fig. 5 is the circuit diagram of the instantiation of the comparer 5 in the exploded view 2.The output of EXNOR door is connected in the grid of N ditch MOS transistor NM.With the N that is input as of address decoding N ditch MOS transistor NM is set with matching.The connected P ditch of source electrode MOS transistor PM between power supply and output branch road has and import the function of pre-electrically conductive signal Pr as activation control usefulness on grid.

Fig. 6 is the circuit diagram of the 1st instantiation of the EXNOR gate circuit in the exploded view 5.Between power supply and earthing potential, be formed with: with P ditch MOS transistor 71,72, the 1st circuit that N ditch MOS transistor 73,74 is connected in series; With with P ditch MOS transistor 75,76, the 2nd circuit that N ditch MOS transistor 77,78 is connected in series.Between transistor 71 and 75 grid, between transistor 72 and 76 grid, between transistor 73 and 77 interpolar, transistor 74 and 78 grid, be connected the input and output of phase inverter 79,80,81,82 respectively.Input IN1 is connected the grid of transistor 71 and 73.Input IN2 is connected the input of phase inverter 83 and the grid of transistor 74.The output of phase inverter 83 is connected the grid of transistor 72.Transistor 72 and 73 tie point and the tie point of transistor 76 and 77 are connected in the input of phase inverter 84 jointly.The output of phase inverter 84 becomes the logic output of EXNOR gate circuit.

Fig. 7 is the circuit diagram of the 2nd instantiation of the EXNOR gate circuit in the exploded view 5.Between power supply and earthing potential, be connected in series P ditch MOS transistor 85, N ditch MOS transistor 86, and grid is connected on the input IN1 jointly.P ditch MOS transistor 87, N ditch MOS transistor 88 are connected in series on the common gate of this

transistor

85,86, common drain.Transistor 87 is connected with input IN2 with 88 common gate.Between this

transistor

87 and 88 common gate, common drain by 89 couplings of highway gate circuit.The P ditch side of highway gate circuit 89 is by input IN1 control.The N ditch side of highway gate circuit 89 is by the common drain output control of transistor 85,86.Transistor 87 is connected with the input of phase inverter 90 with 88 common drain.The output of phase inverter 90 becomes the logic output of EXNOR gate circuit.

Fig. 8 is the circuit diagram of the instantiation of the interior address register 101 of the code translator in the exploded view 2 (or Fig. 1).4 the situation of being input as of showing code translator as basic comprising, is made of 3 circuit identical with above-mentioned circuit shown in Figure 3, its deposit action as with clock signal C K or/CK constitutes synchronously keeping exporting.In each input with 2 IN1, IN2 or IN3, IN4, in the clock gate NAND30 of formation processing logic, 31 the circuit, the additional latch function that is produced by time clock phase inverter IV7, IV8 respectively obtains AND output.Constituting these 2 AND output signal ADIN1, ADIN2 in the circuit of clock gate NAND32 as input, the additional latch function that produces by time clock phase inverter IV9, obtain AND output, it just becomes decoded signal output, is sent in the circuit 120 of Fig. 1.

Below, the circuit operation of the sequential chart key diagram 1 of usefulness Fig. 9.In the cycle 1～3rd, the read cycle, read the data Q1 corresponding, Q2 with address A1, A2.Because the cycle 3 is Input Address not, it is the DEAD cycle therefore.Highway gate circuit 3 is along with the activation that is produced by signal/SCON side, and highway gate circuit 10 is along with the activation that is produced by signal/WRITE side, in specify the address of register 101, and the unit in the selection memory cell array 108.

Cycle the 4, the 5th, write cycle time.In the cycle 4, address A3 is stored in register 101.In the preceding semiperiod in cycle 4, carry out write cycle time last of front along with memory node Astr (address), Dstr (data) and write action.At this moment, highway gate circuit 3 is along with the activation to signal SCON side, the content assigned address of corresponding register 110 sides.Second half in the cycle 4 is interim, and highway gate circuit 3 is along with the activation that is produced by signal/SCON side, and highway gate circuit 10 is selected the unit in the memory cell array corresponding with the address A3 of register 101 appointments 108 along with the activation that signal WRITE side produces.Preceding half in the cycle 5 selects the unit of corresponding address A3 to write data D3.In register 110, store A3, in register 104, store D3.Later half in the cycle 5 is according to address A4 selected cell.The data D4 that carries out to the A4 address in cycle 5 writes, if it is continuous in following one-period to write action, then can carry out in the cycle 6, but because the cycle 6 is read cycles, thereby not carry out writing to the unit.Remain in register 110,104 to next write cycle time, in the initial cycle of next write cycle time, write to the unit of the address of corresponding A 4.

In reading, when reading the data of last r/w cell, as previously mentioned,, therefore read from memory node Dstr owing to do not write to the unit.That is, last write address is maintained at memory node Astr.Detect this Astr with comparer 5 and deny with consistent from the address (output of register 101) of outside input.Under the situation of unanimity, along with the activation that produces by signal FCMP one side of highway gate circuit 6, the data of memory node Dstr are sent to register 105, from the output buffer 109 that activates control by signal/G, read DQ as I/O.

Figure 10 is with the SRAM in the time-delay wiring method of the present invention, by transmitting the more shown oscillogram that goes out of the mode of data and mode in the past for the word line activating of access address to bit line.In synchronized model SRAM in the past, exist word line to select, activate T0 time delay of (SWL); Determine that from SWL the back is to the action tolerance limit T1 for preventing that mistake from writing that begins to write to the unit; And the activation of the bit line that writes to the unit determines, to making the bit line current potential recover T2 time delay of former state.In the initial time that action needs T0+T1+T2 of writing.Need time of T1+T2 at the continuous write cycle time of writing in the action.

In the SRAM of delay recording method of the present invention, with the selection of the address A3 corresponding word lines of determining in the cycle 4, the delay that activation (SW3) has T4, in the later half realization in cycle 4.And in the cycle 5, SWL3 keeps the SWL4 that activates to the A4 correspondence and rises.In the cycle 5, on the address of A3, write data D3.T3 is synchronous with the rising edge of clock signal C K, and write transistor etc. write serial circuit operation, transmits the needed time of data to bit line.In addition, T1, T2 are identical with the situation of above-mentioned SRAM in the past.

Initial write the time that action needs T3+T2.But, as mode in the past, do not need the tolerance limit of T1.At the write cycle time of writing continuously in the action is T1+T2.T4 and bit line are write the time that returns to former level after the action and are equated.Reading in the action of cycle 6, with minimum delay time T0 switching SWL5.This is because SWL4 was not used in this cycle.Write cycle time last write action, promptly, do not write corresponding with write address A4 carried out in this cycle, this write address A4 and write data D4 are maintained at respectively in register shown in Figure 1 110, the register 104, if following one-period arrives, then owing to carry out in its initial cycle, thereby SWL4 had no relations in the cycle 6.

If adopt the SRAM of the time-delay wiring method of above-mentioned formation, then compare with the time T 0-T3 that writes shown in Figure 11 to very short unit, can obtain this write time that writes to the unit really of T2.

If make further high speed cycle length, the relation of T1＜T3＜T0＜T2 is then arranged, the 1st feature of the present invention is to shorten to write needed T.T. of action.The time that shortens is (T0+T1+T2)-(T3+T2)=T0+T1-T3.For example, if consider T0=1.1ms, T1=0.4ms, the situation of T3=0.8ms, then T0+T1-T3=0.7ms.

In addition, if consider the action of reading after the such action of cycle 5 to cycle 6 of Figure 10, then ought make under the situation of high speed cycle length, when SWL5 rises, the recovery of the current potential of bit line BL is insufficient in mode in the past.Therefore, the bitline delays in the read cycle increases, thereby the access time is increased.That is, because the reading action after writing makes low speedization cycle length, thereby in mode in the past, the high speed of action is very difficult.This application as mentioned above, and is compared with the past, writes end owing to can only make at high speed with T0+T1-T3, thereby can obtain the release time of bit line current potential fully.There is not the problem that action recovers of writing in its result.In addition, the time T 2 that writes also increases.Thus, the present invention is relevant with the bit line capacity, and its effect of high capacity and high-speed SRAM is remarkable.

If adopt the present invention as mentioned above, then read action or write all identical this point of action different to the access delay of word line with in the past synchronized model, non-synchronous type SRAM, synchronized model SRAM of the present invention utilizes the time-delay wiring method, the access delay that makes word line in reading is for minimum, access delay to word line is increased, just can make apace thus and write release.Just can provide a kind of thus and can fully carry out the recovery of bit line, the read latency after preventing to write makes and writes the synchronized model static random access memory that tolerance limit increases.

Claims

1. one kind has with clock signal and synchronously memory cell array is carried out access action, sense data in determining to read the readout interval of address signal, in the next write cycle in the cycle of determining to write address signal, write the semiconductor storage of the time-delay writing mode of data, comprising:

At write activity or read in the action, the word line and the bit line that are provided with for the storage unit of selecting in the said memory cells array;

In above-mentioned write activity, determining to select the above-mentioned word line corresponding in the above-mentioned cycle that writes address signal with writing address signal, and the time delay that keeps adding, maintenance selected the state of above-mentioned word line to write the device of above-mentioned data to said memory cells up to definite above-mentioned data in above-mentioned next write cycle and till these data occurring on the above-mentioned bit line;

Read in the action above-mentioned, in determining the above-mentioned readout interval of reading address signal, select the above-mentioned word line corresponding and do not keep the device of above-mentioned additional delay time with reading address signal.

2. one kind has with clock signal and synchronously memory cell array is carried out access action, sense data in determining to read the readout interval of address signal, in the next write cycle in the cycle of determining to write address signal, write the semiconductor storage of the time-delay writing mode of data

Determine in the above-mentioned readout interval to write in above-mentioned timing of reading address signal and above-mentioned write cycle and determine in the cycle before the data that the above-mentioned timing that writes address signal is different, read different with the timing that writes the above-mentioned access action in place.

3. one kind has with clock signal and synchronously memory cell array is carried out access action, sense data in determining to read the readout interval of address signal, in the next write cycle in the cycle of determining to write address signal, write the semiconductor storage of the time-delay writing mode of data, comprising:

Be used for according to above-mentioned read address signal to the said memory cells array carry out access the 1st decoding the path;

Be used for according to above-mentioned write address signal to the said memory cells array carry out access the 2nd decoding the path;

Append to the delay circuit on above-mentioned the 2nd decoding path;

During the previous cycle of first write cycle after above-mentioned readout interval switches to write cycle, be used for according to above-mentioned write address signal to the said memory cells array carry out access the 3rd decoding the path.

4. semiconductor storage according to claim 3 is characterized in that: above-mentioned the 3rd decoding path is identical with above-mentioned the 1st decoding path from the decoding speed that above-mentioned rising edge of clock signal begins.

5. semiconductor storage according to claim 3 is characterized in that: above-mentioned the 3rd decoding path has identical transfer rate with above-mentioned the 2nd decoding path.

6. semiconductor storage according to claim 3, it is characterized in that: the address register that writes address signal that keeps output to determine is contained in above-mentioned the 3rd decoding path in above-mentioned write cycle, in above-mentioned the 3rd decoding path when selected, this address register keeps the address signal that writes exported, and can carry out access to the said memory cells array.

7. semiconductor storage according to claim 3 also comprises:

Keep output and the above-mentioned data register that writes the corresponding data of address signal;

The comparer that address signal compares that writes of reading address signal and the 3rd decoding path to above-mentioned the 1st decoding path;

Have the 1st data routing and the 2nd data routing that sends from the data of above-mentioned data register that send from the data of said memory cells array, control by means of the output signal of above-mentioned comparator circuit, select either party commutation circuit in above-mentioned the 1st data routing and the 2nd data routing

In above-mentioned comparer, above-mentionedly read address signal and write address signal when consistent detecting, from the data of above-mentioned data register as sense data.

8. according to the described semiconductor storage of any one claim in the claim 1 to 3, it is characterized in that: synchronously memory cell array is carried out access action with above-mentioned rising edge of clock signal.

9. according to the described semiconductor storage of any one claim in the claim 1 to 3, it is characterized in that: synchronously memory cell array is carried out access action with above-mentioned rising edge of clock signal and negative edge.

10. one kind has with clock signal and synchronously memory cell array is carried out access action, sense data in determining to read the readout interval of address signal, the time-delay that writes data in the next write cycle in the cycle of determining to write address signal writes the semiconductor storage of originating party formula, comprising:

Synchronously be taken into and keep the 1st register of address signal with clock signal;

Within the address signal in remaining on above-mentioned the 1st register, synchronously be taken into above-mentioned clock signal and keep exporting the 2nd register that writes address signal;

Have and send from the 1st path of the address signal of above-mentioned the 1st register and send the 2nd path that writes address signal, select either party the 1st commutation circuit in above-mentioned the 1st path and the 2nd path from above-mentioned the 2nd register;

Have and be arranged between above-mentioned the 1st register and above-mentioned the 1st path, be directly connected to the 3rd path on above-mentioned the 1st path, with the 4th path that is connected to by delay circuit on above-mentioned the 1st path, select either party the 2nd commutation circuit in above-mentioned the 3rd path and the 4th path;

The control device of above-mentioned the 1st commutation circuit and the 2nd commutation circuit, work becomes to make in readout interval and by above-mentioned the 3rd path and the 1st path the said memory cells array to be carried out access according to reading address signal, in write cycle, by above-mentioned the 4th path and the 1st path the said memory cells array is carried out access according to writing address signal, in the previous cycle of first write cycle after switching to write cycle at readout interval with between write cycle from readout interval, by above-mentioned the 2nd path the said memory cells array is carried out access according to the address signal that writes from above-mentioned the 2nd register.

11. semiconductor storage according to claim 10, it is characterized in that: have the chip select signal of supplying with from the outside and write the permission signal, above-mentioned control device contains the synthetic signal selection control said chip in useful inside and selects signal and write the formation that allows signal.

12. semiconductor storage according to claim 10 is characterized in that: also possess:

Keep output and above-mentioned the 3rd register that writes the corresponding data of address signal;

The comparer of the output of more above-mentioned the 1st register and the 2nd register;

Have and send from the 5th path of the data of said memory cells array and send,, select either party the 3rd commutation circuit in above-mentioned the 5th path and the 6th path by means of the output signal of above-mentioned comparer from the 6th path of the data of above-mentioned the 3rd register,

In above-mentioned comparer, above-mentionedly read address signal and write address signal when consistent detecting, from the data of above-mentioned the 3rd register as sense data.

13. semiconductor storage according to claim 10 is characterized in that: synchronously memory cell array is carried out access action with above-mentioned rising edge of clock signal.

14. semiconductor storage according to claim 10 is characterized in that: synchronously memory cell array is carried out access action with above-mentioned rising edge of clock signal and negative edge.