CN1471180A - Method for preparing high-temperature superconducting material intrinsic junction - Google Patents
Method for preparing high-temperature superconducting material intrinsic junction Download PDFInfo
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- CN1471180A CN1471180A CNA03131922XA CN03131922A CN1471180A CN 1471180 A CN1471180 A CN 1471180A CN A03131922X A CNA03131922X A CN A03131922XA CN 03131922 A CN03131922 A CN 03131922A CN 1471180 A CN1471180 A CN 1471180A
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- mesa structure
- etching
- ion etching
- temperature superconducting
- intrinsic junction
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000463 material Substances 0.000 title claims description 9
- 238000000992 sputter etching Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000009413 insulation Methods 0.000 claims abstract description 3
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 238000002360 preparation method Methods 0.000 claims description 14
- 239000010410 layer Substances 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000002887 superconductor Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 238000002604 ultrasonography Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910004247 CaCu Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000869 ion-assisted deposition Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
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- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
The invented method includes following steps. (1) Manual peeling, (2) metal layer protection, (3) fixation, (4) photo etching graphics, (5) ion etching, (6) insulation protection, (7) ultrasound cleaning, (8) structuring and connecting electrode. In step (5), ion etching with low energy is adopted. In step (8), two top electrodes are structured on mesa structure. The advantages of the invention are as follows. Through fine controlling parameters such as thickness of metal level and etching time etc. the invention realizes primary controlling number of intrinsic junction. The fine controlling number of junction is realized by second time of ion etching and added etching. The invention is suitable to control of number of intrinsic junction for a variety of high temperature super conducting material.
Description
One, technical field
The present invention relates to a kind of high temperature superconducting materia, particularly a kind of preparation method of high temperature superconducting materia intrinsic junction.
Two, background technology
High temperature superconducting materia has obtained extensive studies and attention at material and devices field always since finding.High temperature superconducting materia has very strong anisotropy, and has the natural layer structure that Josephson is coupled along the c direction of principal axis, utilizes this layer structure just can constitute the intrinsic Josephson junction, is called for short intrinsic junction.Intrinsic junction is very important problem in the research of high-temperature superconductor knot, and it has a lot of potential using values such as high frequency, high power oscillation source, high-frequency signal detection and voltage reference.Because Bi
2Sr
2CaCu
2O
8+x(BSCCO) the monocrystalline intrinsic junction has very high stability and consistency, so BSCCO is a material the most frequently used in the intrinsic junction research field.
High temperature superconducting materia intrinsic junction technology of preparing mainly comprises two classes at present: traditional technology of preparing [L.X.You based on mesa structure, P.H.Wu, W.X.Cai, S.Z.Yang, H.B.Wang and L.Kang, Chinese ScienceBulletin 48 (2003), and 24] and double-side technology technology of preparing [H.B.Wang, J.Chen, L.X.You, P.H.Wu andT.Yamashita, IEICE Trans.Electron.E85-C (2002), 691].The former is widely used preparation means, and it realizes simple, and controls the number of knot easily; The double-side technology technology of preparing is a recent development technology, and this technology has been removed the single crystal substrates of bulk by process means, thus the influence of avoiding single crystal substrates that knot is used, but this technology is comparatively complicated, can't effectively control the number of knot.
For the control of intrinsic junction number, a few thing report is arranged also at present.Many knot series connection aspect, people such as Wang Huabing utilize two-sided knot process means to realize two-dimentional intrinsic junction knot battle array, thereby have obtained the nearly series connection [H.B.Wang of 11500 knots, K.Maeda, J.Chen, P.H.Wu and T.Yamashita, Physica C372 (2002), 327].The intrinsic junction that contains the minority knot prepares the aspect also some reports, but repeatability is not high, and best result has only realized 4～5 knots of reliable preparation [A.Yurgens, D.Winkler, N.V.Zavaritsky and T.Claeson, Phys.Rev.B53 (1996), R8887].
Three, summary of the invention
1, goal of the invention: the purpose of this invention is to provide a kind of method of utilizing traditional mesa structure to prepare the high temperature superconducting materia intrinsic junction, utilize this method can realize containing any footing purpose intrinsic junction.
2, technical scheme: intrinsic junction preparation method of the present invention is:
(1) separate little superconduction thin slice from bulk superconductive monocrystal material, can adopt usually that instrument such as adhesive tape is auxiliary to be finished, the size of thin slice is generally 2mm * 2mm * 0.1mm.
(2) on the unsalted surface of the superconduction thin slice that separates, deposit the layer of metal protective layer at once, protective layer can be silver or gold as protective layer, the mode of thermal evaporation or ion assisted deposition is adopted in the growth of metal level usually.
(3) with being fixed on the substrate by the monocrystalline thin slice of plated metal protective layer of small pieces, and baking is reinforced about 100 degree, makes it possible to utilize planar technique to realize further preparation.
(4) form the mesa structure figure of needs by photoetching process on the surface of monocrystalline thin slice, its area size can be according to our requirement decision.
(5) adopt ion energy less than 300 electron-volts low energy ion etching, construct mesa structure on the monocrystalline thin slice, etch rate is the thickness of per minute etch thicknesses smaller or equal to single intrinsic junction, and the time of etching is by the height and the speed decision of table top.Because the height of table top can be by the time and the speed decision of etching, therefore, the number of the knot that is comprised in the mesa structure is also determined with regard to process thus.
What mesa structure intrinsic junction preparation method adopted usually is energetic ion lithographic technique (the ion etching energy is greater than 500 electron-volts), and metal layer thickness do not done requirement, this makes that etch rate is very high on the one hand, the actual etch period of monocrystalline can't accurately be determined on the other hand, and therefore the number of knot is uncontrollable.Controlled in order to realize the footing purpose, the present invention has adopted low energy ion etching (ion energy is less than 300 electron-volts), and the etch rate of superconductor has been reduced an order of magnitude, its per minute etch thicknesses is reached even less than the thickness of single intrinsic junction.The footing order can be controlled by etch period fully like this.Simultaneously, the present invention has accurately measured metal layer thickness, according to the etch rate of metal level correspondence, can obtain to be used in the ion etching time of etching superconductor accurately.Thereby calculate the number of knot.
(6) after ion etching process finishes, evaporate one deck insulating material at once mesa structure is carried out insulation protection, be short-circuited to avoid the intrinsic junction in the mesa structure and the single crystal substrates of mesa structure.Usually the insulating material that adopts is calcirm-fluoride or silica.
(7) sample is carried out ultrasonic cleaning, with the photoresist at removal mesa structure top and the insulating layer material on the photoresist.
(8) because the smaller directly line of mesa structure area, so we will adopt further step, distinguish extraction electrode from mesa structure top and bottom.When the 5th went on foot ion etching, we adopted the low energy ion etching, make etch rate enough low, the preliminary control that realization finishes number, and footing purpose departure is ± 1.In order to realize that the footing purpose is accurately controlled, the principle that we measure with reference to four terminals, two top electrodes of structure on mesa structure.The ion etching time to the structure electrode is further controlled.Can further reduce the number of effectively tying in the mesa structure like this so that the part knot is contained in the lead resistance of four terminals measurement in the mesa structure like this.And realize further the number of knot being controlled.Because such preparation process can also adopt the method for adding etching, therefore, the present invention can suitably loosen the requirement of footing purpose when Preliminary design.Such as needs footing order is N when knot, and we at first realize containing the mesa structure of the individual knot of N+M (M is optional, gets 3 or 4 usually), during ion etching for the second time, carries out etch period according to M+1 knot and controls then.The result is measured, if number can adopt the method for adding etching, till the footing order reaches requirement more than N.Accurate control with regard to realizing finishing number like this.Utilize this method to prepare and contain the intrinsic junction that any minority order is tied.The intrinsic junction that only contains single knot also can easily obtain.
3, beneficial effect: the present invention compared with prior art, its remarkable advantage is: adopt the low energy ion etching, by parameters such as accurate control metal layer thickness, etch periods, realized intrinsic junction footing purpose is tentatively controlled, and further utilize ion etching for the second time and adopt the method for adding etching, realized the footing purpose is accurately controlled.This method is applicable to various high temperature superconducting materia intrinsic junction footing purpose controls.
Four, description of drawings
Fig. 1 is a mesa structure intrinsic junction sample preparation schematic diagram.Wherein (I) is the structure graph after (4); (II) be structure graph after (5); (III) be structure graph after (6); (IV) be structure graph after (7).
Fig. 2 is controlled footing order mesa structure intrinsic junction structural representation.
Fig. 3 (a) is the electronic transport feature measurement curve chart of 4 knots.
Fig. 3 (b) is the electronic transport feature measurement curve chart of 3 knots.
Five, embodiment
1, adopts Bi
2Sr
2CaCu
2O
8+x(BSCCO) as high temperature superconducting materia, the thickness of its single intrinsic junction is 1.54 nanometers, and metal layer material adopts silver, and insulating layer material adopts calcirm-fluoride.
2, the ion etching energy of Cai Yonging is 250 electron-volts, etching speed (the destroyed superconducting layer thickness d under the corresponding etching condition that sees the following form
VtBe 2.7 nanometers).As a comparison, provide etch rate under 1000 electron-volts simultaneously.
| Ion energy | Beam current density | ???ER Bi | ???ER Ag | ??ER Au | |
| The high energy etching | ??1000eV | ??0.76mA/cm 2 | ???18nm/min | ???76nm/min | ??54nm/min |
| The low energy etching | ??250eV | ??0.38mA/cm 2 | ???1.3nm/min | ???9.3nm/min | ??6.3nm/min |
ER
Bi, ER
AgAnd ER
AuRepresent BSCCO, silver and golden etch rate respectively
Intrinsic junction that contains three knots of design structure of the present invention.In the experiment, the thickness of ground floor silverskin is 56 nanometers, and the ion etching time is 12 minutes for the first time, and the number of tying in the mesa structure of acquisition is 7, and the result is Duoed one than expectation.In order to obtain to contain the intrinsic junction of three knots, need make have 4 knots to be separated in the mesa structure by ion etching, thereby be included in the contact resistance by ion etching.For this reason, at first relax the requirement to the knot number, design has 3 knots to be separated by ion etching.Silver film thickness is 104 nanometers for the second time, and the ion etching time is 19 minutes for the second time, carries out the electronic transport feature measurement for the sample of testing acquisition and the results are shown in Figure 3, and empirical curve shows that the number of the knot of acquisition is 4, Duos one than the footing order of needs.Therefore, can add 1 minute etching to sample, the sample electronic transport characteristic of adding after the etching is seen Fig. 4, and the number of knot has reached our designing requirement.
Claims (5)
1, a kind of preparation method of high temperature superconducting materia intrinsic junction may further comprise the steps:
(1) separates little superconduction thin slice from bulk superconductive monocrystal material;
(2) on the unsalted surface of the superconduction thin slice that separates, deposit layer of metal at once;
(3) being fixed on the substrate small pieces by the monocrystalline thin slice of plated metal protective layer;
(4) on the surface of monocrystalline thin slice, form the mesa structure figure of needs by photoetching process;
(5) carry out ion etching, on the monocrystalline thin slice, construct mesa structure;
(6) ion etching process is evaporated one deck insulating material at once mesa structure is carried out insulation protection after finishing;
(7) sample is carried out ultrasonic cleaning, with the photoresist at removal mesa structure top and the insulating layer material on the photoresist;
(8) electrode structure be connected;
It is characterized in that:
In (5), adopt ion energy less than 300 electron-volts low energy ion etching, etch rate is the thickness of per minute etch thicknesses smaller or equal to single intrinsic junction, the time of etching is by the height and the speed decision of table top;
In (8), two top electrodes of structure carry out ion etching second time on mesa structure, make part knot in the mesa structure be contained in the lead resistance that four terminals measure, and reduce the number of effectively tying in the mesa structure.
2, the preparation method of high temperature superconducting materia intrinsic junction according to claim 1, it is characterized in that: when needs footing order was N knot, etching realized containing the mesa structure of N+M knot for the first time, during ion etching for the second time, carry out etch period control (N, M are natural number) according to M+1 knot.
3, the preparation method of high temperature superconducting materia intrinsic junction according to claim 2 is characterized in that: M is 3 or 4.
4, according to the preparation method of claim 2 or 3 described high temperature superconducting materia intrinsic junctions, it is characterized in that: if the footing order during more than N, adopts the method for adding etching, till the footing order requires.
5, the preparation method of high temperature superconducting materia intrinsic junction according to claim 1, the time that it is characterized in that (5) intermediate ion etching comprises to the etch period of metal level with to the etch period of superconductor.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB03131922XA CN100346491C (en) | 2003-06-18 | 2003-06-18 | Method for preparing high-temperature superconducting material intrinsic junction |
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| CNB03131922XA CN100346491C (en) | 2003-06-18 | 2003-06-18 | Method for preparing high-temperature superconducting material intrinsic junction |
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| CN1471180A true CN1471180A (en) | 2004-01-28 |
| CN100346491C CN100346491C (en) | 2007-10-31 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101820046A (en) * | 2010-04-09 | 2010-09-01 | 中国科学院上海微系统与信息技术研究所 | Method for preparing superconductive intrinsic junction |
| CN101868127B (en) * | 2009-11-24 | 2012-11-07 | 清华大学 | Preparation process of superconductive planar circuit |
| CN105576115A (en) * | 2015-12-24 | 2016-05-11 | 南京大学 | Fabrication method of double-sided junction and high-temperature super-conduction Bi<2>Sr<2>CaCu<2>O<8+Delta> (BSCCO) terahertz source |
| CN105742478A (en) * | 2016-03-17 | 2016-07-06 | 南京大学 | Fabrication method of iron-based single-crystal super-conduction microbridge |
| CN109626323A (en) * | 2009-02-27 | 2019-04-16 | D-波系统公司 | Superconducting integrated circuit |
| US11856871B2 (en) | 2018-11-13 | 2023-12-26 | D-Wave Systems Inc. | Quantum processors |
| US11930721B2 (en) | 2012-03-08 | 2024-03-12 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| US11957065B2 (en) | 2017-02-01 | 2024-04-09 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4432134A (en) * | 1982-05-10 | 1984-02-21 | Rockwell International Corporation | Process for in-situ formation of niobium-insulator-niobium Josephson tunnel junction devices |
| JPH0974231A (en) * | 1995-09-07 | 1997-03-18 | Nippon Telegr & Teleph Corp <Ntt> | Superconductive three terminal element |
| CN1111314C (en) * | 1996-10-31 | 2003-06-11 | 南开大学 | High temperature super conductive film substrate step intrinsic Josephson junction array and its preparing method |
| JPH1126822A (en) * | 1997-07-02 | 1999-01-29 | Oki Electric Ind Co Ltd | High temperature superconduction josephson element and its manufacture |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109626323A (en) * | 2009-02-27 | 2019-04-16 | D-波系统公司 | Superconducting integrated circuit |
| CN109626323B (en) * | 2009-02-27 | 2020-12-01 | D-波系统公司 | Superconducting integrated circuit |
| CN101868127B (en) * | 2009-11-24 | 2012-11-07 | 清华大学 | Preparation process of superconductive planar circuit |
| CN101820046A (en) * | 2010-04-09 | 2010-09-01 | 中国科学院上海微系统与信息技术研究所 | Method for preparing superconductive intrinsic junction |
| CN101820046B (en) * | 2010-04-09 | 2013-05-22 | 中国科学院上海微系统与信息技术研究所 | Method for preparing superconductive intrinsic junction |
| US11930721B2 (en) | 2012-03-08 | 2024-03-12 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| CN105576115A (en) * | 2015-12-24 | 2016-05-11 | 南京大学 | Fabrication method of double-sided junction and high-temperature super-conduction Bi<2>Sr<2>CaCu<2>O<8+Delta> (BSCCO) terahertz source |
| CN105576115B (en) * | 2015-12-24 | 2018-04-17 | 南京大学 | A kind of preparation method of two-sided knot high-temperature superconductor BSCCO THz sources |
| CN105742478A (en) * | 2016-03-17 | 2016-07-06 | 南京大学 | Fabrication method of iron-based single-crystal super-conduction microbridge |
| CN105742478B (en) * | 2016-03-17 | 2018-06-26 | 南京大学 | A kind of preparation method of iron-based monocrystalline superconducting microbridge |
| US11957065B2 (en) | 2017-02-01 | 2024-04-09 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| US11856871B2 (en) | 2018-11-13 | 2023-12-26 | D-Wave Systems Inc. | Quantum processors |
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| CN100346491C (en) | 2007-10-31 |
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