CN1467827A - Improved mask ROM process and element - Google Patents

Improved mask ROM process and element Download PDF

Info

Publication number
CN1467827A
CN1467827A CNA021605068A CN02160506A CN1467827A CN 1467827 A CN1467827 A CN 1467827A CN A021605068 A CNA021605068 A CN A021605068A CN 02160506 A CN02160506 A CN 02160506A CN 1467827 A CN1467827 A CN 1467827A
Authority
CN
China
Prior art keywords
region
channel region
pocket
implantation
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA021605068A
Other languages
Chinese (zh)
Other versions
CN1225782C (en
Inventor
1
陈国庆
李若加
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CNB021605068A priority Critical patent/CN1225782C/en
Priority to US10/391,537 priority patent/US6940135B2/en
Publication of CN1467827A publication Critical patent/CN1467827A/en
Application granted granted Critical
Publication of CN1225782C publication Critical patent/CN1225782C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a process for making integrated circuit elements of masking type read-only memory comprising, carrying out a implanting process to form a wellblock on the semiconductor substrate, and forming a plurality of embedded implanting area through the first pattern type light shield, each of the embedded implanting area includes a source electrode area and drain area of the individual memory element area, which belongs to one of the plurality of memory elements. The invention can also be used to form pocket areas in the embedded implanting area of the individual memory element area.

Description

Modified form mask ROM technology and element
Technical field
The present invention is relevant for integrated circuit and the technology made at semiconductor element thereof.More specifically, the invention provides a kind of method of making mask ROM, can dwindle its critical dimension, and effectively exempt punch-through effect.But range of application of the present invention is real more extensive than this.For example, the present invention can be applicable to design and other aspects of embedded read-only memory.
Background technology
From a small amount of Connection Element of manufacturing on silicon wafer originally, evolution is to millions of the elements of today for integrated circuit.Performance that the tradition integrated circuit is provided and complexity far surpass the imagination originally.In order to improve complexity and current densities (meaning is the component number that can hold on each wafer), there is the smallest elements size of the title of element " geometry " to heal and becomes mini along with integrated circuit evolution from generation to generation.
Increase current densities and not only improved the complexity and the performance of integrated circuit, also provide low-cost part simultaneously for the consumer.A machine of producing integrated circuit or wafer is expensive several hundred million easily, even multi-million dollar.Every machine can the production some wafer, and can hold the integrated circuit of some on every wafer.Therefore, if can allow the individual elements of each integrated circuit dwindle, just can make more element on every wafer, thereby increase the output of this machine.Element be dwindled is a very big challenge, because each integrated circuit technology all has its restriction.In other words, certain special process only is applicable to certain size usually, otherwise just must the whole technology of change or the configuration of element.
Integrated circuit component has numerous species, comprises memory, specific function integrated circuit component, microprocessor element etc.Then comprise read-only memory in the memory as ROMs.Read-only memory is divided into a mask ROM and an oxidation read-only memory again.Along with component size is dwindled day by day, mask ROM also faces various restrictions.For example, mask ROM has the problem of puncture, and promptly a memory cell can provide wrong memory cell state information on interpretoscope.In other words, this memory cell can export 1 but not therefore 0 state causes improper output.Component size is more little, and such problem is just serious more.The starting voltage of memory cell descends, and causes the improper of this memory cell to read.Traditional read-only memory integrated circuit element often exists this class and other restrictions.
In view of this, the treatment technology of improvement semiconductor element has its necessity in fact.
Summary of the invention
The present invention will provide the technology of making method for semiconductor element that comprises.Particularly, the invention provides a kind of method of making mask ROM, can dwindle its critical dimension, and effectively exempt punch-through effect.But range of application of the present invention is real more extensive than this.For example, the present invention can be applicable to design and other aspects of embedded read-only memory.In specific embodiment, the invention provides a kind of method of making the mask ROM integrated circuit component, can reduce the puncture influence between source area and the drain region, because the formula that the latter can make the mistake is read.This method comprises utilizes implantation technology to form a plurality of wellblocks on the semiconductor-based end, and forms a plurality of buried types implantation region through first patterning light shield.First patterning light shield is to form above the semiconductor-based end.Each buried type implantation region comprises a source area and the drain region on indivedual memory cells zone.These memory cell zones are in respect of a plurality of.This method forms pocket region near also being included in buried type implantation region in the channel region in each memory cell zone.First pocket region is defined as between channel region and source area.Second pocket region is then between the drain region on channel region and each the memory cell zone.This method comprises that utilizing implantation is that the one or more routing districts of selecting writes formula, to finish the sequencing that one or more selects fixed memory cell zone.
In another embodiment, the invention provides a kind of method of making integrated circuit component, critical dimension can be reduced into less than 0.35 micron from about 0.35 micron comprising a method for designing, use reduction and can cause mask ROM to do the punch-through effect that improper program reads.This method for designing comprises utilizes implantation to form several wellblocks on the semiconductor pedestal, and forms a plurality of buried types implantation region through first patterning reticle field, with source area between the channel region that defines each memory cell zone and drain region.This method also the buried type implantation region in the channel region in each memory cell zone near the formation pocket region.This pocket region possesses the assorted relatively value characteristic of buried type implantation region.This method is the one or more routing district codings of selecting, to finish the sequencing that one or more selects fixed memory cell zone.The purpose of this pocket region is for one in the channel region that reduces by or above memory cell zone or above source area and the punch-through effect between the drain region.
In another embodiment, the invention provides a mask ROM integrated circuit component.This element comprises a semiconductor pedestal, wellblock that forms and a source area that links to each other with the drain region on the semiconductor pedestal; This source area and drain region all possess the characteristic of first kind of assorted value.Channel region is defined as between source area and drain region.First pocket region is defined as between channel region and source area.Second pocket region is defined as between channel region and drain region.The character line is defined as the channel region top.This element has an inner layer dielectric layer above the character line, a metal interconnecting layer is then arranged above this dielectric layer.First and second pocket region all belong to second kind of assorted value characteristic, promptly with respect to first kind of assorted characteristic that is worth.First pocket region and second pocket region make source area interfere mutually in the working voltage drain region of not making peace during less than starting voltage.
The present invention and conventional art have been compared plurality of advantages.For example, the invention provides a kind of based on conventional art, easy-to-use technology.In certain embodiments, this method allows and is partitioned into more polycrystalline grain on every wafer, thereby reaches higher element yield (device yields in dies per wafer).Therefore, the technology that this method provides can be compatible with conventional process techniques, and need not significantly to revise legacy equipment and technology.The present invention also provides the modified form mask ROM that is not subjected to the traditional element restriction.Different embodiment can reach different advantages.Above-mentioned and other advantage of the present invention will in the present invention explanation and below do more detailed description.
Following elaborate and will help that with accompanying drawing other purposes of the present invention, feature and advantage are had understanding more fully.
Description of drawings
Fig. 1 has shown the vertical view of a mask ROM memory cell design in the embodiments of the invention;
Fig. 2 has shown the sectional view of a mask ROM in the embodiments of the invention;
Fig. 3 has shown the memory cell circuit diagram of mask ROM in the embodiments of the invention;
Fig. 4-7 has shown in the embodiments of the invention, makes the method for mask ROM.
Embodiment
The invention provides the technology of making method for semiconductor element that comprises.More specifically, the invention provides a kind of method of making mask ROM, can dwindle its critical dimension, and effectively exempt punch-through effect.But range of application of the present invention is real more extensive than this.For example, the present invention can be applicable to design and other aspects of embedded read-only memory.
Fig. 1 has shown the Figure 100 that overlooks of a mask ROM memory cell design in the embodiments of the invention.This figure only is for example, does not use to limit the present patent application scope.Anyly be familiar with present technique field person and all understand the present invention and can do many other variations, change and application.As shown in the figure, this vertical view comprises a plurality of polysilicon conductors 107, and each conductor is all a memory cell 101 definition one character line.Demonstration source/drain region or active region 105 among the figure.This active region comprises the buried regions that an impurity concentration is higher.In the present embodiment, this buried regions comprises as boron family and other N+ type impurity.As scheme to show that a passage implants 109.These passages are implanted can be at certain memory born of the same parents coding.Through the memory cell of sequencing exportable as " 1 " and logic state.Otherwise, without the memory cell of sequencing then can export " 0 ".Relevant more details of the present invention will be introduced below the present invention's explanation reaches.
Fig. 2 has shown the sectional view of a mask ROM 200 in the embodiments of the invention.This figure only for for example, does not use to limit the present patent application scope.Anyly be familiar with present technique field person and all understand the present invention and can do many other variations, change and application.In addition, identical with other accompanying drawing, the part reference number only supplies the usefulness of cross reference among the figure.200 sectional views are at the single memory cell in the array.This memory cell comprises the substrate 205 that contains the wellblock.This substrate belongs to p type impurity usually, but also may belong to other kinds impurity.This wellblock belongs to p type impurity equally.Polysilicon layer 107 is to form above this substrate surface.As figure and demonstration source/drain region 103.Then form a pocket region 203 between buried regions and the channel region, implant comprising the passage in the present embodiment.201 of another pocket region form between buried regions and channel region.These two pocket region interact between channel region and buried regions separately, prevent to produce punch-through effect between source area and the drain region.
Present embodiment provides multiple parameter.Pocket region mainly is to utilize counter ion to implant the p type impurity that forms.It is with boron or boron fluoride and so on for it that counter ion is implanted.Its implant concentration is usually between 5 * 1011 to 5 * 1013atoms/cm2, but other dosage also can.Used energy arrives 100keV between 25keV usually, but other magnitudes of voltage also can.Usually counter ion is implanted and can be implanted technology by use angle.But decide on practical situations, other technology that are fit to also can.
Fig. 3 has shown the memory cell circuit diagram 300 of mask ROM in the embodiments of the invention.This figure only for for example, does not use to limit the present patent application scope.Anyly be familiar with present technique field person and all understand the present invention and can do many other variations, change and application.This figure comprises a plurality of memory cells.Each memory cell all contains a transistor unit, stores " 1 " or " 0 " signal by implantation.Each memory cell all links to each other with a bit line with a character line, and the bit line links to each other with sense amplifier.The structure of buried type implantation region definition bit line.Relevant more details of the present invention will be illustrated in the following manner.
Embodiments of the invention can be summarized as follows:
1. substrate is provided;
2. formation wellblock;
3. forming buried type N+ implants;
4. form counter-doping in pocket region and implant, with the definition source area;
5. selection portion divides the channel region of memory array to form the coding implantation;
6. above substrate, form character line polysilicon layer;
7. character line polysilicon layer is carried out patterning;
8. formation inner layer dielectric layer;
9. formation contact zone;
10. formation metal wire;
11. above metal level, form protective layer; And
12. implement other steps necessarys.
More than each step enforcement a kind of method of the embodiment of the invention is provided in proper order.This method utilization is carried out counter-doping in pocket region and is implanted and avoid the punch-through effect that produces between the source area and drain region in the channel region.These punch-through effects can cause improper program to read, and other restrictions.These restrictions and other steps all the present invention explanation and below detailed description is arranged.
Fig. 4 to Fig. 7 has shown in the embodiments of the invention, makes the method for mask ROM.These accompanying drawings only are for example, do not use to limit the present patent application scope.Anyly be familiar with present technique field person and all understand the present invention and can do many other variations, change and application.This method at first provides a substrate 401, and its surface, top is 403.This substrate can be the semiconductor-based end of picture Silicon Wafer and so on.Silicon base material belongs to the P type usually, and concentration then is 10 14-10 16Atom/cm 3, but other possibilities are also arranged.
As shown in Figure 5, mask layer 501 forms above substrate surface 403.Utilize traditional lithography process to finish the patterning of this mask layer then.This method is included in buried regions 503 and implants, and forms the bit line structure.Implantation rule employing boron or boron fluoride or other elements carry out cloth and plant.When channel region was the 0.01-0.10 micron, the degree of depth of buried layer was the 0.1-0.50 micron usually.Pocket region 505 is to implant technology 506 by angle to form.It then is to utilize between 10 degree to the angle 601 between 30 degree to finish that angle is implanted, but angle there is no certain limitation.Pocket region 505 forms a p type impurity profile in substrate.These impurity profiles can prevent to produce punch-through effect between the buried type implantation region.For raising the efficiency cause, pocket region forms as buried regions when mask step.
The step that this method selection portion divides the memory cell zone to carry out programming is to finish the sequencing of a series of memory components.At this, light shield can memory cell zone, cover part.All the other zones then keep not having the state that light shield covers.These no Lacquer finish cover areas of coverage then utilize impurity 701 to carry out cloth to plant, this memory cell is encoded to 703, as shown in Figure 7.Implantation region 703 interconnects source area and drain region, allows signal be able to transmit between Liang Qu.This method forms a character line polysilicon layer above the subregion of substrate.These polysilicon series of strata are come patterning in addition with traditional light shield and etching technique.Above this polysilicon layer, then form one or more inner layer dielectric layers.According to this method, in this dielectric layer, will form the contact zone.Then, the metal (for example aluminium) of this method utilization above contact layer forms intraconnections.Above these intraconnections, then form the protective layer of forming by oxide usually, and the mononitride layer.According to different embodiment, this method can include other steps necessarys.
Example as herein described and embodiment only are for example, thus anyly be familiar with present technique field person when can doing a little retouching or change, and these retouchings or change should be included in spirit of the present invention and the scope, and belong within the accompanying claim.

Claims (20)

1, a kind of method of making the mask ROM integrated circuit component can reduce the punch-through effect that can cause program to misread between source area and the channel region, comprises the following step:
Implement an implantation technology and on the semiconductor-based end, form the wellblock;
Form a plurality of buried types implantation region by first patterning light shield; First patterning light shield is formed at top, the semiconductor-based end, comprises a source area and a drain region then is formed between the channel region in indivedual memory cells zone in interior buried type implantation region; Total a plurality of memory cells zone;
Form pocket region near the buried type implantation region in the channel region in each memory cell zone, be defined as between channel region and source area comprising first pocket region, and second pocket region is defined as between the channel region and drain region in each memory cell zone; And
Implementing implantation is part channel region coding, to finish the sequencing in part memory cell zone.
2, the method for claim 1 is characterized in that, the part channel region is to be selected by a single light shield technology to decide.
3, the method for claim 1 is characterized in that, pocket region is when same light shield technology, is defined as the buried type implantation region according to the opposite admixture with respect to the buried type implantation region.
4, as the described method of claim l, it is characterized in that, implement boron or boron fluoride implanting ions, form pocket region.It is with respect to about 20 to 30 degree of substrate surface that the planting of this implantation technology enters the firing angle degree, and implant concentration is between 5E11 to 5E13atoms/cm2, use energy then 15 to 100keV.
5, the method for claim 1 is characterized in that, each channel region is about 0.3 micron, even littler.
6, the method for claim 1 is characterized in that, pocket region can reduce the punch-through effect in the channel region between the source/drain region in memory cell zone.
7, the method for claim 1 is characterized in that the wellblock belongs to P-type material.
8, the method for claim 1 is characterized in that, substrate belongs to the material of P type feature.
9, the method for claim 1 is characterized in that, the used implant concentration in buried type implantation region is between 1E15 to 2E15atoms/cm2, and used energy then is 20 to 60keV.
10, method as claimed in claim 9 is characterized in that, the buried type implantation region comprises phosphorus or arsenic atom.
11, a kind of method of making integrated circuit component, critical dimension can be contracted to below 0.35 micron from 0.35 micron comprising a kind of method for designing, can cause the mask ROM element to misread the punch-through effect of program with reduction, this method comprises the following step:
Implement one and implant technology on the semiconductor-based end, to form several wellblocks;
See through first patterning light shield and form a plurality of buried types implantation region, with a source area and the drain region between the channel region that defines each memory cell zone;
Form several pocket region near the buried type implantation region in the channel region in each memory cell zone, this pocket region belongs to the relative doping property in buried type implantation region; And
Be the part channel region coding in indivedual memory cell zones, to finish the sequencing in or above memory cell zone;
Those pocket region can reduce the punch-through effect that produces between the source area of channel region in indivedual memory cells zone and the drain region.
12, method as claimed in claim 11 is characterized in that, the part channel region is to select via a light shield technology to decide.
13, method as claimed in claim 11 is characterized in that, pocket region is defined by the admixture relative with the buried type implantation region.
14, method as claimed in claim 11, it is characterized in that, pocket region is to utilize the implantation technology that boron or boron fluoride carry out and form, planting of this implantation technology enters firing angle with respect to substrate surface 20 to 30 degree, this implantation technology institute using dosage is 5E11 to 5E13atoms/cm2, used energy then between 15 to 100keV.
15, method as claimed in claim 11 is characterized in that, each channel region is about 0.30 micron, even littler.
16, method as claimed in claim 11 is characterized in that, the wellblock is a P-type material.
17, method as claimed in claim 11 is characterized in that, substrate is a P type feature material.
18, method as claimed in claim 11, wherein, the buried type implantation region is to utilize implant dosage 1E15 to 2E15 atoms/cm2, and uses energy 20 to 60keV and form.
19, method as claimed in claim 19 is characterized in that, the buried type implantation region comprises phosphorus or arsenic atom.
20, a mask ROM integrated circuit component, this element comprises:
The semiconductor substrate;
One wellblock that on the semiconductor-based end, forms;
A source area and a drain region that comprises second buried regions that comprises first buried regions, this source area links to each other with the drain region, and belongs to first kind of doping property together;
One is defined as the channel region between this source area and this drain region;
One is defined as first pocket region between channel region and source area;
One is defined as second pocket region between channel region and drain region;
One is defined in the character line of channel region top;
One is positioned at the inner layer dielectric layer of this character line top; And
One is positioned at the metal interconnecting layer of this inner layer dielectric layer top;
First and second pocket region is to belong to second kind of impurity, and second kind of impurity is and first kind of type that impurity is relative, and first and second pocket region allows source area when the buried regions applied voltage is lower than starting voltage, and interfere mutually unlikely and drain region.
CNB021605068A 2002-12-27 2002-12-27 Improved mask ROM process and element Expired - Lifetime CN1225782C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CNB021605068A CN1225782C (en) 2002-12-27 2002-12-27 Improved mask ROM process and element
US10/391,537 US6940135B2 (en) 2002-12-27 2003-03-17 Mask-ROM process and device to prevent punch through using a halo implant process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB021605068A CN1225782C (en) 2002-12-27 2002-12-27 Improved mask ROM process and element

Publications (2)

Publication Number Publication Date
CN1467827A true CN1467827A (en) 2004-01-14
CN1225782C CN1225782C (en) 2005-11-02

Family

ID=29784846

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021605068A Expired - Lifetime CN1225782C (en) 2002-12-27 2002-12-27 Improved mask ROM process and element

Country Status (2)

Country Link
US (1) US6940135B2 (en)
CN (1) CN1225782C (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1309053C (en) * 2004-03-26 2007-04-04 力晶半导体股份有限公司 Method for producing flash storing device
WO2016119477A1 (en) * 2015-01-29 2016-08-04 无锡华润上华半导体有限公司 Preparation method for flat cell rom device
CN110060724A (en) * 2019-04-09 2019-07-26 江苏东海半导体科技有限公司 A kind of reading out structure of exposure mask memory

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781867B2 (en) * 2002-07-11 2004-08-24 Micron Technology, Inc. Embedded ROM device using substrate leakage
KR100890613B1 (en) * 2007-01-26 2009-03-27 삼성전자주식회사 Mask ROM devices and method for manufacturing the same
CN102446718A (en) * 2011-09-08 2012-05-09 上海华力微电子有限公司 Method for reducing hot carrier implantation damage of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649629A (en) * 1985-07-29 1987-03-17 Thomson Components - Mostek Corp. Method of late programming a read only memory
JP3355083B2 (en) * 1996-03-13 2002-12-09 シャープ株式会社 Method for manufacturing semiconductor device
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1309053C (en) * 2004-03-26 2007-04-04 力晶半导体股份有限公司 Method for producing flash storing device
WO2016119477A1 (en) * 2015-01-29 2016-08-04 无锡华润上华半导体有限公司 Preparation method for flat cell rom device
CN105990242A (en) * 2015-01-29 2016-10-05 无锡华润上华半导体有限公司 Preparation method of flat cell read only memory (ROM)
CN110060724A (en) * 2019-04-09 2019-07-26 江苏东海半导体科技有限公司 A kind of reading out structure of exposure mask memory

Also Published As

Publication number Publication date
CN1225782C (en) 2005-11-02
US6940135B2 (en) 2005-09-06
US20040126974A1 (en) 2004-07-01

Similar Documents

Publication Publication Date Title
US7141468B2 (en) Application of different isolation schemes for logic and embedded memory
US5861334A (en) Method for fabricating semiconductor device having a buried channel
US5576573A (en) Stacked CVD oxide architecture multi-state memory cell for mask read-only memories
KR19980057037A (en) Triple well manufacturing method of semiconductor device
US5585297A (en) Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby
EP0562309B1 (en) Planar process using common alignment marks for well implants
EP0610643A1 (en) EEPROM cell and peripheral MOS transistor
US5557131A (en) Elevated emitter for double poly BICMOS devices
EP0160003B1 (en) Mos floating gate memory cell and process for fabricating same
US20060284266A1 (en) High voltage N-channel LDMOS devices built in a deep submicron CMOS process
CN1225782C (en) Improved mask ROM process and element
CN1669152A (en) Field effect transistor, associated use, and associated production method
US7625797B2 (en) Embedded NV memory and method of manufacturing the same
US6803644B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
US20010001721A1 (en) Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell
CN1199926A (en) Method of fabricating semiconductor device capable of providing mosfet which is improved in threshold voltage thereof
EP0643418B1 (en) Process for the manufacture of a Zener Diode for flash-EEPROM devices
US6011283A (en) Pillar emitter for BiCMOS devices
US6797577B2 (en) One mask PNP (or NPN) transistor allowing high performance
US20040053439A1 (en) Method for producing low-resistance ohmic contacts between substrates and wells in CMOS integrated circuits
CN1574294A (en) Semiconductor memory device, memory cell programming method thereof, and covering screen type read-only memory
EP0227965B1 (en) Method for ion implant programming nmos read-only memories and nmos read-only memory obtained thereby
US5643816A (en) High-density programmable read-only memory and the process for its fabrication
CN1470066A (en) Lowered channel doping with source side boron implant for deep sub 0.18 micron flash memory cell
JP4376325B2 (en) Semiconductor memory device and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING

Effective date: 20111129

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20111129

Address after: 201203 No. 18 Zhangjiang Road, Shanghai

Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp.

Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp.

Address before: 201203 No. 18 Zhangjiang Road, Shanghai

Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp.

CX01 Expiry of patent term

Granted publication date: 20051102

CX01 Expiry of patent term