CN1466205A - Flip Chip type semiconductor package using leadframe as chip carrier - Google Patents
Flip Chip type semiconductor package using leadframe as chip carrier Download PDFInfo
- Publication number
- CN1466205A CN1466205A CNA021412235A CN02141223A CN1466205A CN 1466205 A CN1466205 A CN 1466205A CN A021412235 A CNA021412235 A CN A021412235A CN 02141223 A CN02141223 A CN 02141223A CN 1466205 A CN1466205 A CN 1466205A
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- China
- Prior art keywords
- pin
- chip
- semiconductor package
- solder bump
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
A flip chip semiconductor packaging unit with a lead wire frame as the chip loader is to form a blocking piece on every pin of the frame, so that when a chip is connected with the frame by multisolder projection which are at the terminal zone between and pins and blocking piece and become wetting on the pins when welded so the collapse height will be limited by the blocking pieces, so as to increase the resistance against the stress resulted from different CTE.
Description
Technical field
The invention relates to a kind of semiconductor package part and method for making thereof, particularly about a kind of be the crystal covering type semiconductor package part and the method for making thereof of chip bearing member with the lead frame.
Background technology
With lead frame (Lead Frame) is the semiconductor package part of chip bearing member (Chip Carrier), be with the sticking chip carrier (Die Pad) of being located at of chip, relend by bonding wire (Bonding Wires) chip on the chip carrier is electrically connected to pin (Lead), or, with bonding wire chip is electrically connected to pin more directly with the sticking prolongation of being located at pin of chip.The electrical quality of this kind semiconductor packages mode can descend because of the routing distance, and in the mold pressing processing procedure, bank (WireLoop) is subjected to mould stream easily and impacts and produce the routing skew or topple over (Wire Sweeping orSagging), adjacent bank is touched and is short-circuited.The height of packaging part integral body also can be subject to bank height (Loop Height) and can't effectively reduce in addition, can not satisfy on the market the compact demand of packaging part.
And cover crystalline substance (Flip Chip) formula semiconductor packaging is to adapt to the compact developing trend of electronic product, the sophisticated semiconductor encapsulation technology that makes semiconductor device now develop towards high-performance and Highgrade integration.The difference of the semiconductor package maximum of it and general non-crystal covering type is that promptly packaged chip is with inverse manner with its acting surface that is laid with electronic building brick and electronic circuit, be soldered on the chip bearing member as substrate by the solder bump (Solder Bump) that is welded on the chip pad (Bonding Pad), place and be electrically connected on the chip bearing member and chip is connect.The electrical quality that this kind packaged type provides is than routing mode excellence, and the problem that can avoid the routing mode to be produced.But connect the solder bump of establishing on this chip pad, generally be to make as soft metals such as tin 63/ plumbous 37 alloys by low-melting, reflow is during to chip bearing member, often produce unmanageable scolder subside (Collapse) height problem, make solder bump can't resist between chip and chip bearing member the thermal stress that the difference (CETDismatch) because of thermal coefficient of expansion is produced, and cause weld failure between itself and chip bearing member, cause the electric connection between chip and chip bearing member imperfect; And precision degree of the requirement height of this processing procedure, cost thereby significantly increase, generally be only applicable to high priced line, and be not suitable for the lead frame is the product for example DRAM or the SRAM etc. of chip bearing member, makes with the lead frame to be that the semiconductor device of chip bearing member still can't reduce cost and improve the relevant issues of effectively improving under the condition of acceptance rate about bank and routing produced taking into account.
For addressing the above problem, United States Patent (USP) the 5th, 331, No. 235 propose with the lead frame is the semiconductor package part that chip bearing member utilization Flip Chip electrically connects chip and chip bearing member.As shown in Figure 1, this packaging part comprises that at least two are welded the semiconductor chip 32 and 34 that is provided with solder bump 33 and 35 respectively, this two chip 32 and 34 is to use belt to weld (Tape Automated Bonding automatically in the relative mode of acting surface respectively, TAB) technology, after being connected to projection 33 and 35 hot pressing on the film 31, again film 31 is electrically connected to lead frame 37.Yet, this kind belt is welded the structure that film electrically connects chip and lead frame automatically, can cause the raising of packaging cost because of the use that belt is welded film automatically, and this kind semiconductor package part only uses the belt thermo-compressed technology of welding automatically, in conjunction with the electric connection of Flip Chip in lead frame and chip, several semiconductor chips are coated in the packaging part, its encapsulation volume is minimized, but and unresolved solder bump is when reflow, and the solder bump excessive problem that causes engaging failure of subsiding takes place because of scolder is moistening.For effectively solving the Welding Problems of solder bump and pin, invent in United States Patent (USP) the 6th, 184, the semiconductor package part of No. 573 cases promptly proposes a kind of structure of refusing solder flux (Solder Mask) that is coated with on pin, as shown in Figure 2, be coated with on the pin two 7 of this kind semiconductor package part refuse solder flux 26 after, so be welded with solder bump 24 corresponding to chip 21 and 22 and 25 places are formed with perforate 260, implant for the solder bump on chip 21 and 22 24 and 25, when reflow is handled, solder bump 24 and 25 can by perforate 260 restriction not the moistening pin of reason scolder the excessive problem of subsiding is arranged, and borrow subsiding highly of perforate 260 control solder bumps 24 and 25; But in this processing procedure, will refuse solder flux 26 and apply (Coating) on pin two 7 and form the processing procedure complexity and the cost height of perforate, and there is no improvement for simplifying processing procedure and reducing cost, the product that is suitable for still is restricted.
For guarantee between solder bump and chip bearing member electric connection not the reason solder bump subside when the reflow operation and excessively fail, other has the solder bump that adopts the brazing metal of high lead tolerance to make from the scholar in the industry, the solder bump cost that the brazing metal of the high lead tolerance of this kind is made is very high, and be not inconsistent economic benefit, so still fail effectively to solve aforesaid all problem.
Summary of the invention
A purpose of the present invention is chip bearing member and can avoiding has the situation of the failure of electrically connecting to take place between chip and lead frame crystal covering type semiconductor package part with the lead frame providing a kind of promptly.
Another object of the present invention is chip bearing member with the lead frame providing a kind of then, effectively avoids solder bump moistening crystal covering type semiconductor package part and method for making thereof on lead frame fully on the chip in mode cheaply.
For reaching above-mentioned and other purpose, semiconductor package part of the present invention is to comprise at least one chip with several solder bumps; One has the lead frame of some pins, and the appropriate position on each pin is provided with a stop part, forming a weld zone between the end by this stop part and pin, makes chip and the electric connection of this lead frame for the solder bump of chip welds it on; And one in order to coat the packing colloid of this chip, solder bump and pin partly.
Be somebody's turn to do subsiding in order to the definition solder bump highly to prevent solder bump moistening stop part on lead frame fully, can be polyimides film (Polyimide Tape), or with screen printing mode coating by refusing the ponding (Dam) that solder flux constitutes, can effectively control the height that subsides of solder bump, when avoiding solder bump to be soldered on the pin, it is moistening fully on pin and cause both to weld the problem of failure that solder bump takes place.
Formation by stop part of the present invention, the solder bump that chip of the present invention is used needn't use cost be higher than the general above high lead tolerance brazing metal of gold (Eutectic Alloy) twice that merges altogether, or the aforesaid existing anti-welding processing of refusing solder flux, thereby can effectively control the height that subsides of solder bump, the problem of failing with the electric connection of avoiding solder bump and lead frame takes place.
For further promoting the electric connection of solder bump and pin, can on the position between the end of the internal pin portion of stop part and lead frame, be formed with groove (Recess) or projection (Protrusion) in this internal pin position.The formation of this groove or projection can adopt existing punching press (Punching) or etching (Etching) mode to finish, and its shape or the no specific limited of size, as long as can effectively increase the bonding area of solder bump and pin.
The method for making of semiconductor package part of the present invention then comprises the following steps: to prepare a lead frame, and it has several pins; Appropriate location in this pin portion respectively is provided with a stop part, forms a weld zone so that be positioned on this pin between the end of this stop part and pin; The chip that makes a weldering be provided with many solder bumps connects to be put to this lead frame, and it connects the mode of putting is that the solder bump of this chip is soldered on the weld zone of pin, so that this chip and pin electrically connect; And form a packing colloid to coat the some of this chip, solder bump and pin.
Description of drawings
Below be described in further detail characteristics of the present invention and effect with the preferred embodiment conjunction with figs.:
Accompanying drawing 1 be for existing be the cutaway view of the crystal covering type semiconductor package part of chip bearing member with the lead frame;
Accompanying drawing 2 be another existing be the cutaway view of the crystal covering type semiconductor package part of chip bearing member with the lead frame;
Accompanying drawing 3 is cutaway views of the semiconductor package part of first embodiment of the invention;
Accompanying drawing 4A is the manufacturing flow chart of the semiconductor package part of first embodiment of the invention to accompanying drawing 4D;
Accompanying drawing 5 is cutaway views of the semiconductor package part of second embodiment of the invention;
Accompanying drawing 6 is cutaway views of the semiconductor package part of third embodiment of the invention;
Accompanying drawing 7 is cutaway views of the semiconductor package part of fourth embodiment of the invention;
Accompanying drawing 8 is cutaway views of the semiconductor package part of fifth embodiment of the invention.
Embodiment
Embodiment 1
As shown in Figure 3 for first embodiment of the invention be the crystal covering type semiconductor package part profile of chip bearing member with the lead frame.
As shown in the figure, the semiconductor package part 3 of first embodiment of the invention mainly is by a chip 30, connects the lead frame 31 put and constitutes in order to the packing colloid 32 of the some that coats this chip 30 and lead frame 31 for this chip 30.
This chip 30 is formed with on the action face of electronic building brick and electronic circuit in it, be welded with many solder bumps 33 with existing welding manner, so that this chip 30 is borrowed this solder bump 33 and lead frame 31 in succession, and make this chip 30 and lead frame 31 form the crystal covering type syndetons.
This lead frame 31 is to have many pins 310, and each pin 310 is made of internal pin 311 that packing colloid 32 coated and the external pin 312 that exposes outside this packing colloid 32.Respectively this internal pin 311 and have an end 313, and 313 of each ends preset distance of all being separated by.Connect on the surface of putting for chips 30 and closely by the then sticking polyimides film 314 that is equipped with of the appropriate location of this end 313 at this internal pin 311, form a weld zone 315 to connect on the surface of putting for chip 30 in its end 313 and 314 on film at this internal pin 311, borrow the reflow technology to be soldered on this weld zone 315 for this solder bump 33, and make this chip 30 borrow this solder bump 33 and the pin 310 of lead frame 31 to electrically connect.This solder bump 33 is owing to be subjected to stopping of this film 314, its moistening zone to internal pin 311 in the reflow operation only can be confined to this weld zone 315, and unlikely extending on the zone of internal pin 311 outside this weld zone 315, so it is moistening fully on internal pin 311 and make itself and the problem generation of the welding failure of internal pin 311 not have solder bump 33; Simultaneously, this film 314 has a predetermined height, after borrowing this solder bump 33 to be electrically connected on the lead frame 31 at this chip 30, is enough to control the height that this solder bump 33 subsides, and can avoids taking place the excessive problem of subsiding of solder bump 33.
In addition, also can replacing of this film 314 by refusing the stop part that solder flux or other suitable material make, make this stop part can borrow existing mode of printing or coating method to be laid in appropriate location on the internal pin 311, borrow the setting of this stop part, can effectively stop on the solder bump 33 moistening zones to weld zone 315, guaranteeing that solder bump 33 has enough height that subsides with opposing chip 30 and the thermal stress that difference caused of lead frame 31 because of thermal coefficient of expansion, thereby must guarantee good electric connection with pin 310.
Be depicted as the schematic diagram of encapsulation procedure of the semiconductor package part 3 of first embodiment of the invention to accompanying drawing 4D as accompanying drawing 4A.
On making, as shown in accompanying drawing 4A, prepare one and do not have chip carrier (Die Pad) and the lead frame 31 that only constitutes by many pins 310.As shown be the lead frame of a bilateral arranged type (Dual-in-Line Type), with the use that is bilateral arranged type chip of a corresponding weld pad, if chip is a peripheral weld pad formula person, then this lead frame 31 also can be four limit arranged types (Quad Flat Type) persons.Each pin 310 has an internal pin 311 and an external pin 312, and this internal pin 311 also has an end 313.
Shown in accompanying drawing 4B, a polyimides film 314 is affixed to default place on the internal pin 311, to form a weld zone 315 in this film 314 and 313 of ends on the surface that is pasted with film 314 at this internal pin 311.
Shown in accompanying drawing 4C, a chip 30 that is welded with many solder bumps 33 connect in the surface mode down of welding this solder bump 33 put to the pin 310 of this lead frame 31.It connects the mode of putting is that this solder bump 33 is soldered on the weld zone 315 of this internal pin 311 with existing reflow operating type, makes this chip 30 borrow solder bump 33 and pin 310 to electrically connect.As previously mentioned, because the setting of film 314 is arranged, solder bump 33 can be only moistening on weld zone 315 because of stopping of film 314 in crumple and after subsiding, and unlikely 315 other the outer zones that extend to pin 310 in the weld zone are so can guarantee the electric connection quality of solder bump 33 and pin 310.
Shown in accompanying drawing 4D, after chip 30 borrows solder bump 33 and pin 310 to electrically connect, promptly carrying out molding operation is coated in the packing colloid 32 that forms with potting resin with the internal pin 311 with this chip 30, solder bump 33 and pin 310, make chip 30 and extraneous seal isolation, can prevent the inside of outside air or foreign matter intrusion semiconductor package part 3.
Form this packing colloid 32 successive process afterwards, as toasting (Curing), impress (Marking), remove slag/moulding (Trim/Form) and cut list (Singulation) etc., all for existing step, so do not give unnecessary details in a separate paper at this.
Embodiment 2
As shown in Figure 5, the semiconductor package part 5 of second embodiment of the invention is to be approximately identical to aforesaid first embodiment, its difference be this semiconductor package part 5 pin 510 on, be to be pasted with film 514a and 514b respectively on the lower surface, with by 513 of 513 of the ends of film 514a and pin 510 and film 514b and ends respectively on this pin 510, form weld zone 515a and 515b on the lower surface, planting many solder bump 53a that connect for institute on the chip 50a on is soldered on the weld zone 515a by means of the reflow operation, to electrically connect chip 50a to pin 510, and plant many solder bump 53b that connect for institute on the chip 50b once and be soldered on the weld zone 515b by means of the reflow operation, electrically connecting chip 50b to pin 510, and make semiconductor package part 5 become the structure of multicore sheet.Because no matter the solder bump that is welded on the upper surface of pin 510 or the lower surface is film 514a and 514b is limited in weld zone 515a and the 515b, thus can not occur solder bump because of subside excessive cause and pin between the electric connection situation of failing.
As shown in Figure 6, the semiconductor package part 6 of third embodiment of the invention is roughly the same with aforesaid first embodiment, just for to make when planting in the solder bump on the chip 60 63 in reflow on the weld zone to pin 610 615, solder bump 63 is obtained further control with the electric connection of pin 610, this pin 610 also can be formed with at least one groove 616 on weld zone 615, make solder bump 63 when moistening, because of the formation of groove 616 increases moistening contact area, so can more effectively strengthen the electrical connectivity of 610 of solder bump 63 and pins.
The shape of this groove 616 can be dish-shaped, cup-shaped or taper from cross-section, and its shape there is no specific restriction; Have, the quantity of its setting is also unrestricted again, but can be continuous phase mode in succession, makes smoothization of air spots or the roughening of weld zone 615.
Embodiment 4
As shown in Figure 7, the semiconductor package part 7 of fourth embodiment of the invention is roughly the same with aforesaid first embodiment, can also punching press or the mode of bending form at least one projection 717, so that this solder bump 73 is in crumple and after subsiding, this projection 717 must be inserted in this solder bump 73, and then strengthens annexation between the two.
Same, this projection 717 quantity is set and shape does not have specific limited yet.
As shown in Figure 8, the semiconductor package part 8 of fifth embodiment of the invention is roughly the same with aforesaid first embodiment, its difference is, this semiconductor package part 8 is a Sequare shape pin-free planar (Quad Flat Non-leaded, QFN) structure, just the bottom surface 810b of this pin 810 exposes outside this packing colloid 82 after packing colloid 82 forms, and makes the direct and external device electric connection of bottom surface 810b of this pin 810.The end face 810a of pin 810 then also supplies being sticked of film 814, and is forming a weld zone 815 for the 83 welding usefulness of the solder bump on the chip 80 on this end face 810a.
Claims (16)
1. a semiconductor package part is characterized in that, this semiconductor package part is to comprise:
At least one chip that is equipped with several solder bumps that connects;
One has the lead frame of several pins, be provided with a stop part in the appropriate location of this pin respectively, so that this pin is provided with on the surface of this stop part, form a weld zone by this stop part between the end of pin, be soldered on this weld zone for this solder bump, and make this chip be electrically connected on this lead frame; And
One packing colloid is in order to coat the some of this chip, solder bump and pin.
2. semiconductor package part as claimed in claim 1, it is characterized in that, the pin of this lead frame is that part is coated by this packing colloid, and another part then exposes outside this packing colloid, electrically connects with external device with the part that is exposed outside packing colloid by this pin.
3. semiconductor package part as claimed in claim 1 is characterized in that, the bottom surface of the pin of this lead frame is to expose outside this packing colloid, electrically connects with bottom surface and the external device that is exposed by this pin.
4. semiconductor package part as claimed in claim 1 is characterized in that, this stop part is a film.
5. semiconductor package part as claimed in claim 1 is characterized in that, this stop part is a ponding of coating on this pin, forming with resin material with mode of printing.
6. semiconductor package part as claimed in claim 1 is characterized in that, also is formed with at least one groove on this weld zone.
7. semiconductor package part as claimed in claim 1 is characterized in that, also is formed with at least one projection on this weld zone.
8. semiconductor package part as claimed in claim 1 is characterized in that, this solder bump is to be soldered on the weld zone of this pin with the reflow operating type.
9. the method for making of a semiconductor package part is characterized in that, this method for making comprises the following steps:
Prepare a lead frame, it has several pins; One stop part is set on the appropriate location of this pin,, between the end of this stop part and pin, forms a weld zone to be provided with at this pin on the surface of stop part;
Connect and put a chip to this lead frame, planted many solder bumps on this chip, this solder bump is soldered on the weld zone of corresponding pin, make this chip borrow this solder bump and lead frame to electrically connect; And form a packing colloid to coat the some of this chip, solder bump and pin.
10. method for producing semiconductor packaging part as claimed in claim 9, it is characterized in that, the pin of this lead frame is that part is coated by this packing colloid, and another part then exposes outside this packing colloid, electrically connects with external device with the part that is exposed outside packing colloid by this pin.
11. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, the bottom surface of the pin of this lead frame is to expose outside this packing colloid, electrically connects with bottom surface and the external device that is exposed by this pin.
12. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, this stop part is a film.
13. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, this stop part is a ponding of coating on this pin, forming with resin material with mode of printing.
14. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, also is formed with at least one groove on this weld zone.
15. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, also is formed with at least one projection on this weld zone.
16. method for producing semiconductor packaging part as claimed in claim 9 is characterized in that, this solder bump is to be soldered on the weld zone of this pin with the reflow operating type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021412235A CN1466205A (en) | 2002-07-03 | 2002-07-03 | Flip Chip type semiconductor package using leadframe as chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021412235A CN1466205A (en) | 2002-07-03 | 2002-07-03 | Flip Chip type semiconductor package using leadframe as chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1466205A true CN1466205A (en) | 2004-01-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021412235A Pending CN1466205A (en) | 2002-07-03 | 2002-07-03 | Flip Chip type semiconductor package using leadframe as chip carrier |
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| Country | Link |
|---|---|
| CN (1) | CN1466205A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403241A (en) * | 2011-11-15 | 2012-04-04 | 三星半导体(中国)研究开发有限公司 | Double-side plastic packaging method of LGA (Land Grid Array) |
| CN105702652A (en) * | 2014-12-11 | 2016-06-22 | 意法半导体有限公司 | Integrated circuit (IC) package with a solder receiving area and associated methods |
| CN107026141A (en) * | 2016-01-04 | 2017-08-08 | 英飞凌科技股份有限公司 | Semiconductor devices including solder barrier |
-
2002
- 2002-07-03 CN CNA021412235A patent/CN1466205A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403241A (en) * | 2011-11-15 | 2012-04-04 | 三星半导体(中国)研究开发有限公司 | Double-side plastic packaging method of LGA (Land Grid Array) |
| CN102403241B (en) * | 2011-11-15 | 2013-11-27 | 三星半导体(中国)研究开发有限公司 | Double-side plastic packaging method of LGA (Land Grid Array) |
| CN105702652A (en) * | 2014-12-11 | 2016-06-22 | 意法半导体有限公司 | Integrated circuit (IC) package with a solder receiving area and associated methods |
| US10297534B2 (en) | 2014-12-11 | 2019-05-21 | Stmicroelectronics Pte Ltd | Integrated circuit (IC) package with a solder receiving area and associated methods |
| CN105702652B (en) * | 2014-12-11 | 2019-10-18 | 意法半导体有限公司 | Integrated circuit (IC) packaging body and associated method with solder receiving area |
| US10529652B2 (en) | 2014-12-11 | 2020-01-07 | Stmicroelectronics Pte Ltd | Integrated circuit (IC) package with a solder receiving area and associated methods |
| CN107026141A (en) * | 2016-01-04 | 2017-08-08 | 英飞凌科技股份有限公司 | Semiconductor devices including solder barrier |
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