CN1464407A - Process for controlling micro processor read-in camera pick-up head data and controller therefor - Google Patents
Process for controlling micro processor read-in camera pick-up head data and controller therefor Download PDFInfo
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Abstract
The invention discloses a process for controlling micro processor read-in camera pick-up head data characterized by that a pick-up head controller is arranged between the pick-up head and the micro processor, when the pick-up head transmits data to the micro processor, the data is first output into the pick-up head controller, Then the pick-up head controls the micro processor to read-in data from internal through interrupt mode. The invention also discloses pick-up head controller for achieving said process which is linked between the pick-up head and the micro processor. Based on the pick-up head controller and control process of the invention, the pick-up head data can be buffered and the data output can be controlled. It is achieved by the invention that under the precondition of minimum incremental cost, the micro processor data calling frequency for micro processor is lowered, the processing capability of the micro processor is thus fully utilized and the system performance is enhanced substantially.
Description
Technical field
The present invention relates to camera data read technology, refer to that especially a kind of control microprocessor reads the method and the camera controller of camera data.
Background of invention
Develop rapidly along with the electronics and the communication technology, people are more and more higher to the requirement of all kinds of electronic system real-time Communication for Power functions, therefore, some systems have introduced a series of communication function, for example: bluetooth and GSM and 802.11b or the like, in these systems, mostly will introduce the function of image, thereby the requirement that increases camera will be very important.
At present, in the process of introducing camera, usually introduce the CMOS camera, the annexation of this CMOS camera and microprocessor as shown in Figure 1, CMOS camera 11 links to each other with microprocessor 12 by the IO analog form, microprocessor 12 is the state of inquiry IO constantly, and identification CMOS camera 11 variation of output signals situations are so that further handle.
For complementary metal oxide semiconductor (CMOS) (CMOS) camera commonly used, referring to shown in Figure 2, the output interface of CMOS camera is mainly exported following several signal: the clock signal MCLK, the I that need during the work of CMOS camera
2The clock sclk of C universal serial bus, I
2The output data ADC[9:0 of the data SDATA of C universal serial bus, CMOS camera], the Dot Clock HCLK of CMOS camera, the row clock VCLK of CMOS camera and the frame clock SOF of CMOS camera.Wherein, ADC[9:0] numerical data that changes into by simulation of expression, represent redly for 3 in 10 bits, represent blueness for 3, represent green for 4.The situation of change of above-mentioned signal when Fig. 2 has provided camera work, as can be seen from the figure, during camera work, by the numerical value of exportable each the pixel RGB of the variation of HCLK signal, col.48 wherein, col.49 etc. promptly represent the 48th, 49 row etc.; When the HCLK signal changed to pixel value of each row that camera sets, VCLK changed, and the indication next line begins; When the VCLK signal changed to the pixel value of each set row of camera, the SOF signal changed, and indicated new frame to begin, and so went round and began again, and camera just can operate as normal.
Owing to do not have the camera controller between existing C MOS camera and the microprocessor, general microprocessor adopts general input and output (GPIO) mode to finish the processing that signal changes.As shown in Figure 3, when system initialization, system at first will be provided with SOF, HCLK, VCLK and ADC[9:0] initial value, that is: these signals of initialization.When the camera operate as normal, the state of IO is constantly inquired about in little processing, microprocessor to the Signal Processing process as shown in Figure 4:
A1. judge in the signal of current collection whether the SOF signal indicates a new frame to begin, if the value that current row and column then is set is 0, enters step b1, otherwise, directly enter step b1;
B1. judge in the signal of current collection whether the VCLK signal indicates new delegation to begin, if the value that then is provided with when the prostatitis is 0, and the value of row adds 1, enters step c1, otherwise, directly enter step c1;
C1. judge in the signal of current collection whether the HCLK signal indicates new pixel to begin, if, then read ADC[9:0] on data in the microprocessor internal memory of preparing for this ranks pixel of storage of appointment, the value that is provided with when the prostatitis adds 1, returns step a1, otherwise, directly return step a1.
From above-mentioned processing procedure as can be seen, owing to do not have integrated camera controller in the microprocessor, microprocessor will come the output signal of acquisition camera by inquiry IO state, so, when this CMOS camera pixel more for a long time, microprocessor must constantly scan input, could constantly read the data on this CMOS camera.Because the working method of CMOS camera is continuous working, therefore in order to guarantee not make loss of data, microprocessor must all consume most of performance on the data read of CMOS camera, this just is not very high embedded microprocessor for original performance, can finish other task more hardly, so make the application of CMOS camera that very big difficulty is arranged.If but directly the CMOS camera is integrated on the microprocessor, the performance of microprocessor is reduced greatly.In addition, the interface of CMOS or other class camera is not set in some microprocessor, more can't introduces camera for this microprocessor system.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of control microprocessor to read the method for camera data, make it under the prerequisite that increases few cost, reduce the data access frequency of microprocessor, sufficiently and reasonably utilize the processing power of microprocessor, and then significantly improve system performance.
Another object of the present invention is to provide a kind of camera controller, make the data of its energy buffer memory camera and the output of control data, and then improve the handling property of total system.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of control microprocessor reads the method for camera data, it is that a camera controller is set between camera and microprocessor, when camera when microprocessor transmits data, earlier data are outputed in the camera controller, pass through the interrupt mode control microprocessor from its inner reading of data by the camera controller again.
This method further comprises: the camera controller is one section output data that fixing memory headroom is stored camera of portion's definition within it in advance.
In said method, the variation of camera controller real-time judge frame signal, row signal and column signal, new frame begins if frame signal changes indication, and then the value of current row and column is set is 0 to the camera controller; If the row signal changes the new row beginning of indication, then the setting of camera controller when the value in prostatitis be 0, the value of Hanging adds 1 simultaneously; New pixel begins if column signal changes indication, and then the setting of camera controller adds 1 when the value in prostatitis, and reads the output data of camera, is stored in the predefined memory headroom of camera controller.Wherein, after the camera controller read the output data of camera, remove each 10 bit data earlier minimum two, removing low two data combination with per four again was one 32 data, is stored in the predefined memory headroom of camera controller.
In reading of data, the camera output data quantity of being stored in the internal memory that the camera controller is set reaches a half of this set memory total amount, and the camera controller produces half capacity and interrupts HALF_IRQ to microprocessor.When the camera output data quantity of being stored in the internal memory that the camera controller is set equaled this set memory total amount, the camera controller produced full capacity interruption FULL_IRQ and interrupts to microprocessor.
In microprocessor side, when microprocessor responds half capacity interruption HALF_IRQ entered the break in service flow process, this method further comprised:
A1., the internal memory start address that data read is set is 0;
B1. microprocessor reading of data from the internal memory that the camera controller is set runs through the back current memory address and adds 1;
Whether the value of c1. judging current memory address equals half of the set memory amount of camera controller, if not, then return step b1; Otherwise the memory headroom that the camera controller is set is divided into two parts, then preceding half section memory address and second half section memory address is exchanged.
When microprocessor responds full capacity interruption FULL_IRQ entered the break in service flow process, this method further comprised:
A2., the internal memory start address that data read is set is 0;
B2. microprocessor reading of data from the internal memory that the camera controller is set runs through the back current memory address and adds 1;
Whether the value of c2. judging current memory address equals the set memory amount of camera controller, if not, then return step b2; Otherwise system reads an error flag, and the data relevant with this misdata are abandoned.
The present invention also provides a kind of camera controller, be used to be arranged between camera and the microprocessor, control microprocessor is from the camera reading of data, be connected by bus mode between camera and the camera controller, be connected in direct memory access (DMA) (DMA) mode between microprocessor and the camera controller; This controller comprises:
The data analysis read module is used to judge the variation of camera signals, and variation is provided with parameter value or reads image data according to signal;
Cache module is used for the view data that buffer-stored data analysis read module reads from camera;
Interrupt generation module, be used to judge the current store status of cache module, and produce interruption to microprocessor according to current store status, control microprocessor is from its inner reading of data.
Wherein, described cache module is camera controller one section fixing memory headroom of portion's setting within it in advance.Described camera signals is frame signal or row signal or column signal.Described parameter value is the value of current line or works as the value in prostatitis.Described current store status is that the data of storing in the cache module have reached half of total volume, or the cache module capacity is full.The interruption that is produced is that half capacity interrupts HALF_IRQ, or full capacity interrupts FULL_IRQ.
By such scheme as can be seen, key of the present invention is: increase a camera controller between original camera and microprocessor, be used for buffer memory and control view data, to alleviate the burden of microprocessor, improve the performance of system.
Therefore, control microprocessor provided by the present invention reads the method and the camera controller of camera data, owing to increased the camera controller, when microprocessor work, camera elder generation in the camera controller, when storing some into, produces data storage to interrupt, microprocessor is again by dma mode, and unification is read.So, microprocessor is freed from loaded down with trivial details inquiry, judgement, shifting function, alleviate the burden of microprocessor, reduced the rate of people logging in of microprocessor, more help the reasonable distribution of microprocessor, and then significantly improve system performance, improve system effectiveness self processing power.And as the camera controller, only needing increases very little cost with the programmable chip of maturation, and with respect to the raising of system performance, the ratio of performance to price has also improved.
Description of drawings
The sequential chart of output signal when Fig. 1 works for the CMOS camera;
Fig. 2 is the annexation synoptic diagram of CMOS camera and microprocessor in the prior art;
Fig. 3 is the initialization flowchart of microprocessor processes CMOS camera signals in the prior art;
Fig. 4 is the process flow diagram that microprocessor processes CMOS camera signals changes in the prior art;
Fig. 5 is the annexation synoptic diagram of camera controller of the present invention and camera and microprocessor;
Fig. 6 handles one of fundamental diagram of camera signals for camera controller of the present invention;
Fig. 7 handle for camera controller of the present invention camera signals fundamental diagram two;
Fig. 8 handle for camera controller of the present invention camera signals fundamental diagram three;
One of schematic diagram that Fig. 9 produces for interruption in the camera controller of the present invention;
Figure 10 is two of the schematic diagram that interrupts in the camera controller of the present invention producing;
Figure 11 is the process flow diagram of microprocessor of the present invention to the HALF_IRQ break in service;
Figure 12 is the process flow diagram of microprocessor of the present invention to the FULL_IRQ break in service.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
In order to solve the problems of the prior art, the present invention has made a controller for camera, as shown in Figure 5, between camera 51 and microprocessor 52, increase a camera controller 50, this camera controller 50 is provided with two interfaces, and one towards camera 51, and another is towards microprocessor 52, make camera controller 50 become the tie between camera 51 and the microprocessor 52, be used for a large amount of view data of buffer memory and control its output to microprocessor.Mainly comprise three parts in this camera controller 50: data analysis read module, cache module and interruption generation module, its basic principle of work is exactly: the variation of frame signal in the data analysis read module real-time judge camera 51 of camera controller 50, row signal and column signal, and change value or the reads image data that current ranks are set according to signal; To be cached in from the view data that camera 51 reads the cache module then; When the interruption generation module of camera controller 50 detects half or capacity that the image data amount of depositing reached the self EMS memory capacity and has expired, then to 52 interruptions of microprocessor, microprocessor 52 is once read the view data of storage in the current camera controller 50, handles.Conduct interviews by bus mode between camera 51 and the camera controller 50, comprise data bus and address bus, to accelerate access speed; Be connected with dma mode between camera controller 50 and the microprocessor 52, disposable reading of data, thus improved the treatment effeciency of microprocessor.
The camera controller that the present invention increased adopts programmable logic device (PLD) to realize, such as: FPGA, CPLD, or other has the chip of same function.In the present embodiment, the camera controller adopts FPGA.At first, in FPGA, distribute some internal memories, but because the restriction of FPGA memory source for the view data that will store, in FPGA can not according to: line number * columns * 10bit distributes, and can only distribute the internal memory of a few row needs, for example: 4 row * columns * 32bit.Secondly, whether which row define the current data that open the beginning of data indication in internal memory is, define data again and indicate current data effective.
Referring to Fig. 6～shown in Figure 8, the principle of work of FPGA reads image data and buffer memory is such: because FPGA is concurrent working, therefore, to SOF signal, VCLK signal and HCLK Signal Processing parallel finishing on hardware.When the new frame of SOF signal indication began, the value that FPGA is provided with current row and column was 0, continue then to judge, otherwise cycle criterion always; When new the going of VCLK signal indication began, the value that FPGA is provided with when the prostatitis was 0, and the value of row adds 1, continuation judgement then, otherwise cycle criterion always; When the new pixel of HCLK signal indication begins, the value that FPGA is provided with when the prostatitis adds 1, and read ADC[9:0] on data, with per 4 ADC[9:0] data combination is one 32 data, again this 32 bit data is stored in the internal memory of FPGA for this pixel distribution, continue then to judge, otherwise cycle criterion always.Reading and during data splitting, because normally 32 of Microprocessor Interface, so be combined as 32 data.But 4 ADC[9:0] when data combination is one 32 bit data, can have more 8 bit data, the simplest method is directly to remove each ADC[9:0] in minimum two, though so can be influential to the data result, but influence is little, and concerning system optimization, has but made things convenient for a lot.
In the FPGA side, when FPGA detects the half that the current view data capacity of storing has reached self random access memory (RAM) capacity, FPGA can produce HALF_IRQ and interrupt to microprocessor, indicate current data to arrive half of max cap., system for prompting reads, indicate these data effective simultaneously, as shown in Figure 9.When FPGA detected the current view data capacity of storing and equaled the capacity of self random access memory (RAM), FPGA can produce FULL_IRQ and interrupt to microprocessor, indicates the data of the current RAM of not depositing in invalid simultaneously, as shown in figure 10.
In microprocessor side, have no progeny among the microprocessor responds HALF_IRQ, enter HALF_IRQ break in service treatment scheme, as shown in figure 11:
A2., the start address that data read is set earlier is 0;
B2. microprocessor reading of data from the internal memory of FPGA definition then, run through the data of current address after, the address is added 1;
Whether the value of c2. judging the current address equals half of the defined internal memory max cap. of FPGA, if not, then return step b2; Otherwise, the order of Installed System Memory is set, that is: defined memory headroom is divided into two parts, the address of preceding half section internal memory and second half section internal memory is exchanged, data are wherein waited for when interrupt next time and being read.That is to say that after the content of current half part is read sky, the content of latter half is replaced up, so, for microprocessor, what read is the content of first half in the internal memory forever, can reduce the complexity of microprocessor processes program.
In microprocessor side, have no progeny among the microprocessor responds FULL_IRQ, enter FULL_IRQ break in service treatment scheme, as shown in figure 12:
A3., the start address that data read is set earlier is 0;
B3. microprocessor reading of data from the internal memory of FPGA definition then, run through the data of current address after, the address is added 1;
C3. judge whether the value of current address equals the max cap. of internal memory that FPGA defines, if not, step b3 then returned; Otherwise system reads an error flag, and the data relevant with the data that make a mistake are at last abandoned, such as: if when certain frame data does not all deposit the defined internal memory of FPGA in, memory size is just full, and then these frame data will make a mistake, and should lose.
As seen, in such scheme, microprocessor need not go to read the output data of camera in real time, but read a certain amount of data by down trigger is disposable, the phenomenon of having avoided microprocessor only to be busy with reading the camera output data and can not having handled other affairs takes place, make microprocessor can rationally use the processing power of self, and then improved system performance and efficient.
By the application example of following mask body, can further find out the superior part that increases the camera controller.In the present embodiment, microprocessor system adopts the SA1110 of INTEL, and the CMOS camera that is equipped with for this processor is the MCM20114 of MOTOROLA, colored VGA, and resolution is 640 * 480.Because this processor does not have the interface of CMOS camera, therefore adopting model is the FPGA of the SPARTAN-II X2S100-5PQ208C of XILINX, as the camera controller between this CMOS camera and the SA1110 processor system.Suppose that this CMOS camera provides the view data of 30 frames p.s., the capacity that FPGA distributes for buffering is 640 * 4 * 32bit.
So, if by GPIO analog form reading of data of the prior art, because whole flow processs is to finish by software, the cycle of can calculation system inquiring about is:
Cycle=1/ (640 * 480 * 30)=1/9216000 is promptly: the frequency of this inquiry is 9.216MHz.
And after adopting FPGA to be the camera controller, because FPGA is equivalent to a buffering, so the access frequency of microprocessor obviously reduces, the cycle that the system in the case can calculated is inquired about is:
Cycle=640 * 4 * 4/ (640 * 480 * 30)=1/900 are promptly: its access frequency is 900Hz, has reduced by 10240 times than preceding kind of mode.As seen, this controller can significantly improve the performance of system.
The present invention is not only applicable to the CMOS camera, also can be used for other camera, only needs according to the difference of interface corresponding treatment scheme to be changed slightly.In a word, the above is preferred embodiment of the present invention only, is not to be used for limiting protection scope of the present invention.
Claims (16)
1, a kind of control microprocessor reads the method for camera data, it is characterized in that: a camera controller is set between camera and microprocessor, when camera when microprocessor transmits data, earlier data are outputed in the camera controller, pass through the interrupt mode control microprocessor from its inner reading of data by the camera controller again.
2, method according to claim 1 is characterized in that this method further comprises: the camera controller is one section output data that fixing memory headroom is stored camera of portion's definition within it in advance.
3, method according to claim 1 and 2, it is characterized in that this method further comprises: the variation of camera controller real-time judge frame signal, row signal and column signal, new frame begins if frame signal changes indication, and then the value of current row and column is set is 0 to the camera controller; If the row signal changes the new row beginning of indication, then the setting of camera controller when the value in prostatitis be 0, the value of Hanging adds 1 simultaneously; New pixel begins if column signal changes indication, and then the setting of camera controller adds 1 when the value in prostatitis, and reads the output data of camera, is stored in the predefined memory headroom of camera controller.
4, method according to claim 3, it is characterized in that this method further comprises: after the camera controller reads the output data of camera, remove each 10 bit data earlier minimum two, removing low two data combination with per four again is one 32 data, is stored in the predefined memory headroom of camera controller.
5, method according to claim 1, it is characterized in that this method further comprises: the camera output data quantity of being stored in the internal memory that the camera controller is set reaches a half of this set memory total amount, and the camera controller produces half capacity and interrupts HALF_IRQ to microprocessor.
6, method according to claim 1, it is characterized in that this method further comprises: when the camera output data quantity of being stored in the internal memory that the camera controller is set equaled this set memory total amount, the camera controller produced full capacity and interrupts FULL_IRQ to microprocessor.
7, method according to claim 5 is characterized in that this method further comprises when microprocessor responds half capacity interruption HALF_IRQ enters the break in service flow process:
A1., the internal memory start address that data read is set is 0;
B1. microprocessor reading of data from the internal memory that the camera controller is set runs through the back current memory address and adds 1;
Whether the value of c1. judging current memory address equals half of the set memory amount of camera controller, if not, then return step b1; Otherwise the memory headroom that the camera controller is set is divided into two parts, then preceding half section memory address and second half section memory address is exchanged.
8, method according to claim 6 is characterized in that this method further comprises when microprocessor responds full capacity interruption FULL_IRQ enters the break in service flow process:
A2., the internal memory start address that data read is set is 0;
B2. microprocessor reading of data from the internal memory that the camera controller is set runs through the back current memory address and adds 1;
Whether the value of c2. judging current memory address equals the set memory amount of camera controller, if not, then return step b2; Otherwise system reads an error flag, and the data relevant with this misdata are abandoned.
9, a kind of camera controller is used to be arranged between camera and the microprocessor, and control microprocessor is characterized in that from the camera reading of data this controller comprises:
The data analysis read module is used to judge the variation of camera signals, and variation is provided with parameter value or reads image data according to signal;
Cache module is used for the view data that buffer-stored data analysis read module reads from camera;
Interrupt generation module, be used to judge the current store status of cache module, and produce interruption to microprocessor according to current store status, control microprocessor is from its inner reading of data.
10, camera controller according to claim 9 is characterized in that: described cache module is camera controller one section fixing memory headroom of portion's setting within it in advance.
11, camera controller according to claim 9 is characterized in that: described camera signals is frame signal or row signal or column signal.
12, camera controller according to claim 9 is characterized in that: described parameter value is the value of current line or works as the value in prostatitis.
13, camera controller according to claim 9 is characterized in that: described current store status is that the data of storing in the cache module have reached half of total volume, or the cache module capacity is full.
14, according to claim 9 or 13 described camera controllers, it is characterized in that: the interruption that is produced is that half capacity interrupts HALF_IRQ, or full capacity interrupts FULL_IRQ.
15, camera controller according to claim 9 is characterized in that: be connected by bus mode between camera and the camera controller.
16, camera controller according to claim 9 is characterized in that: be connected in direct memory access (DMA) (DMA) mode between microprocessor and the camera controller.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281376A (en) * | 2010-06-09 | 2011-12-14 | 柯尼卡美能达商用科技株式会社 | Image processing device, method and computer readable storage medium for storing programs |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102281376A (en) * | 2010-06-09 | 2011-12-14 | 柯尼卡美能达商用科技株式会社 | Image processing device, method and computer readable storage medium for storing programs |
| US8976373B2 (en) | 2010-06-09 | 2015-03-10 | Konica Minolta, Inc. | Image processing apparatus, computer-readable storage medium storing program and image processing method |
| CN102281376B (en) * | 2010-06-09 | 2015-08-19 | 柯尼卡美能达商用科技株式会社 | Image processing equipment, method and stored program computer-readable recording medium |
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Owner name: LIANXIANG (BEIJING) CO. LTD.; HUMANTEC INDUSTRIAL Free format text: FORMER OWNER: LIANXIANG (BEIJING) CO. LTD. Effective date: 20080627 |
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Effective date of registration: 20080627 Address after: No. 6, Pioneer Road, Beijing, Haidian District: 100085 Co-patentee after: Lenovo Mobile Communication Technology Ltd. Patentee after: Lenovo (Beijing) Co., Ltd. Address before: No. 6, Pioneer Road, Haidian District information industry base, Beijing, China: 100085 Patentee before: Lenovo (Beijing) Co., Ltd. |
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