CN1901708A

CN1901708A - Device, method and chip and cell phone for realizing image data collection

Info

Publication number: CN1901708A
Application number: CNA2006100613326A
Authority: CN
Inventors: 季渊; 陈庆
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2006-06-26
Filing date: 2006-06-26
Publication date: 2007-01-24
Anticipated expiration: 2026-06-26
Also published as: CN100531311C

Abstract

This invention provides a device for realizing image data collection including: an image input interface receiving input image data, a FIFO unit storing image data temporarily, a FIFO control unit storing said image data in said FIFO unit and fetching said image data based on the idle situation of the bus to finish the transfer of clock domain, a channel controller fetching image data from said FIFO unit and selecting a suitable channel for the transfer of image data, a primary interface of the FI high performance bus outputting image data by the bus, a register stack controlling and selecting functions of the image input interface, the FIFI unit, the FIFO controller and said channel controller and a slave interface of the FI high performance bus configuring the register in said register stack. Besides, this invention also provides a method for realizing image data collection.

Description

A kind of device, method and chip and mobile phone of realizing image data acquiring

Technical field

The present invention relates to image processing techniques, exactly, relate to video interface device and its implementation among a kind of Camera (camera).

Background technology

At present more and more mobile phones begin to support camera function, and the image pickup processing unit framework of cell phone system generally comprises image processing subsystem and imageing sensor SOC (System On Chip, SOC (system on a chip)) chip.

Imageing sensor SOC chip general integrated imageing sensor, original image data are handled (as the conversion between RGB and the YUV, Y/C upholds, γ proofreaies and correct etc.), function such as image output format adjustment, imageing sensor SOC chip also provides video interface in addition, and it is according to certain video protocols output digital image.

Image processing subsystem requires to finish the reception and the processing of Camera view data, and it comprises image data interface and image applications software processes device can be provided.Image applications software processes device can be finished by one or more pieces SOC in the mobile phone, and image data interface generally is integrated in certain a slice SOC chip.

Fig. 1 has provided a kind of existing image processing system, and image processing subsystem and video interface in this system (Camera interface) modular design is in a SOC.The view data of video interface images acquired transducer (Camera Sensor) output, transmit standard according to certain data format and bus, send view data to image processing subsystem, and this technical scheme is higher to the degree of dependence of microprocessor, need to rely on software or DMA (direct memory access (DMA)) mode to accept view data, thereby bus load is heavier, processing capability in real time is not strong, cause processing speed slower, maximum pixel that in addition can the acceptance pattern picture is also restricted, can only accept the camera of less type, applicability is relatively poor, and power consumption is bigger.

Summary of the invention

The object of the invention is to provide a kind of device, method that realizes image data acquiring, strengthens image receiving ability and disposal ability, alleviates processor burden and bus load.

Another object of the present invention is further to provide chip that is integrated with described realization image data acquiring device and the mobile phone that uses this chip.

The device of realization image data acquiring provided by the invention comprises: the image input interface receives the view data of importing; Cell fifo, storing image data; The FIFO control unit deposits view data in described cell fifo, and the change over clock territory; Channel controller, reads image data from described cell fifo, and the transmission of view data selected suitable channel; The Advanced High-performance Bus main interface is exported view data by Advanced High-performance Bus; Register file is controlled and function selecting described image input interface, described cell fifo, described fifo controller unit and described channel controller; Advanced High-performance Bus is configured the register in the described register file from interface.

Described video interface device also comprises: graphics processing unit, receive the control of described register file, and the view data that described image input interface receives is handled, and the view data after will handling is stored in the described cell fifo by the FIFO control unit.

Described video interface device also comprises: the Interrupt Process unit, receive the control of described register file, and handle multiple interruption.

Described image input interface is positioned at the camera clock zone, and described channel controller, AHB Master Interface, register file and AHB Slave interface are positioned at the Advanced High-performance Bus clock zone.

Described channel controller comprises: data flow control, read the view data in the described cell fifo, and described view data is happened suddenly to transmit handle; MUX is carried out channel arbitration to the transmission of view data.

Described data flow control comprises: image data controller Y, image data controller U and image data controller V, read Y passage, U passage and V channel image data in the described cell fifo respectively, and the transmission that happens suddenly is handled.

Described cell fifo comprises: Y FIFO, U FIFO and V FIFO, store Y passage, U passage and V channel image data respectively; Described FIFO control unit comprises: the Y fifo controller deposits the Y channel image data in Y FIFO; The U fifo controller deposits the U channel image data in U FIFO; The VFIFO controller deposits the V channel image data in V FIFO.

A kind of method that realizes image data acquiring provided by the invention may further comprise the steps: Advanced High-performance Bus is configured a plurality of registers the register file from interface; The image input interface receives the view data of input according to configuration result; The FIFO control unit according to configuration result with image data storage in cell fifo; Channel controller is according to configuration result reads image data from cell fifo, and selects suitable passage to transmit; The Advanced High-performance Bus main interface is exported view data.

Described passage comprises Y passage, U passage and V passage, the suitable passage of described selection is specially: be set under the situation of fixed priority scheme at Y passage, U passage and V passage, the storage modes different according to view data carry out channel selecting according to the priority orders that is provided with; Perhaps be set under the situation of circular priority pattern, based on the different the highest passages of policy selection priority at Y passage, U passage and V passage.

Described strategy is for to select according to data volume in the passage, and the passage that data volume is maximum occupies the highest priority; Perhaps described strategy waits for that for to select in proper order according to the passage most recently used passage at most occupies the highest priority.

Described image input interface is specially according to the view data that configuration result receives input: the Interrupt Process unit detects register and upgrades interruption; Image data frame to input carries out information configuration; Image data frame after the reception information configuration.

Also comprise after the image input interface receives the view data of importing according to configuration result: graphics processing unit is handled the view data that described image input interface receives.

A kind of chip provided by the invention is integrated with the device of realizing image data acquiring in the described chip, the device of described realization image data acquiring comprises: the image input interface receives the view data of importing; Cell fifo, storing image data; The FIFO control unit deposits view data in described FIFO, and the change over clock territory; Channel controller, reads image data happens suddenly to transmit and handles from described cell fifo, and channel arbitration is carried out in the transmission of view data; The Advanced High-performance Bus main interface is exported the view data that described channel controller burst transmits after handling by Advanced High-performance Bus; Register file is controlled and function selecting described image input interface, described cell fifo, described fifo controller unit and described channel controller; Advanced High-performance Bus is configured the register in the described register file from interface.

A kind of mobile phone provided by the invention has at least a chip to be integrated with the device of realizing image data acquiring in the chip that described mobile phone uses, the device of described realization image data acquiring comprises: the image input interface receives the view data of importing; Cell fifo, storing image data; The FIFO control unit deposits view data in described FIFO, and the change over clock territory; Channel controller, reads image data happens suddenly to transmit and handles from described cell fifo, and channel arbitration is carried out in the burst transmission of view data; The Advanced High-performance Bus main interface is exported the view data that described channel controller burst transmits after handling by Advanced High-performance Bus; Register file is controlled and function selecting described image input interface, described cell fifo, described fifo controller unit and described channel controller; Advanced High-performance Bus is configured the register in the described register file from interface.

The present invention program is by being configured the register in the register file, can realize control and function selecting to image input interface, cell fifo, fifo controller unit and channel controller, can support Y, U, V triple channel transfer of data, optimized image data transmission mechanism, reduced bus and waited for load.

The invention provides an image input interface unit and a cover image acceptance mechanism, can accept the view data of the multiple form of camera output easily, finish functions such as image storage, image preview.

The present invention has strengthened view data greatly and has handled bandwidth by three road FIFO image data channels are provided, and has optimized image data transmission mechanism, improved the image ability to accept, reduce bus load, can accept the image of higher pixel, can support the image pixel more than 1,600 ten thousand.

The present invention is built-in Digital Image Processing unit, can finish image arbitrary proportion convergent-divergent, the image yuv data is converted to image algorithms such as RGB data, Y/C extension, image brightness, colourity, contrast adjustment, image Gamma correction, flating processing, image alpha mixing, image sharpening, image passivation, has promoted image-capable.

The present invention is by built-in special image processing unit, can handle in real time input picture, and unnecessary elder generation with image data storage behind memory, read described view data by microprocessor or other special image processing units then and carry out image processing, thereby avoided entire image storage is once read once again, reduced the data payload of memory, significantly the elevator system performance.

The present invention disposes by the different passage priority of accepting is provided, and has reduced the possibility of overflowing of accepting view data, and has strengthened continuity and reliability that image is accepted.

In addition, multiple register configuration that the present invention is integrated provides abundant camera interface type, can support multiple camera.

Description of drawings

Fig. 1 is a prior art image processing system schematic diagram;

Fig. 2 is an interface signal block diagram of realizing the image data acquiring device among the first embodiment of the invention and second embodiment;

Fig. 3 is a block diagram of realizing the image data acquiring device in the first embodiment of the invention;

Fig. 4 is a block diagram of realizing the image data acquiring device in the second embodiment of the invention;

Fig. 5 is a deposit data mode schematic diagram under the YUV pattern;

Fig. 6 is a channel arbitration schematic diagram among the present invention;

Fig. 7 is an image interface unit hardware fundamental diagram among the present invention;

Fig. 8 is image interface unit software workflow figure among the present invention;

Fig. 9 is the embodiment that the present invention is integrated with the chip of realizing the image data acquiring device;

Figure 10 is the capable sequential chart of chip operation shown in Figure 9;

Figure 11 is the frame sequential chart of chip operation shown in Figure 9;

Figure 12 is an embodiment of the present invention's mobile phone of disposing chip shown in Figure 9.

Embodiment

The present invention reduces bus and waits for load in order to optimize image data transmission mechanism, utilizes Advanced High-performance Bus from interface a plurality of registers the register file to be configured; The image input interface receives the view data of input according to configuration result; The FIFO control unit according to configuration result with image data storage in cell fifo; Channel controller is selected suitable passage to happen suddenly and is transmitted processing according to configuration result reads image data from cell fifo; View data output after the Advanced High-performance Bus main interface will happen suddenly and transmit handle.

In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.

See also shown in Figure 2ly, realize among the first embodiment of the invention and second embodiment that the device of image data acquiring is that video interface device (AVIU) mainly comprises four class interfaces: image input interface, Advanced High-performance Bus main interface (AHB Master Interface), Advanced High-performance Bus are from interface (AHB Slave interface) and interrupt interface.The image input interface is used to receive view data, comprises row, column synchronizing signal, data-signal, master slave mode selection signal etc.; The Advanced High-performance Bus main interface is used for exporting view data to ahb bus; Advanced High-performance Bus is used for accessing video interface arrangement internal register from interface; Interrupt interface is an interrupt signal output, can be combination interruption output, also can be that independent interruption of separating exported.

See also shown in Figure 3ly, comprise in the video interface device in the first embodiment of the invention that image input interface, graphics processing unit, cell fifo, FIFO control unit, data flow control (IMAC), MUX (MUX), the register file that comprises a plurality of registers, Advanced High-performance Bus main interface, Advanced High-performance Bus are from interface and Interrupt Process unit.Wherein cell fifo further comprises YFIFO, U FIFO and V FIFO, and is corresponding, and the FIFO control unit comprises Y fifo controller, U fifo controller and V fifo controller, and data flow control also correspondingly comprises Y IMAC, UIMAC and V IMAC.Wherein image input interface and graphics processing unit are positioned at image clock territory (camera clock zone), and Y IMAC, U IMAC and V IMAC, MUX, AHB Master Interface, AHB Slave interface, register file and Interrupt Process unit are positioned at the Advanced High-performance Bus clock zone.

The image input interface receives the view data of imageing sensor (not showing among the figure) output, and just the VI interface signal is delivered to graphics processing unit with view data; A state machine is arranged in the image input interface in addition, this state machine is partly stored (crop) with the image window that needs in the input picture to store and is got off, briefly, a line address counter and a column address counter are arranged in this state machine, in the time of among count value drops on target image, state machine will get off storage, sits when being listed as Y if count value has surpassed the row-coordinate X and the row of target window, and these view data that exceed part are dropped.Graphics processing unit is handled the view data of input, be converted to image algorithms such as RGB data, Y/C extension, image brightness, colourity, contrast adjustment, image Gamma correction, flating processing, image alpha mixing, image sharpening, image passivation as image arbitrary proportion convergent-divergent, image yuv data, its processing procedure is disclosed by prior art, no longer describes in detail here; The FIFO control unit will be handled the back view data through graphics processing unit and deposit cell fifo in, and read described view data according to the bus idle condition, thereby carry out the conversion of image clock territory and Advanced High-performance Bus clock zone, the existing multiple technologies scheme of this conversion can realize, also no longer describes in detail herein.Data flow control (IMAC) reads the view data in the cell fifo, selects suitable transmission means such as burst transfer mode that view data is transmitted processing; MUX (MUX) is carried out channel arbitration to the burst transmission of view data; Advanced High-performance Bus main interface (AHB MASTER interface) will happen suddenly transmit to handle and arbitration after view data by Advanced High-performance Bus (AHB MASTER) output; Register file comprises a plurality of registers, and to image input interface, graphics processing unit, cell fifo, fifo controller unit, data flow control and MUX are controlled and function selecting; Advanced High-performance Bus is from interface, and the signal that receives CPU (not showing among the figure) transmission is configured a plurality of registers in the register file.

The video interface device can be supported three kinds of data storage methods in the present embodiment: RGB pattern, YUV pattern, YC pattern.Under the RGB pattern, only a data passage Y passage is effective, and all data will be stored in a slice memory headroom continuously this moment, just among the Y FIFO, this pattern is applicable to the continuous occasion of storing of view data such as LCD demonstrations, initial data (Raw data) processings.Under the YUV pattern, Y, U, three data passages of V are all effective, all data, press planar IMC1, IMC2, IMC3 or IMC4 mode as shown in Figure 5, be stored in three memory headrooms, just among Y FIFO, U FIFO and the V FIFO, this pattern is applicable to view data processing such as JPEG compression, MPEG compression.Under the YC pattern, brightness Y and chrominance C will take two passages wherein, as Y passage and U passage, be stored in three memory headrooms by planarIMC1, IMC2, IMC3, IMC4, YV12 as shown in Figure 5, be Y FIFO, U FIFO and V FIFO accordingly or press planar NV12 mode, being stored in two memory headrooms, is Y FIFO and U FIFO accordingly.Because storage mode is disclosed by prior art shown in Fig. 5, no longer specifically introduce herein.

Under the YUV pattern, Y, U, these three passages of V can work alone, and its control signal is sent by the image input interface, and view data is sent by graphics processing unit.After each passage is enabled, all will catch in the video flowing valid data just, be saved in each self-corresponding FIFO after, and be synchronized to system's Advanced High-performance Bus clock zone by the fifo controller of correspondence.The quantitative data of storage quota in FIFO, corresponding IMAC just will send data transfer request to Advanced High-performance Bus.

See also shown in Figure 4ly, comprise in the video interface device in the second embodiment of the invention that image input interface, graphics processing unit, cell fifo, FIFO control unit, data flow control (IMAC), MUX (MUX), register file, Advanced High-performance Bus main interface, Advanced High-performance Bus are from interface and Interrupt Process unit.Wherein cell fifo further comprises Y FIFO, U FIFO and VFIFO, and is corresponding, and the FIFO control unit comprises Y fifo controller, U fifo controller and VFIFO controller.Wherein image input interface and graphics processing unit are positioned at image clock territory (camera clock zone), and data flow control, MUX, Advanced High-performance Bus main interface, Advanced High-performance Bus are positioned at the Advanced High-performance Bus clock zone from interface, register file and Interrupt Process unit.

Compare with first embodiment, data flow control does not split into three in the present embodiment, and data flow control is positioned at after the MUX, before the Advanced High-performance Bus main interface.Because each functions of modules does not change in the video interface device, no longer describe in detail herein.

Be understood that, also Y FIFO, U FIFO and VFIFO among first embodiment and second embodiment can be merged into a cell fifo, and design the function that a comparatively complicated FIFO control unit merges YFIFO control unit, U FIFO control unit and V FIFO control unit.

The implementation method of video interface device provided by the invention mainly may further comprise the steps:

Advanced High-performance Bus is configured a plurality of registers the register file from the signal that interface receives the CPU transmission.

The image input interface goes to receive the view data of imageing sensor input according to the register file configuration result.

The FIFO control unit according to the register file configuration result with image data storage in cell fifo.

MUX is selected suitable passage according to the register file configuration result.

Data flow control reads the view data in the cell fifo.

View data output after the Advanced High-performance Bus main interface will happen suddenly and transmit handle.

See also shown in Figure 6, Fig. 6 has disclosed among the first embodiment of the invention and second embodiment MUX and has carried out the channel arbitration process, just select the process of appropriate channel, MUX is provided with arbitration state machine, determines by the priority of judging channel request current Advanced High-performance Bus main interface by which passage is taken.Usually arbitration state machine has fixed priority (using numeral among the figure) and two kinds of operating states of repeating query priority (using letter representation among the figure).

When fixed priority, after resetting, arbitration state machine is in idle condition.Arbitration state machine adopts different state exchange mechanism according to different data storage methods.

Under the YUV pattern, Y, U, three passages of V are all effective.State machine carries out state according to 1 → 2 → 3 → 4 order and switches.After the V channel data transmitted and finishes, in order to save the clock cycle, the Y passage sent data transmission requests at once, and then state machine carries out according to 1 → 2 → 3 → 5 order.

Under the YC pattern, two passages of Y, U are all effective, and the Y passage is used to deposit brightness data, and the U passage is as depositing chroma data.State machine carries out state according to 1 → 2 → 6 order and switches.After the U channel data transmitted and finishes, in order to save the clock cycle, the Y passage sent data transmission requests at once, and then state machine carries out according to 1 → 2 → 7 order.

Under the RGB pattern, only the Y passage is effective.State machine carries out according to 1 → 8 order.

When repeating query priority, after resetting, arbitration state machine is in idle condition.The priority of Y, U, three passages of V has characteristic by turns.Select to have two kinds of strategies by turns: a kind of is that another kind is by passage most recently used rank order by the ordering of the data volume in the passage FIFO.

Press the data volume ordering strategy in the passage FIFO, be that the interior data volume of current which passage FIFO is maximum, this passage just occupies the highest request of data priority, for example works as the interior data volume of Y FIFO the most for a long time, and arbitration state machine just selects the Y passage to take the Advanced High-performance Bus main interface.

By passage most recently used rank order strategy be, after some passages were asked, the priority of this passage was reduced to minimum, and the priority of the passage of original priority is upgraded to the highest wait just passage at most and occupies the highest priority.For example original priority is U, V, Y, and after then the U channel data transmit to finish, priority was reduced to minimum, the V passage since the stand-by period at most, priority becomes the highest, prioritization becomes V, Y, U.

The present invention selects according to the data volume ordering strategy in the passage FIFO earlier when carrying out the passage prioritization, selects according to passage most recently used rank order strategy when data volume is identical again.Because by the priority that ceaselessly automaticallyes switch, make the priority of each data channel equal as far as possible, thereby can make full use of the FIFO of each passage, reduce the data that some passages cause because data bandwidth is too small and overflowed risk, particularly the data in the FIFO of some passages are overflowed under the extreme case, and the FIFO of another passage is empty possibility.

See also shown in Figure 7ly, Fig. 7 has disclosed the working principle of hardware that image interface unit in the video interface device receives view data.

After the image input interface is enabled, wait for the arrival of frame synchronizing signal; After receiving frame synchronizing signal, judge whether the register updated space is updated, if not, enter sleep state and continue to wait for frame synchronizing signal; If the configuration information that register file utilizes CPU to send upgrades a plurality of registers, and the register value after will upgrading is that configuration information sends the image input interface to; The image input interface begins to receive the view data that camera sensor sends according to configuration information after receiving configuration information, and judges whether to occur unusual; If, carry out abnormality processing, if not, wait the current frame image Data Receiving back that finishes to produce Data Receiving and finish interruption; Judge whether to continue to receive the next frame image then, if proceed to receive, otherwise receiving course finishes.

See also shown in Figure 8ly, Fig. 8 has disclosed image interface unit software workflow in the video interface device.

Processor at first disposes camera sensor, just imageing sensor is carried out initialization.

Then the image interface unit is carried out initialization, specifically comprises: configurable clock generator and reset, configuration control register, configuration image property register, configuration image memory address and the register updated space is set.

CPU waits for interruption, and judges interrupt type.

Interrupt if register upgrades, the expression register is updated, and CPU judges whether the configuration information (mainly comprising image memory address and image size) of next frame image is identical with present frame, as if identical, directly disposes the memory address of next frame image; If inequality, elder generation disposes the transmission mode and the image attributes of next frame, disposes the memory address of next frame image again; Then the register updated space is provided with once more and continues to wait for and interrupt.

If aborted is carried out aborted and is handled;

If data are accepted to finish interruption, represent that a frame normally finishes receiving, CPU handles the view data of present frame; Judge whether to receive the next frame image then, if continue to wait for and interrupt; If not, closing image input interface (camera IF); Finish image data transmission.

Wherein aborted comprises the interruption of ahb bus mistake: image has exceeded the effective address scope, can reassign the storage first address, or distributes bigger image storage space;

Frame data are lost interruption: all abandon present frame;

FIFO overflows interruption: comprise that data fifo overflows interruption and the FIFO request signal overflows interruption.These two kinds of FIFO overflow the average bandwidth that all shows internal data can not satisfy the real-time Transmission requirement.Suitably improve CAM_CLK (concrete implication sees also table 1), reduce data volume, increase the ranks blanking time or improve the internal bus bandwidth, can avoid FIFO to overflow;

Overflow interruption in the ranks: data line is not stored and is finished, and new data line arrives.The data of newline will cover the previous row data.Suitably increase blanking signal in the ranks, perhaps reduce CAM_CLK, can avoid overflowing interruption in the ranks.

Work is interrupted, interrupted and data are accepted to finish interruption except above-mentioned register upgrades, also comprise the initial interruption of frame, be used for indication and detect frame synchronizing signal, a new frame begins, and the start of line interrupts, and is used for indicating detecting nominated bank.

The explanation of table 1 video interface device pin

The pin title	Direction	Implication
The pin title	Direction	Implication	CAM_DATA[9:0]	Input	The 10 bit image data input of AVIU.Data compatibility 8 bit data bus.Most-significant byte or least-significant byte compatibility are by register configuration.
CAM_PCLK	Input	The clock input of AVIU.	CAM_DATA[9:0]	Input
CAM_PCLK	Input	The clock input of AVIU.	CAM_HSYNC	Input	The horizontal-drive signal input of AVIU.
CAM_VSYNC	Input	The vertical synchronizing signal input of AVIU.	CAM_HSYNC	Input	The horizontal-drive signal input of AVIU.
CAM_VSYNC	Input	The vertical synchronizing signal input of AVIU.	CAM_CLK	Output	The CAM clock output of SystemController can be adopted the 1-32 frequency-dividing clock output of system bus clock.

See also shown in Figure 9ly, be integrated with an embodiment of the chip of video interface device in the frame of broken lines for the present invention, this chip comprises 5 pins at least, and wherein four be input pin, and one is output pin (specifically implication is asked for an interview table 1).AVIU refers to the video interface device among the figure; Camerasensor refers to imageing sensor, produces image pixel clock CAM_PCLK, picture frame synchronizing signal CAM_VSYNC, image line synchronizing signal CAM_HSYNC, view data CAM_DATA[9:0], view data also can be 8 with 10, adopts 10 here.Chip internal also comprises system controller (SystemController), is used to provide the work clock CAM_CLK of camerasensor.

See also shown in Figure 10ly, Figure 10 has disclosed the capable sequential chart that the present invention is integrated with the chip operation of video interface device.Blanking is the blanking data, P0, P1 ... Pn is the view data of every row.When CAM_HSYNC was effective, the image interface device was the view data of every row in the data of the rising edge sampling CAM_DATA of CAM_PCLK.The significant level of CAM_HSYNC can be disposed by control register, is that high level is effective among the figure.

See also shown in Figure 11ly, Figure 11 has disclosed the frame sequential chart that the present invention is integrated with the chip operation of video interface device.When CAM_VSYNC is effective, internal signal FramePulse will produce the frame synchronizing signal of a clock cycle width, represent that a frame begins.PreB and PostB are respectively blanking time and the frame final blanking time before the frame, and LTIME is row effective time, and LBLK is blanking time in the ranks, and FBLK is the interframe blanking time, and these five parameters are determined by the imageing sensor input signal.The effective edge of CAM_VSYNC is that rising edge is effective among the figure along being disposed by control register.

See also shown in Figure 12ly, Figure 12 provides an embodiment and this mobile phone image processing process of the mobile phone that disposes chip shown in Figure 8.This mobile phone comprises imageing sensor (Camera sensor), video interface device (AVIU), arm processor, lcd controller, LCD, RAM controller and RAM, comprises ARM_DAHB bus and CAM_AHB bus in addition.Image processing process is specific as follows,

Step 1., the data mode of arm processor configuration image transducer and video interface device is RGB, the video interface device is by the CAM_AHB bus, with the RGB transfer of data to the RAM controller, as MPMC, SSMC etc.;

Step 2., after every frame RGB storage was finished, the video interface device sent interruption, notice ARM present frame is accepted to finish;

Step 3., arm processor is read the RGB data of present frame in the RAM controller, and makes corresponding data processing, as form adjustment etc.; If do not deal with, then step 1. in the view data lcd controller that writes direct, as EMI;

4. step transfers to lcd controller with the RGB data after handling by ARM_DAHB and is used for showing;

Step 5., when carrying out camera function (image storage), the data mode of arm processor configuration image transducer and video interface device is YUV, the video interface device passes through the CAM_AHB bus, and yuv data is transferred to the RAM controller;

Step 6., after the storage of every frame yuv data was finished, the video interface device sent interruption, notice ARM present frame is accepted to finish;

Step 7., arm processor is read the yuv data of present frame in the RAM controller, and makes corresponding data processing, as JPEG compression etc.;

Step 8., the image data storage after ARM will dispose is in nonvolatile memory such as Flash ROM etc.

The video interface device that the present invention program provides can bring following beneficial effect:

1, the invention provides an image input interface unit and a cover image acceptance mechanism, can accept easily the view data of the multiple format of camera output, finish the functions such as image storage, image preview.

2, provide the several data storage mode, can carry out packed (compress mode) and planar (spatial dispersion mode) storage mode to the input data, be conducive to software or the hardware module image data processing of different system;

3, by integrated built-in graphics processing unit can finish image arbitrary proportion convergent-divergent, image YUV data are converted to the image algorithms such as RGB data, Y/C extension, brightness of image, colourity, contrast adjustment, image Gamma correction, flating processing, image alpha mixing, image sharpening, image passivation, have promoted image-capable.

4, the present invention is by providing three road FIFO image data channels, greatly strengthen view data and processed bandwidth, optimized image data transmission mechanism, improved the image ability to accept, reduce bus load, can accept the image of higher pixel, and by providing the different passage priority of accepting to dispose, reduce the possibility of overflowing of accepting view data, strengthened continuity and reliability that image is accepted.

5, the present invention is built-in Digital Image Processing unit, the present invention is by built-in special image processing unit, can process in real time input picture, and unnecessary store view data into memory first after, then read described view data by microprocessor or other special image processing units and carry out the image processing, thereby avoided entire image storage is once read once again, reduced the data payload of memory, significantly the elevator system performance.

The above only is preferred embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1, a kind of device of realizing image data acquiring is characterized in that, comprising:

Advanced High-performance Bus is from interface, in order to transmit the configuration information of CPU;

Register file comprises a plurality of registers, is respectively applied for to receive the configuration information that CPU sends from interface by described Advanced High-performance Bus;

The image input interface is used for receiving the view data of importing according to described configuration information;

Cell fifo is used for according to the temporary described view data of described configuration information;

The FIFO control unit is used for depositing described view data in described cell fifo according to described configuration information, and reads described view data according to the Advanced High-performance Bus idle condition, thereby carries out the conversion between first clock zone and the second clock territory;

Channel controller according to described configuration information reads image data from described cell fifo, and is the transmission selective channel and the load mode of view data;

Advanced High-performance Bus main interface, the view data that will send by the channel of described selection utilize Advanced High-performance Bus output;

Wherein, described image input interface is positioned at first clock zone, and described channel controller, Advanced High-performance Bus main interface, register file and Advanced High-performance Bus are positioned at the second clock territory from interface.

2, the device of realization image data acquiring as claimed in claim 1 is characterized in that, described device also comprises:

Graphics processing unit is handled the view data that described image input interface receives according to described configuration information, and the image data storage after will handling by described FIFO control unit is in described cell fifo.

3, the device of realization image data acquiring as claimed in claim 1 is characterized in that, described device also comprises:

The Interrupt Process unit according to described configuration information, produces multiple interruption and sends to CPU.

As the device of claim 1 or 2 or 3 described realization image data acquirings, it is characterized in that 4, described channel controller comprises:

MUX is carried out channel arbitration to the transmission of described view data, selects suitable passage;

Data flow control reads the view data in the described cell fifo, and by the passage that described MUX is selected described view data is happened suddenly to transmit and handle.

5, the device of realization image data acquiring as claimed in claim 4, it is characterized in that, described data flow control comprises: image data controller Y, image data controller U and image data controller V, be respectively applied for the Y passage, U passage and the V channel image data that read in the described cell fifo, and the transmission that happens suddenly is handled.

6, as the device of claim 1 or 2 or 3 described realization image data acquirings, it is characterized in that,

Described cell fifo comprises: Y cell fifo, U cell fifo and V cell fifo are respectively applied for storage Y passage, U passage and V channel image data;

Described FIFO control unit comprises:

The Y fifo controller is used for depositing the Y channel image data in Y FIFO;

The U fifo controller is used for depositing the U channel image data in U FIFO;

The V fifo controller is used for depositing the V channel image data in V FIFO.

7, a kind of method that realizes image data acquiring is characterized in that, may further comprise the steps:

CPU sends configuration information from interface to a plurality of registers the register file by Advanced High-performance Bus;

The configuration information that the image input interface receives according to register file receives the view data of input;

The FIFO control unit according to the configuration information of register file with image data storage in cell fifo;

Channel controller is according to configuration information reads image data from cell fifo of register file, and selects suitable channel to transmit;

The Advanced High-performance Bus main interface will utilize Advanced High-performance Bus output by the view data that described suitable channel sends.

8, the method for realization image data acquiring as claimed in claim 7 is characterized in that, described passage comprises Y passage, U passage and V passage, and described channel controller selects suitable channel to be specially:

Be set under the situation of fixed priority scheme at Y passage, U passage and V passage, the storage modes different according to view data carry out channel selecting according to the priority orders that is provided with; Perhaps

Be set under the situation of circular priority pattern at Y passage, U passage and V passage, based on the different the highest passages of policy selection priority.

9, the method for realization image data acquiring as claimed in claim 8 is characterized in that, institute

State strategy for to select according to data volume in the passage, the passage that data volume is maximum occupies the highest priority; Perhaps

Described strategy waits for that for to select in proper order according to the passage most recently used passage at most occupies the highest priority.

As the method for claim 7 or 8 or 9 described realization image data acquirings, it is characterized in that 10, described image input interface specifically comprises according to the view data of the configuration result reception input of register file::

Image input interfaces etc. are by the time frame synchronizing signal;

Register (what value is best illustrated be) value after a plurality of registers upgrade in the image input interface receiving register heap;

Register (what value is best illustrated be) value after the image input interface upgrades according to described a plurality of registers receives the view data of input;

The image input interface is finished the reception of present frame and is produced and interrupts.

11, the method for realization image data acquiring as claimed in claim 10 is characterized in that, also comprises before the value after a plurality of registers upgrade in the described image input interface receiving register heap:

Register file detects the register updated space and is refreshed, and the configuration information of described a plurality of registers is upgraded.

12, as the method for claim 7 or 8 or 9 described realization image data acquirings, it is characterized in that, also comprise after the view data of described image input interface according to the configuration information reception input of register file:

Graphics processing unit carries out Digital Image Processing to the view data that described image input interface receives.

13, a kind of chip is characterized in that, is provided with the device of realizing image data acquiring in the described chip, and the device of described realization image data acquiring comprises:

The Advanced High-performance Bus interface is in order to transmit the configuration information of CPU;

Register file comprises a plurality of registers, accepts the configuration information that CPU sends from interface by described Advanced High-performance Bus;

The image input interface receives the view data of importing according to described configuration information;

Cell fifo is stored described view data according to described configuration information;

The FIFO control unit deposits described view data in described cell fifo according to described configuration information, and reads described view data according to the bus idle condition, thereby carries out the conversion between first clock zone and the second clock territory;

The Advanced High-performance Bus main interface will utilize Advanced High-performance Bus output by the view data that described suitable channel sends;

14, chip as claimed in claim 13 is characterized in that, the device of described realization image data acquiring also comprises:

According to described configuration information the view data that described image input interface receives is carried out Digital Image Processing, and the image data storage after will handling by the FIFO control unit is in described cell fifo.

15, as claim 13 or 14 described chips, it is characterized in that, realize that the device of image data acquiring also comprises:

16, a kind of mobile phone is characterized in that, described mobile phone is provided with a device of realizing image data acquiring at least, and the device of described realization image data acquiring comprises: