CN1461990A

CN1461990A - Programming auxiliary control instrument of field programmable device

Info

Publication number: CN1461990A
Application number: CN 01145588
Authority: CN
Inventors: 方志宏; 刘浩; 吴誉
Original assignee: Baoshan Iron and Steel Co Ltd
Current assignee: Baoshan Iron and Steel Co Ltd
Priority date: 2001-12-29
Filing date: 2001-12-29
Publication date: 2003-12-17
Anticipated expiration: 2021-12-29
Also published as: CN1223932C

Abstract

An auxiliary programming control unit for the field programmable device (FPGA) is composed of a programming controller, a field programmable device (FPGA), and a decoder. Said programming controller has a combined encoded signal output. Said FPGA has programming control signal input, clock signal input and data signal input. Said decoder is connected between said combined encoded signal output of programming controller and the relative input of FPGA. Its advantages are simple circuit and high reliability.

Description

The programming auxiliary control instrument of field programmable device

Technical field

The present invention relates to the online programming device of a kind of field programmable device (FPGA), specifically, is a kind of programming auxiliary control instrument.

Technical background

The FPGA device be one rising gradually, popular a kind of components and parts.In many occasions purposes is widely arranged, for example: instrument and meter for automation, fields such as communication.Particularly the instrument of hand-held, portable, pocket, miniaturization and equipment etc. are its following very important applications, and bigger profit margin is arranged, and the FPGA device is used for portable apparatus equipment, improves the value of these products greatly.

Spartan Series FPGA with Xilinx is an example, at present, the FPGA device is carried out online programming, generally all need have 4 control signal wires, i.e. PROG (programming signal), CLK (clock signal), Data (data-signal), Done (finishing signal).Shown in Fig. 1-1 and Fig. 1-2, they are respectively common FPGA download circuit synoptic diagram and signal sequence synoptic diagram.Fig. 1-1 has shown a standard programming circuit.Circuit middle controller 1 has used 4 control signal PROG, CLK, Data, DONE.Shown in Fig. 1-2, the 1. at first initialization of Prog signal controlling FPGA2, the low level of a Prog signal makes FPGA2 enter the programming state, and in programming process and in the later operational process, the Prog signal keeps high level; 2. in programming process, the Data signal cooperates with the CLK signal, rising edge at each CLK signal, FPGA2 locks/reads a Data signal, so circulation is all delivered among the FPGA2 up to the program that controller 1 will need to programme, and 3. works as FPGA2 and correctly receives after the program, will produce a DONE signal, all finish notice programmable controller 1.This circuit is a circuit than standard, for the certain applications occasion, it still is proper, but for the very little application of hand-held instrument equidimension, perhaps controller 1 itself has only the application of 1～2 I/O control line, the Prog signal and the CLK signal that are programmable controller 1 output are exported by a P/C/D assembly coding signal control line by Prog signal, CLK signal and the Data signal of a P/C assembly coding signal control line output or its output, so, above-mentioned preferred circuit, perhaps similar with it circuit just can't have been used.

Summary of the invention

The object of the present invention is to provide a kind of programming auxiliary control instrument of field programmable device,, have only the online programming problem of 1-2 bar I/O control line so that solve for small size or programmable controller such as hand-held instrument one class.

Technical scheme of the present invention is but that the respective input that a decoding unit connects the P/C or the P/C/D assembly coding signal output part of coding controller and accepts the scene coder spare of programming is set, can promptly be undertaken by shown in Fig. 1-1 and Fig. 1-2 when making it by the connected mode of common standard type to the field programmable device online programming.

As mentioned above, the present invention is achieved in that the field programmable device that it comprises programmable controller and accepts programming, and this programmable controller has assembly coding signal output part output assembly coding signal; This field-programmable device then has programming control signal input end, clock signal input terminal and data-signal input end, characteristics are, also have one the assembly coding signal decomposition become the decoding unit of corresponding independent component signal, its connect in three input ends in this assembly coding signal output part and this field programming device with decompose the corresponding input end of independent component, for example programming control signal input end;

The assembly coding signal of the assembly coding signal output part output of said this programmable controller is programming/clock composite signal or programming/clock/data combination signal, they export programming control signal and clock signal or programming control signal, clock signal and data-signal respectively after decoding unit decodes, and the corresponding programming control signal input end of difference this field programmable device of feed-in, clock signal input terminal or programming control signal input end, clock signal input terminal and data-signal input end;

Further, the width of the programming signal in the said assembly coding signal greater than the width of the width of programming control signal and this programming control signal greater than 5 times of clock signal periods or greater than the 5 haplotype data derations of signal;

Said decoding unit comprises programming decoding circuit and clock decoding circuit or programming decoding circuit, clock decoding circuit and data decode circuitry respectively by independent component situation that the assembly coding signal comprised;

Particularly, said programming decoding circuit comprises that the integrating circuit 311 be made up of resistance R 1 and capacitor C 1 and this integrating circuit certainly are connected the diode D1 of this assembly coding signal output part by a negative pole, and an output terminal connects the not gate U1 of programming control signal input end; Usually, the width of time constant R1 * C1＜1/5 programming signal;

Described clock decoding circuit is replaced by a lead that is connected that connects assembly coding signal output part and clock signal input terminal;

Said data decode circuitry, it comprises the integrating circuit of being made up of resistance R 2 and capacitor C 2, and be connected the input end of data-signal with its output terminal by the tie point that the input end of a not gate U2 connects this resistance R 2 and capacitor C 2, and the free end of this resistance R 2 connects the output terminal of this assembly coding signal.

Advantage of the present invention is that circuit structure is simple and reliable, has solved programmable controller very easily and has had only 1-2 bar I/O control signal wire to carry out the problem of online programming such as use field programmable devices such as hand-held, portable, pocket, small-sized instrument and equipment.

Description of drawings

Fig. 1-the 1st, the programming Control download circuit figure of existing field programmable device.

Fig. 1-2 is the programming control signal sequential chart of the field programmable device shown in Fig. 1-1.

Fig. 2-the 1st, but the programming Control download circuit synoptic diagram of scene of the present invention coder spare.

Fig. 2-the 2nd, the control signal sequential chart of the field programmable device shown in Fig. 2-1.

Fig. 3-the 1st, the programming Control download circuit synoptic diagram of another field programmable device of the present invention.

Fig. 3-the 2nd, the control signal sequential chart of the field programmable device shown in Fig. 3-1.

Fig. 4-be the embodiment circuit theory diagrams of the programming signal demoder among the present invention.

Fig. 4-the 2nd, the programming signal synoptic diagram among Fig. 4-1.

Fig. 5-the 1st, the embodiment circuit theory diagrams of the data-signal demoder among the present invention.

Fig. 5-the 2nd, the data-signal synoptic diagram among Fig. 5-1.

Embodiment

Provide two embodiment of the present invention respectively according to Fig. 2-1～Fig. 5-2 below, one of them is to be used for programmable controller, and two online programming control signals output-programming/clock P/C assembly coding signal and data Data signal are only arranged; Another is to be used for the assembly coding signal that programmable controller only has an online programming control signal output: programming/clock/data P/C/D.

Embodiment 1:

See also Fig. 2-1,2-2 and Fig. 4-1,4-2:

Present embodiment has provided a kind of a kind of FPGA programmed circuit of simplifying of simplifying shown in Fig. 2-1.The I/O control signal wire of controller 1 comprises P/C and Data.The P/C control signal produces the waveform shown in Fig. 2-1, shown in Fig. 4-1, obtain the Prog signal through the Prog decoding circuit, through CLK decoding circuit 32 in this example also can without, promptly by a lead that connects assembly coding signal output part 10 and clock signal input terminal 22, obtain the CLK signal, they form complete FPGA control signal with the Data signal, finish the programming Control to FPGA.

This circuit only uses 2 I/O control signal wires, lacks than the standard program circuit, utilizes the encoding and decoding of special control signal, obtains finishing the programing work of FPGA.

Among Fig. 2-1, assembly coding signal output part 10 in the connection programmable controller 1 and the programming control signal input end 21 in the field programmable device 2, decoding unit 3 between the clock signal input terminal 22, it comprises programming decoding circuit 31 and clock decoding circuit 32, decoding circuit and assembly coding signal such as Fig. 4-1 wherein programme, shown in the 4-2, P/C assembly coding signal is made up of Prog coded signal and CLK coded signal, among Fig. 4-1, programming decoding circuit 31 comprises integrating circuit 311 and diode D1 and the not gate U1 that is made up of resistance R 1 and capacitor C 1, this diode D1 just, negative pole connects integrating circuit 311 and assembly coding signal output part 10 respectively, and the input end of this not gate U1 is connected integrating circuit 311 and programming control signal input end 21 respectively with output terminal.Prog coding is the long high level of one-period, sees the t2-t0 of Fig. 4-2, and it is greater than the time constant τ of programming decoding circuit 31 _Prog, and the CLK coding is the short pulse of period ratio, less than the timeconstant of coding and decoding circuit 31 _ProgSo the Prog signal can decodedly obtain, the clock coded signal is then filtered.Generally can select Prog code period t2-t0＞5 τ _Prog, and clock code period t3-t2＜1/5 τ _ProgAfter the FPGA programming finished, the P/C signal should reset immediately, otherwise mistake can appear in programming.Resistance R 1=10K Ω in the present embodiment, capacitor C 1=0.1 μ F, diode D1 are 1N5817 type diode, and U1 is a 74HC14 type not gate.

Embodiment 2

See also Fig. 3-1,3-2, Fig. 4-1,4-2 and Fig. 5-1,5-2.

Present embodiment has provided a kind of FPGA programmed circuit of more simplifying shown in Fig. 3-1, and it uses an I/O control signal wire, and the assembly coding signal is P/C/D, and decoding unit 3 comprises programming decoding circuit 31, clock decoding circuit 32 and data decode circuitry 33.The difference of present embodiment and embodiment 1, only be to have increased a data decoding circuit 31, it is shown in Fig. 5-1, Fig. 5-2, this decoding circuit 33 comprises integrating circuit 331 and not gate U2 who is made up of resistance R 2 and capacitor C 2, the free end 3311 of this resistance R 2 connects this assembly coding signal output part 10, and this not gate U ₂Input end and output terminal be connected the resistance R 2 in this integrating circuit 331 and the tie point 3312 and the data-signal input end 23 of capacitor C 2 respectively.

Usually shown in Fig. 4-1,4-2, in P/C/D assembly coding signal, the Prog coding is the long high level of one-period, sees the t2-t0 of Fig. 4-1, and it is greater than the timeconstant of Prog decoding circuit _Prog, CLK (Data) coding is the short pulse of period ratio, less than the timeconstant of decoding circuit _ProgSo the Prog signal can decodedly obtain, other uncorrelated signals then are filtered.Generally can select Prog code period t2-t0＞5 τ _Prog, and CLK (Data) code period t3-t2＜1/5 τ _ProgAfter the FPGA programming finishes, the P/C signal, perhaps the P/C/D signal should reset immediately, otherwise mistake can appear in Prog.

The mechanism of Data decoding circuit 23 can be divided into Data=0 and two kinds of situations of Data=1:

During Data=0, when the rising edge t5 of the previous data of P/C/D signal finishes, and keep a period of time, arrive t6 after, continue to keep high level, through about τ _DataRelevant with original state, low level will appear in the Data control signal wire, and promptly signal 0, for more reliable, can wait a period of time, and the P/C/D signal provides a negative pulse again and is used for locking data during due in t9.Certainly the width of negative pulse should be narrow, otherwise the Data signal can reverse common negative pulse width t10-t9＜1/4 τ _CLK

During Data=1, when the rising edge t5 of the previous data of P/C/D signal finishes, and keep a period of time, arrive t6 after, enter low level immediately, through about τ _DataRelevant with original state, high level will appear in the Data control signal wire, and promptly signal 1, for more reliable, can wait a period of time, and during due in t10, the P/C/D signal provides a rising edge again and is used for locking data.

The Data signal also can be come out by decoding correctly like this.The decoding circuit 32 that the CLK signal need not be special in the present embodiment, the P/C/D signal can directly use as the CLK control signal.

In the present embodiment, R1=10K Ω, C1=0.1 μ F, R2=1K Ω, C2=0.01 μ F, D1 are 1N5817, U1/U2 is 74HC14.Can certainly adjust as required.

Claims

1, a kind of programming auxiliary control instrument of field programmable device, the field programmable device (2) that comprises programmable controller (1) and accept to programme, this programmable controller (1) contains an assembly coding signal output part (10); This field programmable device (2) contains programming control signal input end (21), clock signal input terminal (22) and data-signal input end (23), it is characterized in that, also have one the assembly coding signal decomposition become the decoding unit (3) of corresponding independent component signal, its connect in three input ends (21,22,23) in this assembly coding signal output part (10) and this field programming device (2) with the corresponding input end of decomposition independent component.

2, the programming auxiliary control instrument of field programmable device according to claim 1, it is characterized in that, the assembly coding signal of assembly coding signal output part (10) output of this programmable controller (1) is programming/clock composite signal or programming/clock/data combination signal, they export programming control signal and clock signal or programming control signal respectively after decoding unit (3) decoding, clock signal and data-signal, and the corresponding programming control signal input end (21) of difference this field programmable device of feed-in (2), clock signal input terminal (22) or programming control signal move into end (21), clock signal input terminal (22) and data-signal input end (23).

3, the programming auxiliary control instrument of field programmable device according to claim 2, it is characterized in that, the width of the programming signal in the said assembly coding signal greater than the width of the width of programming control signal and this programming control signal greater than 5 times of clock signal periods or greater than the 5 haplotype data derations of signal.

4, the programming auxiliary control instrument of field programmable device according to claim 1 and 2, it is characterized in that said decoding unit (3) comprises programming decoding circuit (31) and clock decoding circuit (32) or programme decoding circuit (31), clock decoding circuit (32) and data decode circuitry (33) respectively by independent component situation that the assembly coding signal comprised.

5, according to the programming auxiliary control instrument of claim 3 or 4 described field programmable devices, it is characterized in that, said programming decoding circuit (31) comprises that the integrating circuit (311) be made up of resistance R 1 and capacitor C 1 and this integrating circuit (311) certainly are connected the diode D1 of this assembly coding signal output part (10) by a negative pole, and an output terminal connects the not gate U1 of programming control signal input end (21).

6, field programmable device according to claim 5 and programming auxiliary control instrument, it is characterized in that described clock decoding circuit (32) is replaced by a lead that is connected that connects assembly coding signal output part (10) and clock signal input terminal (22).

7, the programming auxiliary control instrument of field programmable device according to claim 5, it is characterized in that, said data decode circuitry (33), it comprises the integrating circuit of being made up of resistance R 2 and capacitor C 2 (331), and be connected the input end (23) of data-signal with its output terminal by the tie point (3312) that the input end of a not gate U2 connects this resistance R 2 and capacitor C 2, and the free end of this resistance R 2 (3311) connects the output terminal (10) of this assembly coding signal.