CN1459827A - Manufacturing method of selective gate pole of gate separating type quickflash memory cell - Google Patents
Manufacturing method of selective gate pole of gate separating type quickflash memory cell Download PDFInfo
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Abstract
A process for preparing the selective grid of grid-splitted flash memory cell features that the selective grid is formed on the side wall of the channel on basic semiconductor material to reduce the transverse size of selective grid and keep the length of channel, and includes generating a channel in the basic semiconductor material at one side of suspended grid structure, generating a dielectric polysilicon layer on the suspended grid structure and side wall of channel, and generating a polysilicon spacer on the side wall of said dielectric polysilicon layer to obtain the selective grid. Its advantages are high write-in efficiency and low writing current.
Description
Technical field
The invention relates to a kind of semiconductor subassembly and processing procedure, particularly relevant for the manufacture method of the selection gate of a kind of gate separating type (Split-gate) flash memory cell.
Background technology
Typically, the data storage medium in the computer is broadly divided into volatility (Volatile) internal memory and non-volatile (Nonvolatile) internal memory two classes.Volatile memory includes DRAM (Dynamic Random Access Memory) (DRAM) and static random access memory (SRAM), the data that it deposited in can disappear because of power interruptions, so be mainly used in temporary data access, and non-voltile memory is after power-off, still can keep stored data, thereby can be applicable to the data storage of various different occasions.Non-voltile memory can be divided into again according to the data access mode: shade curtain read-only storage (MaskROM), EEPROM (EPROM), electronics EEPROM (EEPROM) and flash memory (Flash EEPROM) etc.
Since the flash memory of 256K since start to excel in 1987, flash memory has become the development main flow of non-voltile memory gradually.Flash memory is the close internal memory of the height that advantage developed out in conjunction with EPROM and EEPROM, have superior characteristics such as non-volatile, rewritable, high density and durability, very suitable portable computer and the telecommunications industry of being applied to, very have the scholar to foretell that flash memory will become the leading role who drives next stage semiconductor revolution, visible flash memory accounts for critical role in semi-conductor industry.
Typically, flash memory can be distinguished according to frame mode and be two kinds of gate separating type (Split-gate) flash memory and folded lock formula (Stack-gate) flash memories, and wherein the data of the gate separating type flash memory folded lock formula flash memory of speed of erasing is fast, so reuse for semiconductor industry now.General gate separating type flash memory cell structure comprise suspension gate structure, an a control grid/selection gate and of forming by gate pole oxidation layer/compound crystal silicon layer/oxide layer be formed between this suspension gate structure and the control grid/selection gate between the compound crystal silicon dielectric layer, because the compound crystal silicon layer of this suspension gate structure is not electrical connected with any electrode, so be called the suspension gate.The data of flash memory is erased and write activity can be by applying the combination of different voltage at control grid, source electrode, drain and base material, and electronics injected or shifts out the suspension gate.In order to make the gate separating type flash disk operation, select gate must cover distance between drain area (or source area) and the suspension gate at least, promptly by drain area or source area to the suitable distance of the essential maintenance between the gate of suspending with as the electronics channel.If channel length too in short-term, short channel effect (ShortChannel Effects) takes place easily, and channel length then can make and write deterioration of efficiency when oversize.
Along with semiconductor integration (Integration) with increase day by day, size of components is contracted to time micron or deep-sub-micrometer (＜.35 μ m) scope in response to trend.Because flash memory needs suitable channel length, cause the gate separating type flash memory of making the micro size that its degree of difficulty is arranged, therefore need a kind of new tool micro size of development and can keep the gate separating type flash memory structure of channel length, to address the above problem.
Summary of the invention
In view of the channel length that needs between source/drain in the above-mentioned known flash memory and the suspension gate to keep suitable, cause the size of flash memory structure to dwindle problems such as difficult, the present invention is the manufacture method that proposes a kind of selection gate of gate separating type flash memory cell, trench sidewall in semiconductor substrate forms the selection gate, to dwindle the lateral dimension of selecting gate and to keep channel length.
One of main purpose of the present invention is the manufacture method of selection gate that a kind of gate separating type flash memory cell is provided, be to be applied on the semiconductor base material, formed at least one suspension gate structure and one source pole district on this semiconductor substrate with gate pole oxidation layer/compound crystal silicon layer/first oxide layer, this method comprises the following step at least: form irrigation canals and ditches in this semiconductor substrate of a side of this suspension gate structure, these irrigation canals and ditches are the opposite sides that are positioned at this source area; Form a compound crystal silicon dielectric layer on the sidewall of this suspension gate structure and these irrigation canals and ditches; Form a polysicilion spacer on this compound crystal silicon dielectric layer sidewall with as selecting gate; And form a drain area in these irrigation canals and ditches are adjacent should the semiconductor substrate of suspension gate structure in.
Another object of the present invention is for providing a kind of manufacture method of gate separating type flash memory cell, and this method comprises the following step at least: form a gate pole oxidation layer on the semiconductor base material; Form a compound crystal silicon layer on this gate pole oxidation layer; Form a silicon nitride layer on this compound crystal silicon layer; Form irrigation canals and ditches in this silicon nitride layer and expose the part upper surface of this compound crystal silicon layer, to define a suspension gate district; Form one first oxide layer in these irrigation canals and ditches; Forming a common source plugs between two adjacent these suspension gate districts; Carry out this compound crystal silicon layer and this gate pole oxidation layer of etch process, to form a suspension gate structure to remove this silicon nitride layer and not covered by this first oxide layer; Form base material irrigation canals and ditches in the semiconductor substrate of this suspension gate structure one side, these base material irrigation canals and ditches are the opposite sides that are positioned at this common source connector; Form a compound crystal silicon dielectric layer in the sidewall of this suspension gate structure and these base material irrigation canals and ditches; Form a polysicilion spacer in this compound crystal silicon dielectric layer sidewall with as selecting gate; And form a drain area in these irrigation canals and ditches are adjacent should the semiconductor substrate of suspension gate structure in.
A further object of the present invention is for providing a kind of gate separating type flash memory cell structure, this structure includes at least: a suspension gate structure, be formed on the semiconductor base material, this suspension gate structure has from the bottom to top a gate pole oxidation layer, a compound crystal silicon layer and one first oxide layer of storehouse in regular turn, has irrigation canals and ditches in this semiconductor substrate of a side of this suspension gate structure; A compound crystal silicon dielectric layer is formed on the sidewall of this suspension gate structure and these irrigation canals and ditches; One polysicilion spacer is formed on the sidewall of this compound crystal silicon dielectric layer with as selecting gate; One drain is formed in the semiconductor substrate of these irrigation canals and ditches, and this drain area is adjacent with this selection gate; And one source pole, be formed in the semiconductor substrate with respect to these irrigation canals and ditches.
Utilize the formed gate separating type flash memory cell of method of the present invention structure, not only can reduce the lateral dimension of selecting gate effectively and keep channel length, and can produce the trajectory hot electron and dash along the selection gate channel of semiconductor substrate trench sidewall and annotate to the gate that suspends, can promote writing data efficiency and reduction writes voltage, reach the high access speed of gate separating type flash memory cell of deep-sub-micrometer processing procedure and the demand of low-power consumption.
Description of drawings
Fig. 1 to Fig. 6 is the processing procedure generalized section of gate separating type flash memory cell of the present invention;
Fig. 7 is a partial plan layout according to gate separating type flash memory cell array layout of the present invention.
The figure number explanation:
10 base materials
20 gate pole oxidation layers
30 compound crystal silicon layers/suspension gate
40 silicon nitride layers
50 first oxide layers
60 photoresist layers
70 clearance walls
80 common source connectors
90 second oxide layers
100 base material irrigation canals and ditches
110 compound crystal silicon dielectric layers
120 polysicilion spacers/selection gate
200 isolated areas
Embodiment
The present invention discloses a kind of gate separating type flash memory cell structure and preparation method thereof, wherein the selection gate of this gate separating type flash memory cell is to be formed on the sidewall of semiconductor substrate irrigation canals and ditches, utilize the base material trench sidewall as selecting the gate channel, can keep channel length and dwindle the lateral dimension of selecting gate, and this kind channel architecture can produce the trajectory hot electron, promotes writing data efficiency and reduction and writes voltage.
At first please refer to Fig. 1, it is the initial configuration that the method according to this invention is made a gate separating type flash memory cell.As shown in Figure 1, memory cell 1 includes semiconductor base material 10, a gate pole oxidation layer 20, a compound crystal silicon layer 30 and a silicon nitride layer 40.Preferably, it is＜100 that base material 10 can use crystallization direction〉single-crystal semiconductor material, and gate pole oxidation layer 20 can utilize temperature to form the oxide layer that thickness is about 50～150 dusts in the high-temperature thermal oxidation method between 800～1000 ℃ on base material 10, also can utilize traditional chemical vapour deposition technique to form this gate pole oxidation layer 20.Compound crystal silicon layer 30 can use Low Pressure Chemical Vapor Deposition (LPCVD) or other known suitable mode is formed on the gate pole oxidation layer 20, and compound crystal silicon layer 30 can select doped polycrystalline silicon or doped polycrystalline silicon is to form the conductor that thickness is about 300～3000 dusts synchronously.Because compound crystal silicon layer 30 does not link to each other with any other conductor, so be called the suspension gate, can be used for store charge.Silicon nitride layer 40 can use Low Pressure Chemical Vapor Deposition to be deposited on the compound crystal silicon layer 30, and thickness is about 500-5000 dusts.
Then, one first photoresist layer (not shown) is to be formed on the silicon nitride layer 40 to define suspension gate district, carries out dry ecthing procedure subsequently, and etching does not cover the silicon nitride layer 40 of first photoresist layer up to exposing compound crystal silicon layer 30.Then, reuse etch process and form the structure of two point upwards, remove first photoresist layer afterwards with upper surface in the compound crystal silicon layer 30 that exposes.
With reference to Fig. 2, form first oxide layer 50 on the compound crystal silicon layer 30 that exposes with chemical vapour deposition technique again, and impose and eat-back or cmp (Chemical Mechanical Polishing) processing procedure, so that the upper surface copline of the silicon nitride layer 40 and first oxide layer 50.
With reference to Fig. 3, then form second photoresist layer 60 on silicon nitride layer 40 with definition common source polar region, carry out etch process again to remove the silicon nitride layer 40 that do not covered, first oxide layer 50, compound crystal silicon layer 30 and gate pole oxidation layer 20 up to the part surface that exposes base material 10 by second photoresist layer 60.Wherein the etch process of each layer for example can use hot phosphate to remove silicon nitride layer 40, use wet etching dipping mode (Dip) to remove first oxide layer 50, use chloride electric paste etching agent to remove compound crystal silicon layer 30, and use the electricity slurry of fluorinated carbon that gate pole oxidation layer 20 is carried out dry ecthing.Subsequently, impose an ion disposing process in the base material 10 that exposes, to form the common source polar region.The dopant material that is used to form the common source polar region is to decide on the material category of base material 10.For example, when being the p type as if base material 10, the n type admixture (for example phosphorus) that can mix in base material 10 is to form the common source polar region; When if base material 10 is the n type, then can in base material 10, mix from a p type admixture (for example boron) to form the common source polar region.Remove second photoresist layer 60 afterwards again.
Then, as shown in Figure 4, deposit the surface of an oxide layer, again this oxide layer is carried out etch process to form common source district's clearance wall (Spacer) 70 in the common source polar region with chemical vapour deposition technique.This common source district clearance wall 70 is sidewalls of first oxide layer 50, compound crystal silicon layer 30 and the gate pole oxidation layer 20 of cover part, to isolate the suspension gate of two adjacent memory cells.Then, deposit another compound crystal silicon layer on common source district clearance wall 70 and common source polar region forming compound crystal silicon connector 80, and impose and eat-back or the cmp processing procedure, with silicon nitride layer 40 as stop layer.
With reference to Fig. 5, form second oxide layer 90 on common source connector 80 with thermal oxidation method, then remove silicon nitride layer 40 with dry ecthing method or wet etch method, as rigid cover curtain compound crystal silicon layer 30 and gate pole oxidation layer 20 are carried out etch process with first oxide layer 50 and second oxide layer 90 again, up to the surface that exposes base material 10.Be the making of finishing suspension gate structure and common source connector at this moment.
Next with reference to Fig. 6 the production method of selecting gate is described.As shown in Figure 6, first and second oxide layer 50 and 90 with the suspension gate structure that Fig. 1～Fig. 5 was finished is carried out etch process as rigid cover curtain to base material 10, to form a plurality of base material irrigation canals and ditches 100 in suspension gate structure both sides, for example for example can adopting, Cl2, HBr, SF6 or SiCl4 are that dry ecthing procedure is carried out to base material 10 in etching electricity slurry source.These base material irrigation canals and ditches 100 are a sloped sidewall in abutting connection with the sidewall of this floating dam electrode structure, and the degree of depth of irrigation canals and ditches and the gradient of trench sidewall can be decided according to actual demand.Then, deposit a compound crystal silicon dielectric layer 110 on the sidewall surfaces of suspension gate structure and base material irrigation canals and ditches 100 with Low Pressure Chemical Vapor Deposition, this compound crystal silicon dielectric layer 110 is as respectively suspend insulating material between gate and the control grid/selection gate of gate separating type flash memory cell, so can use the preferable silica/silicon nitride of dielectric property or the lamination layer structure of silicon oxide/silicon nitride/silicon oxide (ONO).Then, deposit another compound crystal silicon layer on a compound crystal silicon dielectric layer 110, impose etch process again to form polysicilion spacer 120 on a sidewall of compound crystal silicon dielectric layer 110, this polysicilion spacer 120 is the selection gates as the gate separating type flash memory cell.This polysicilion spacer can use traditional chemical vapour deposition technique or other proper method forms, and preferably, its thickness is about between 500～3000 dusts.This second compound crystal silicon layer can be by doping compound crystal silicon or synchronous doped polycrystalline silicon and form conductor, and this second compound crystal silicon also can form the compound crystal metal silicide by doping compound crystal silicon and tungsten silicide, and this material is a kind of gate conducting layer material of present the widest usefulness.Then, can utilize traditional ion implant or the diffusion method impurity in base material irrigation canals and ditches 100 to form drain area.Preferably, the dopant material that is used to form drain area is identical with the dopant material of source area, and is to depend on semiconductor substrate 10 formed material types.Be the making of finishing the gate separating type flash memory cell at this moment.
Fig. 7 is the partial plan layout that shows a memory cell array, wherein illustrates a plurality of according to gate separating type flash memory cell of the present invention and be used to isolate the isolated area 200 of adjoining memory cell array.The generation type of this isolated area 200 can utilize dry ecthing procedure to etch bar irrigation canals and ditches again in semiconductor substrate 10, insert materials such as silicon dioxide and polysilicon then in regular turn and form shallow-channel isolation region (Shallow Trench Isolation, STI), perhaps can use regional oxidizing process (LocalOxidation, LOCOS).In order to make the icon clear and definite, only illustrate the part-structure of this memory cell array.
Typically, the data of gate separating type flash memory cell write be by between drain, source electrode and compound crystal silicon layer (selection lock), applying suitable voltage with electron impact to by the formed suspension gate of compound crystal silicon layer.Under the highfield effect, hot electron is a bump silicon atom and scattering takes place, and then passes gate pole oxidation layer and be incident to the suspension gate.It is voltage by changing between drain, source electrode and the compound crystal silicon layer (selection lock) that the data of memory cell is erased, so that electronics is moved to by the formed selection gate of compound crystal silicon layer via the sidewall dielectric layer from the suspension gate.Owing to the electric field motion of hot electron in channel is to inject the suspension gate by scattering process, therefore need applies enough big voltage and cooperation scattering process and electronics could be injected the suspension lock and reach data and write.In the gate separating type flash memory cell structure that the method according to this invention forms, it selects gate is to be formed on the base material trench sidewall, dwindled and selected the lateral dimension of gate and keep identical channel length simultaneously, therefore applying suitable voltage in drain, source electrode and select lock to write fashionable to carry out data, hot electron is directly to be injected in the suspension gate along base material trench sidewall channel, shown in the arrow direction among Fig. 6.This kind hot electron directly is called trajectory (Ballistic) hot electron by the mode of drain/source electrode towards notes to the gate that suspends and injects, its write efficient be tradition to inject thermionic mode by scattering process good, and can reduce and put on drain, source electrode and select voltage between the lock.
In sum, the present invention discloses a kind of gate separating type flash memory cell structure and production method thereof, forms at the trench sidewall of semiconductor substrate and selects gate with the size of micro flash memory cell and keep channel length.When applying suitable voltage in drain, source electrode and selection gate, the trajectory hot electron dashes notes to the gate that suspends along the channel of trench sidewall, move the mode of just injecting the suspension gate through scattering compared to the traditional hot electronics along horizontal direction, flash memory cell of the present invention is obtained, and to write efficient preferable and can reduce and write voltage.
Claims (16)
1. the manufacture method of the selection gate of a gate separating type flash memory cell, be to be applied on the semiconductor base material, formed at least one suspension gate structure and one source pole district with gate pole oxidation layer/compound crystal silicon layer/first oxide layer on this semiconductor substrate, this method comprises the following step at least:
Form irrigation canals and ditches in this semiconductor substrate of a side of this suspension gate structure, these irrigation canals and ditches are the opposite sides that are positioned at this source area;
Form a compound crystal silicon dielectric layer on the sidewall of this suspension gate structure and these irrigation canals and ditches;
Form a polysicilion spacer on this compound crystal silicon dielectric layer sidewall with as selecting gate; And
Form a drain area in this semiconductor substrate of these irrigation canals and ditches, this drain area is adjacent this selection gate.
2. method according to claim 1 is characterized in that: this first oxide layer that the method that forms these irrigation canals and ditches comprises with this suspension gate structure is rigid cover curtain, and this semiconductor substrate is carried out etch process.
3. method according to claim 1 is characterized in that: these irrigation canals and ditches are a sloped sidewall in abutting connection with the sidewall of this suspension gate structure.
4. method according to claim 1 is characterized in that: this compound crystal silicon dielectric layer comprises the multiple layer dielectric structure of silicon oxide/silicon nitride/silicon oxide (ONO).
5. the manufacture method of a gate separating type flash memory cell, this method comprises the following step at least:
Form a gate pole oxidation layer on the semiconductor base material;
Form a compound crystal silicon layer on this gate pole oxidation layer;
Form a silicon nitride layer on this compound crystal silicon layer;
Form irrigation canals and ditches in this silicon nitride layer and expose the part upper surface of this compound crystal silicon layer, to define a suspension gate district;
Form one first oxide layer in these irrigation canals and ditches;
Forming a common source plugs between two adjacent these suspension gate districts;
Carry out this compound crystal silicon layer and this gate pole oxidation layer of etch process, to form a suspension gate structure to remove this silicon nitride layer and not covered by this first oxide layer;
Form base material irrigation canals and ditches in the semiconductor substrate of this suspension gate structure one side, these base material irrigation canals and ditches are the opposite sides that are positioned at this common source connector;
Form a compound crystal silicon dielectric layer in the sidewall of this suspension gate structure and these base material irrigation canals and ditches;
Form a polysicilion spacer in this compound crystal silicon dielectric layer sidewall with as selecting gate; And
Form a drain area in this semiconductor substrate of these irrigation canals and ditches, this drain area is adjacent this selection gate.
6. method according to claim 5 is characterized in that: form and comprise the following step in the method for these irrigation canals and ditches in this silicon nitride layer:
Form one first photoresist layer on this silicon nitride layer to define this suspension gate district;
Carry out an etch process to remove the part upper surface that does not cover this silicon nitride layer of this first photoresist layer and expose this compound crystal silicon layer;
Carry out an etch process to remove this compound crystal silicon layer of a predetermined thickness, the upper surface of the compound crystal silicon layer of this exposure is the structure that forms the both sides point upward; And
Remove this first photoresist layer.
7. method according to claim 5 is characterized in that: after forming this first oxide layer, more comprise and this first oxide layer is carried out one eat-back processing procedure, and with this silicon nitride layer as etch stop layer.
8. method according to claim 5 is characterized in that: the method that forms this first oxide layer comprises chemical vapour deposition technique.
9. method according to claim 5 is characterized in that: the method that forms this common source connector more comprises the following step:
Form one second photoresist layer and on this silicon nitride layer, have source area altogether with definition;
Carry out etch process removing this silicon nitride layer, this first oxide layer, this compound crystal silicon layer and this gate pole oxidation layer that does not cover this second photoresist layer, and expose the part upper surface of this semiconductor substrate;
Mix this base material to form in common source polar region this base material between two adjacent suspension gate structures;
Remove this second photoresist layer;
Form the sidewall surfaces of a clearance wall in this suspension gate district, wherein this clearance wall is this first oxide layer that covers this gate pole oxidation layer, this compound crystal silicon layer and part;
Forming a compound crystal silicon plugs on this common source polar region;
The upper surface of this compound crystal silicon connector of planarization; And
Form one second oxide layer on this compound crystal silicon connector.
10. method according to claim 5 is characterized in that: these irrigation canals and ditches are a sloped sidewall in abutting connection with the sidewall of this suspension gate structure.
11. method according to claim 5 is characterized in that: this compound crystal silicon dielectric layer comprises the multiple layer dielectric structure of silicon oxide/silicon nitride/silicon oxide (ONO).
12. a gate separating type flash memory cell structure includes at least:
One suspension gate structure is formed on the semiconductor base material, and this suspension gate structure has from the bottom to top a gate pole oxidation layer, a compound crystal silicon layer and one first oxide layer of storehouse in regular turn, has irrigation canals and ditches in this semiconductor substrate of a side of this suspension gate structure;
A compound crystal silicon dielectric layer is formed on the sidewall of this suspension gate structure and these irrigation canals and ditches;
One polysicilion spacer is formed on the sidewall of this compound crystal silicon dielectric layer with as selecting gate;
One drain is formed in this semiconductor substrate of these irrigation canals and ditches, and this drain area is adjacent with this selection gate; And
One source pole is formed in this semiconductor substrate with respect to these irrigation canals and ditches.
13. gate separating type flash memory cell structure according to claim 12 is characterized in that: these irrigation canals and ditches are a sloped sidewall in abutting connection with the sidewall of this suspension gate structure.
14. gate separating type flash memory cell structure according to claim 12 is characterized in that: this compound crystal silicon dielectric layer comprises the multiple layer dielectric structure of silicon oxide/silicon nitride/silicon oxide (ONO).
15. gate separating type flash memory cell structure according to claim 12 is characterized in that: this compound crystal silicon dielectric layer is the sidewall that covers this suspension gate structure, the sidewall of these irrigation canals and ditches and the lower surface of these irrigation canals and ditches partly.
16. gate separating type flash memory cell structure according to claim 12 is characterized in that: more include:
One clearance wall is formed on the sidewall of this suspension gate structure of this irrigation canals and ditches opposite side, and this clearance wall is this gate pole oxidation layer, this compound crystal silicon layer and this first oxide layer that covers this suspension gate structure; And
The one source pole connector is formed between two adjacent these suspension gate structures, is formed with one second oxide layer on this source electrode connector.
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| Application Number | Priority Date | Filing Date | Title |
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| CN02119730.XA CN1200448C (en) | 2002-05-14 | 2002-05-14 | Manufacturing method of selective gate pole of gate separating type quickflash memory cell |
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| CN02119730.XA CN1200448C (en) | 2002-05-14 | 2002-05-14 | Manufacturing method of selective gate pole of gate separating type quickflash memory cell |
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| CN1459827A true CN1459827A (en) | 2003-12-03 |
| CN1200448C CN1200448C (en) | 2005-05-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111081710A (en) * | 2019-12-24 | 2020-04-28 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of flash memory unit sharing source line and flash memory unit sharing source line |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111081710A (en) * | 2019-12-24 | 2020-04-28 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of flash memory unit sharing source line and flash memory unit sharing source line |
| CN111081710B (en) * | 2019-12-24 | 2023-08-15 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory cell sharing source line and flash memory cell sharing source line |
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