CN1450656A

CN1450656A - Grid medium stacking structure

Info

Publication number: CN1450656A
Application number: CN 03116930
Authority: CN
Inventors: 缪炳有; 徐小诚
Original assignee: Shanghai Huahong Group Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Shanghai Huahong Group Co Ltd
Priority date: 2003-05-15
Filing date: 2003-05-15
Publication date: 2003-10-22

Abstract

This invention relates to a pile structure of a high dielectric grating medium, Devices become smaller and smaller. When thickness of gate oxygen is<1.5 nm, the drain current is too mush, so a high dielectric material is used to replace SiO2. This invention puts forward a double-layer grid pile structure: Al2O3/(Ta2O5+Al2O3) or Al2O3/BaZrO3. The band gap of Al2O3 is 8.8eV, dielectric constant-10, conduction band offset is 2.8eV, similar to SiO2 on band gap and energy band combination only short in low dielectric constant, so, we use Ta2O5+Al2O3 (k>10) mixed layer or BaZrO3 to increase the entire dielectric constant. Besides, Ta or TaN are used as the electrode to avoid depletion of polysilicon and B penetration.

Description

A kind of new gate medium laminating structure

Technical field

The invention belongs to the semiconductor integrated circuit manufacturing process technology field, be specifically related to a kind of laminating structure (high-k stack) of high dielectric gate.

Background technology

In CMOS IC manufacturing process, the continuous minimizing that continues to dwindle the requirement grid medium thickness of unit component.This requirement is from the consideration of two aspects: 1. control short-channel effect; 2. realize high current drives---when service voltage reduces, still keep inducing in the raceway groove quantity of electric charge enough big.Under these two kinds of situations, with regard to first approximation, the electrical thickness of gate medium is important.Electrical thickness during transoid determines by three series capacitances, that is: the depletion capacitance of gate electrode, gate medium electric capacity and silicon substrate inversion capacitance, as shown in Figure 1.On the other hand, along with reducing of gate medium physical thickness, pressing index by the direct Tunneling electric current of grid increases; This tunnelling current directly influences the standby voltage of chip, and to the physical thickness of the non-decline of gate medium given lower limit; Even, work as SiO to high performance system (the tunnelling gate current is inessential) ₂Thickness＜the 0.8nm of grid, its tunnelling gate current can not bear.For the gate capacitance that reduces the grid tunnelling current and cause owing to depletion of polysilicon decays, its solution is: introduce new material--the gate medium and the metal gate electrode of-high-k (high k).

Dielectric constant is far above SiO ₂(k _Ox) gate medium can realize and SiO ₂Electrical thickness (t of equal value and thin _Eq), the physical thickness (t of grid medium with high dielectric especially _Phys) greater than SiO ₂(t _Ox):

t _eq＝(k _ox/k)*t _phys

Substitute SiO with high dielectric constant material ₂Not a simple thing, the necessary and SiO of its material internal and interface performance ₂Comparable, and device performance improves significantly.The fundamental characteristics of material, as the thermodynamic stability relevant with silicon substrate, the stability in the microelectronics course of processing under the various heat-treat conditions, low diffusion coefficient, thermal expansion (with silicon) coupling, these all are some important evaluation parameters.

What people at first expected is silicon nitride.To SiO ₂Closely-related with it SiON, interface trap and body internal trap normally 10 ¹⁰Cm ^-2EV ^-1With 10 ¹⁰Cm ^-2The order of magnitude, the reliability of electric charge trapping (traps) and gate medium are unusual important consideration; The thermal stability relevant with silicon also is an important consideration, and leak in the source and the doping of polysilicon activates because high annealing is generally used for.Relevant bibliographical information nitride gate dielectric structure behind the initial oxidation silicon, adopt stove growth (LPCVD), and successively at ammonia (NH ₃) and laughing gas (N ₂O) annealing (800-1000 ℃) in, its result is encouraging.Feasibility in the production---promptly: low leakage current, the inhibition of boron penetration, analogous carrier mobility is conspicuous.The parity price oxide thickness is the CVD silicon nitride of 1.4nm, little two orders of magnitude of its leakage current.The nitride that penetrates on the complete oxidized silicon of boron suppresses.Mobility after the optimization can reach the value of thermal oxidation silicon, thereby makes saturation current also comparable with thermal oxidation silicon.Yet the dielectric constant of nitride not high enough (K ~ 8) is to SiO ₂The device of equivalent electrical thickness＜1nm is not competent, so also need seek the more gate dielectric material of high-k.

People have been following experiment: SiO to three kinds of thin dielectric films ₂, Al ₂O ₃And have boundary layer SiO ₂ZrO ₂These media only have several atomic layers thick, available sputter (sputtering), sol-gel (Sol-gel method), physical vapor Cheng Jifa (PVD), metal organic chemistry vapour phase deposition process (MOCVD) and atomic layer deposition method (ALCVD).The deposited film uniformity is not a major issue, yet integrated also need of the deposit of high dielectric material and other device making technics done further research at several fields.If use traditional autoregistration polysilicon gate, gate dielectric film must be able to be stood rapid thermal annealing (RTAs) 〉=950 ℃, so that activate the polysilicon gate that mixes; In polysilicon gate CMOS technology, common heat treatment causes potential problem, as the formation and the interface SiO of silicide between high medium grid and silicon substrate ₂Appearance.In addition, the diffusion (as boron, oxygen) of passing gate medium is a serious problem; If use metal gates (using low temperature process), many thermal stability problems can be eased.

Someone foretells that it is heat-staple that many binary contact with silicon with ternary oxide, but recently the research of high-k gate insulation layer is mainly concentrated on binary metal oxide such as Ta ₂O ₅, TiO ₂, ZrO ₂, HfO ₂, Y ₂O ₃, La ₂O ₃, Al ₂O ₃, and Gd ₂O ₃With their silicide.The dielectric constant of these materials in 10～40 scopes, compares SiO usually ₂High by 3～10.Experiment showed, SiO with same electrical thickness ₂Compare, the leakage current of high dielectric gate can reduce 10 ³Doubly to 10 ⁶Doubly; But because drain region two dimension fringe field can pass thick high dielectric gate, so limited the benefit that high dielectric gate brings.The drain edge field has reduced source-raceway groove potential barrier, thereby has reduced threshold value or cut-in voltage; Its principle induces potential barrier (DIBL) reduction similar to the leakage of knowing, that is: the electric leakage field is by the silicon substrate coupling source of having modulated-raceway groove potential barrier.Therefore, the use of high dielectric material must be considered simultaneously with the minimizing of electrical thickness; Big silicon-gate medium barrier height is desirable, because the barrier height exponentially formula dependence (exponential is the square root of barrier height) therewith of the direct Tunneling electric current by grid.In addition, also barrier height is relevant therewith to launch the hot carrier that enters gate insulation layer.Therefore, high dielectric gate not only will have broad-band gap, and to have a higher barrier height can be with combination.Al ₂O ₃May be and SiO ₂Make up similar only a kind of material in band gap with being with.

Yet integrated also need of the deposit of high dielectric material and other device making technics done further research at several fields.If use traditional autoregistration polysilicon gate, gate dielectric film must be able to be stood rapid thermal annealing (RTAs) 〉=950 ℃, so that activate the polysilicon gate that mixes; In polysilicon gate CMOS technology, common heat treatment causes potential problem, as the formation and the interface SiO of silicide between high medium grid and silicon substrate ₂Appearance.In addition, the diffusion (as boron, oxygen) of passing gate medium is a serious problem; If use metal gates (using low temperature process), many thermal stability problems can be eased.

In sum, single high dielectric gate material can be divided into two big classes: the one, interface problem---some dielectric material K value is very high, but with SiO is arranged after silicon contacts ₂Boundary layer generates (this is that people do not wish to see), makes SiO of equal value ₂Thickness (t _Eq) reduce a lot, in other words, the corresponding minimizing of the growth thickness of high dielectric material; In addition, interfacial state/defective is a lot, causes the mobility of charge carrier rate to reduce greatly; It two is K value problems on the low side---some dielectric material such as Al ₂O ₃Interfacial characteristics and SiO ₂Similar, but the K value is on the low side, causes its physical thickness (t _Phys) significantly reduce, thereby tunnelling current is increased.Therefore, single high dielectric gate material is difficult to satisfy its requirement, the multi-layer gate medium be combined into a kind of feasible scheme.Consider the pluses and minuses of technologic feasibility and high dielectric material, people usually when design high dielectric gate pile structure at two kinds of type of device: low energy-consumption electronic device---require the tunnelling current minimum of passing gate medium, stand-by power consumption is low; High performance device---firing current is big or opening speed is fast, and tunnelling current is unimportant.

Summary of the invention

The objective of the invention is at low energy-consumption electronic device, propose a kind of double-deck gate medium laminating structure, to solve the unvanquishable shortcoming of single high dielectric material: interface problem or K value problem on the low side---cause carrier mobility to reduce and SiO of equal value ₂Thickness (t _Eq) reduce, tunnelling current can not be inhibited fully.

The double-deck gate medium laminating structure that the present invention proposes is a kind of employing Al ₂O ₃With mixing Ta ₂O ₅+ Al ₂O ₃Or BaZrO ₃High bi-layer of dielectric structure.This gate dielectric structure is applicable to the MOS device of equivalent gate oxide thickness≤1nm, for grid medium with high dielectric provides a kind of possibility.

In order to solve with the interface problem of silicon and to be with combination, we have selected Al for use ₂O ₃Determine layer as the interface.Al ₂O ₃Band gap be 8.8eV, dielectric constant is～10, conduction band offset is 2.8eV, the valence band offset amount is 4.9eV, with SiO ₂Band gap with can be with the combination on similar, be fit to do boundary layer, unique shortcoming is that dielectric constant is on the low side.Therefore, we use the higher Ta of dielectric constant ₂O ₅+ Al ₂O ₃(k＞10) mixed layer or BaZrO ₃Layer improves whole dielectric constant values.In addition, adopt metal gate (single or two kinds of metals all can,, WTi, WN, TiN, TiNi, Ta, TaN alloy etc.) to do electrode as W, thus the technology integration problem of having avoided boron penetration problem that polysilicon gate brings (from polycrystalline to grid oxygen) and activated to anneal and bring.Certainly, select metal electrode must consider the matching problem of work function.Here we select Ta or TaN as metal gate electrode.

The grid pile structure of the novelty of the present invention's design, characteristics are to adopt Al ₂O ₃, mix Ta ₂O ₅+ Al ₂O ₃Or BaZrO ₃High dielectric layer double-decker, realize that the key step of this structure is as follows: elder generation is with the natural SiO of silicon chip surface ₂Remove, adopt atomic layer growth method (ALCVD) or metal organic chemical vapor deposition method (MOCVD) or sol-gel (Sel-gel) the method Al that on the silicon chip of surface hydriding, grows successively then ₂O ₃, mix Ta ₂O ₅+ Al ₂O ₃Or BaZrO ₃High dielectric layer; Use low temperature (less than 600 ℃) technology depositing metal grid Ta or TaN at last.

Above-mentioned silicon chip surface natural oxidizing layer SiO ₂Remove with the HF acid vapor, surperficial dangling bonds are saturated by hydrogen, become hydrophobic surface; Above-mentioned Al ₂O ₃And Al ₂O ₃Tectal growth thickness is 0.3nm～0.8nm; Above-mentioned Al ₂O ₃And Al ₂O ₃Tectal growth adopts ALCVD or MOCVD technology to finish; Above-mentioned Ta ₂O ₅+ Al ₂O ₃The growth thickness of mixed layer is 1～3nm, such as, with Ba (CH ₃) ₂With oxygen or ozone deposit; Above-mentioned BaZrO ₃The growth thickness of high dielectric layer is 4～6nm, such as, use the Sel-gel method with BaO and ZrO ₂Powder is dissolved in behind the solvent sintering in oxygen or ozone atmosphere; Above-mentioned Ta ₂O ₅+ Al ₂O ₃The growth of mixed layer adopts ALCVD or MOCVD or Sel-gel technology to finish; Above-mentioned BaZrO ₃The growth of high dielectric layer adopts MOCVD or Sel-gel technology to finish; Adopt low temperature process (＜600 ℃) PVD or CVD method depositing metal grid _TaOr _TaN

Description of drawings

Fig. 1 represents how the electrical thickness of gate medium determines.Electrical thickness during transoid is by three series capacitance C _InvDetermine, that is: the depletion capacitance of polygate electrodes, gate medium electric capacity and silicon substrate inversion capacitance.

Fig. 2 represents the laminating structure of high dielectric gate, that is: Al ₂O ₃/ (Ta ₂O ₅+ Al ₂O ₃) structure.

Drawing reference numeral: 1---silicon substrate; 2---Al ₂O ₃The 3---metal electrode; 4---Ta ₂O ₅+ Al ₂O ₃5---SiO ₂The 6---polysilicon

The present invention can effectively reduce the grid tunnelling current and because the gate capacitance that depletion of polysilicon causes decays, can realize very high device open frequency; Simple relatively, convenient on the IC manufacturing process, be easy to integrated.

Embodiment

Further describe the present invention below by specific embodiment:

1. surface clean: the natural SiO of silicon chip surface ₂Use the HF vapour removal;

2.Al ₂O ₃Layer growth is determined at the interface: adopt atomic layer growth method (ALCVD) or metal organic chemical vapor deposition method (MOCVD) or sol-gel process (Sel-gel) at the Al about the about 0.5nm of growth on the silicon chip of surface hydriding ₂O ₃Determine layer as the interface;

3.Ta ₂O ₅+ Al ₂O ₃Or BaZrO ₃Deposit: adopt MOCVD or sol-gel (Sol-gel) method deposit 2nmTa ₂O ₅+ Al ₂O ₃Or BaZrO ₃This thickness can be adjusted according to gate oxide thickness of equal value;

4. metal gate deposit: adopt low temperature process (＜600 ℃) CVD method depositing metal grid Ta or TaN.

Promptly obtain required double-deck gate medium laminating structure Al ₂O ₃/ (Ta ₂O ₅+ Al ₂O ₃) or Al ₂O ₃/ BaZrO ₃

Claims

1, a kind of double-deck gate medium laminating structure is characterized in that adopting Al ₂O ₃, mix Ta ₂O ₅+ Al ₂O ₃Or BaZrO ₃High dielectric layer double-decker.

2, double-deck gate medium laminating structure according to claim 1 is characterized in that adopting metal gate Ta or TaN to make electrode.

3, double-deck gate medium laminating structure according to claim 1 is characterized in that above-mentioned Al ₂O ₃And Al ₂O ₃Tectal growth thickness is 0.3nm-0.8nm.

4, double-deck gate medium laminating structure according to claim 1 is characterized in that above-mentioned Ta ₂O ₅+ Al ₂O ₃The thickness of mixed layer is 1～3nm.

5, double-deck gate medium laminating structure according to claim 1 is characterized in that above-mentioned BaZrO ₃The growth thickness of high dielectric layer is 4-6nm.

6, a kind of preparation method of double-deck gate medium laminating structure as claimed in claim 1 is characterized in that concrete steps are as follows: the natural SiO that removes silicon chip surface earlier ₂, adopt atomic layer growth method or metal organic chemical vapor deposition method or the sol-gel process Al that on the silicon chip of surface hydriding, grows successively then ₂O ₃, Ta ₂O ₅+ Al ₂O ₃Or BaZrO ₃High dielectric layer; Use low temperature process depositing metal grid Ta or TaN at last less than 600 ℃.

7, preparation method according to claim 6 is characterized in that above-mentioned silicon chip surface natural oxidizing layer SiO ₂Remove with the HF acid vapor, surperficial dangling bonds are saturated by hydrogen, become hydrophobic surface.