CN1189923C

CN1189923C - Structure of grid medium with high dielectric and its preparation method

Info

Publication number: CN1189923C
Application number: CN 02137198
Authority: CN
Inventors: 缪炳有; 徐小诚
Original assignee: Shanghai Huahong Group Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Shanghai Huahong Group Co Ltd
Priority date: 2002-09-27
Filing date: 2002-09-27
Publication date: 2005-02-16
Anticipated expiration: 2022-09-27
Also published as: CN1416156A

Abstract

The present invention relates to a high dielectric grid medium stacking structure which belongs to the technical field of a manufacturing process of a semiconductor integrated circuit. As the device dimension is reduced continuously, when grid oxygen thickness is less than 1.5 nm, leakage current passing through grid oxygen is too large, a high dielectric material is used for replacing silicon dioxide, however, a single high dielectric grid material can satisfy the requirements with difficulty, and therefore, multilayer grid mediums are combined into a feasible scheme. A grid media double-layer structure is designed in the present invention, namely a Al2O3/BaO+Al2O3 structure. The band gap of the Al2O3 is 8.8eV, the dielectric constant is-10, and the conduction band offset is 2.8eV. The grid media double-layer structure is similar to SiO2 in the combination of the band gap and an energy band, and is suitable for being used as a boundary layer, a BaO(k>20) with high dielectric constant is used for enhancing an integral dielectric constant value, and in addition, a metal gate TiN is used as an electrode to avoid polysilicon depletion and boron penetration.

Description

A kind of structure of grid medium with high dielectric and preparation method thereof

Technical field

The invention belongs to the semiconductor integrated circuit manufacturing process technology field, be specifically related to a kind of laminating structure (high-k stack) of high dielectric gate.

Background technology

In CMOS IC manufacturing process, the continuing of unit component dwindles the requirement grid medium thickness and constantly reduces.This requirement is from the consideration of two aspects: 1. control short-channel effect; 2. realize high current drives---when service voltage reduces, still keep inducing in the raceway groove quantity of electric charge enough big.Under these two kinds of situations, with regard to first approximation, the electrical thickness of gate medium is important.Electrical thickness during transoid determines by three series capacitances, that is: the depletion capacitance of gate electrode, gate medium electric capacity and silicon substrate inversion capacitance, as shown in Figure 1.On the other hand, along with reducing of gate medium physical thickness, pressing index by the direct Tunneling electric current of grid increases; This tunnelling current directly influences the standby voltage of chip, and to the physical thickness of the non-decline of gate medium given lower limit; Even, work as SiO to high performance system (the tunnelling gate current is inessential) ₂Thickness＜the 0.8nm of grid, its tunnelling gate current can not bear.For the gate capacitance that reduces the grid tunnelling current and cause owing to depletion of polysilicon decays, its solution is: introduce new material---the gate medium and the metal gate electrode of high-k (high k).

Dielectric constant is far above SiO ₂(k _Ox) gate medium can realize and SiO ₂Electrical thickness (t of equal value and thin _Eq), the physical thickness (t of grid medium with high dielectric especially _Phys) greater than SiO ₂(t _Ox):

t _eq＝(t _ox/k)*t _phys

Substitute SiO with high dielectric constant material ₂Not a simple thing, the necessary and SiO of its material internal and interface performance ₂Comparable, and device performance improves significantly.The fundamental characteristics of material, as the thermodynamic stability relevant with silicon substrate, the stability in the microelectronics course of processing under the various heat-treat conditions, low diffusion coefficient, thermal expansion (with silicon) coupling, these all are some important evaluation parameters.

What people at first expected is silicon nitride.To SiO ₂Closely-related with it SiON, interface trap and body internal trap normally 10 ¹⁰Cm ^-2EV ^-1With 10 ¹⁰Cm ^-2The order of magnitude, the reliability of electric charge trapping (traps) and gate medium are unusual important consideration; The thermal stability relevant with silicon also is an important consideration, and leak in the source and the doping of polysilicon activates because high annealing is generally used for.Relevant bibliographical information nitride gate dielectric structure behind the initial oxidation silicon, adopt stove growth (LPCVD), and successively at ammonia (NH ₃) and laughing gas (N ₂O) annealing (800-1000 ℃) in, its result is encouraging.Feasibility in the production---promptly: low leakage current, the inhibition of boron penetration, analogous carrier mobility is conspicuous.The parity price oxide thickness is the CVD silicon nitride of 1.4nm, little two orders of magnitude of its leakage current.The nitride that penetrates on the complete oxidized silicon of boron suppresses.Mobility after the optimization can reach the value of thermal oxidation silicon, thereby makes saturation current also comparable with thermal oxidation silicon.Yet the dielectric constant of nitride not high enough (K ~ 8) is to SiO ₂The device of equivalent electrical thickness＜1nm is not competent, so also need seek the more gate dielectric material of high-k.

Someone foretells that it is heat-staple that many binary contact with silicon with ternary oxide, but recently the research of high-k gate insulation layer is mainly concentrated on binary metal oxide such as Ta ₂O ₅, TiO ₂, ZrO ₂, HfO ₂, Y ₂O ₃, La ₂O ₃, Al ₂O ₃, and Gd ₂O ₃With their silicide.The dielectric constant of these materials in 10～40 scopes, compares SiO usually ₂High by 3～10.Experiment showed, SiO with same electrical thickness ₂Compare, the leakage current of high dielectric gate can reduce 10 ³Doubly to 10 ⁶Doubly; But because drain region two dimension fringe field can pass thick high dielectric gate, so limited the benefit that high dielectric gate brings.The drain edge field has reduced source-raceway groove potential barrier, thereby has reduced threshold value or cut-in voltage; Its principle induces potential barrier (DIBL) reduction similar to the leakage of knowing, that is: the electric leakage field is by the silicon substrate coupling source of having modulated-raceway groove potential barrier.Therefore, the use of high dielectric material must be considered simultaneously with the minimizing of electrical thickness; Big silicon-gate medium barrier height is desirable, because the barrier height exponentially formula dependence (exponential is the square root of barrier height) therewith of the direct Tunneling electric current by grid.In addition, also barrier height is relevant therewith to launch the hot carrier that enters gate insulation layer.Therefore, high dielectric gate not only will have broad-band gap, and to have a higher barrier height can be with combination.Al ₂O ₃May be and SiO ₂Make up similar only a kind of material in band gap with being with.

Yet integrated also need of the deposit of high dielectric material and other device making technics done further research at several fields.If use traditional autoregistration polysilicon gate, gate dielectric film must be able to be stood rapid thermal annealing (RTAs) 〉=950 ℃, so that activate the polysilicon gate that mixes; In polysilicon gate CMOS technology, common heat treatment causes potential problem, as the formation and the interface SiO of silicide between high medium grid and silicon substrate ₂Appearance.In addition, the diffusion (as boron, oxygen) of passing gate medium is a serious problem; If use metal gates (using low temperature process), many thermal stability problems can be eased.

In sum, single high dielectric gate material can be divided into two big classes: the one, interface problem---some dielectric material K value is very high, but with SiO is arranged after silicon contacts ₂Boundary layer generates (this is that people do not wish to see), makes SiO of equal value ₂Thickness (t _Eq) reduce a lot, in other words, the corresponding minimizing of the growth thickness of high dielectric material; In addition, interfacial state/defective is a lot, causes the mobility of charge carrier rate to reduce greatly; It two is K value problems on the low side---some dielectric material such as Al ₂O ₃Interfacial characteristics and SiO ₂Similar, but the K value is on the low side, causes its physical thickness (t _Phys) significantly reduce, thereby tunnelling current is increased.Therefore, single high dielectric gate material is difficult to satisfy its requirement, the multi-layer gate medium be combined into a kind of feasible scheme.Consider the pluses and minuses of technologic feasibility and high dielectric material, people usually when design high dielectric gate pile structure at two kinds of type of device: low energy-consumption electronic device---require the tunnelling current minimum of passing gate medium, stand-by power consumption is low; High performance device---firing current is big or opening speed is fast, and tunnelling current is unimportant.

Summary of the invention

The objective of the invention is,, propose a kind of structure of grid medium with high dielectric and preparation method thereof at low energy-consumption electronic device, to solve the unvanquishable shortcoming of single high dielectric material: interface problem or K value problem on the low side---cause carrier mobility to reduce and SiO of equal value ₂Thickness (t _Eq) reduce, tunnelling current can not be inhibited fully.

The structure of grid medium with high dielectric of the present invention's design is with Al ₂O ₃Determine layer as the interface, adopt BaO+Al ₂O ₃Mixed layer is formed a kind of new grid pile structure---Al to improve dielectric constant ₂O ₃/ BaO+Al ₂O ₃Double-decker.It is applicable to the MOS device of equivalent gate oxide thickness≤1.5nm, for grid medium with high dielectric provides a kind of preferred version.

The present invention has selected Al for use in order to solve with the interface problem of silicon and to be with combination ₂O ₃Determine layer as the interface.Al ₂O ₃Band gap be 8.8eV, dielectric constant～10, conduction band offset is 2.8eV, the valence band offset amount is 4.9eV, with SiO ₂Band gap with can be with combination on similar, and SiO seldom appears ₂Boundary layer, unique shortcoming are that dielectric constant is on the low side.Therefore, the present invention adopts the higher BaO of dielectric constant (k＞20) to improve whole dielectric constant values.It is very little in order to guarantee tunnelling current using double-decker.

In addition, the present invention adopt metal gate (single or two kinds of metals all can, as W, WTi, WN, TiN, TiNi, Ta, TaN alloy etc.) do electrode, thus the technology integration problem of having avoided boron penetration problem that polysilicon gate brings (from polycrystalline to grid oxygen) and activated at annealing to bring.The preferred TiN of the present invention makes its work function that better matching be arranged as metal gate electrode.

Above-mentioned structure of grid medium with high dielectric, wherein Al ₂O ₃Thickness is 0.3-0.8nm, BaO+Al ₂O ₃The thickness of mixed layer can be 3-5nm.

The present invention also proposes the preparation method of above-mentioned structure of grid medium with high dielectric, and concrete steps are as follows: elder generation is with the natural SiO of silicon chip surface ₂Remove; Adopt atomic layer growth method (ALCVD) or metal organic chemical vapor deposition method (MOCVD) or sol-gel process (Sel-gel) Al that on the silicon chip of surface hydriding, grows successively then ₂O ₃, the high dielectric layer of BaO, Al ₂O ₃Cover layer; Use low temperature process depositing metal grid TiN at last.Above-mentioned silicon chip surface natural oxidizing layer SiO ₂Available HF acid vapor is removed, and makes surperficial dangling bonds saturated by hydrogen, becomes hydrophobic surface; The Al of available ALCVD or MOCVD technology growth 0.3nm～0.8nm ₂O ₃, such as, with Al (CH ₃) ₃With the steam deposit; The BaO+Al of available ALCVD or MOCVD or Sel-gel growth 3～5nm thickness ₂O ₃(deciding) according to gate oxide thickness of equal value, such as, with Ba (CH ₃) ₂, Al (CH ₃) ₃With oxygen or ozone deposit; Can adopt low temperature process (＜600 ℃) PVD or CVD method depositing metal grid TiN.

The present invention can effectively reduce the grid tunnelling current and because the gate capacitance decay that depletion of polysilicon causes can realize higher device open frequency, guarantee low-power consumption simultaneously again; Simple relatively, convenient on the IC manufacturing process, be easy to integrated.

Description of drawings

Fig. 1 is the electrical thickness decision diagram of gate medium.Electrical thickness during transoid is by three series capacitance C _InvDetermine, that is: the depletion capacitance of polygate electrodes, gate medium electric capacity and silicon substrate inversion capacitance.

Fig. 2 is the double-decker diagram of high dielectric gate, that is: Al ₂O ₃/ BaO+Al ₂O ₃Structure.High dielectric BaO and Al ₂O ₃Mix, to improve overall dielectric constant.

Drawing reference numeral: 1---silicon substrate; 2---Al ₂O ₃The 3---metal electrode; 4---BaO+Al ₂O ₃5---SiO ₂The 6---polysilicon

Embodiment

Further specifically describe the present invention below by embodiment:

1, silicon chip surface cleans: elder generation is with the natural SiO of silicon chip surface ₂Use the HF vapour removal;

2, Al ₂O ₃Layer growth is determined at the interface: adopt atomic layer growth method (ALCVD) or metal organic chemical vapor deposition method (MOCVD) at the Al about the about 0.5nm of growth on the silicon chip of surface hydriding ₂O ₃Determine layer as the interface; Such as, with Al (CH ₃) ₃With the steam deposit;

3, BaO+Al ₂O ₃Deposit: the BaO+Al that adopts ALCVD or MOCVD or sol-gel (Sol-gel) method deposit 4nm left and right thickness ₂O ₃This thickness can be adjusted according to gate oxide thickness of equal value; Such as, with Ba (CH ₃) ₂, Al (CH ₃) ₃With oxygen or ozone deposit;

4, metal gate deposit: adopt low temperature process (＜600 ℃) CVD method deposit TiN metal gate.

Claims

1. a gate dielectric structure is characterized in that with Al ₂O ₃Determine layer as the interface, adopt BaO+Al ₂O ₃Mixed layer is with the raising dielectric constant, and BaO+Al ₂O ₃Mixed layer is formed on Al ₂O ₃The interface is determined to form Al on the layer ₂O ₃/ BaO+Al ₂O ₃The gate medium double-decker.

2. according to right 1 described gate dielectric structure, it is characterized in that adopting metal gate to do electrode.

3. according to right 1 described gate dielectric structure, it is characterized in that Al ₂O ₃Thickness is 0.3-0.8nm, BaO+Al ₂O ₃Thickness is 3-5nm.

4. the preparation method of a dielectric structure as claimed in claim 1 is characterized in that concrete steps are as follows: first natural SiO with silicon chip surface ₂Remove; Adopt atomic layer growth method or metal organic chemical vapor deposition method or the sol-gel process Al that on the silicon chip of surface hydriding, grows successively then ₂O ₃, BaO+Al ₂O ₃Mixed layer is used low temperature process depositing metal grid TiN at last.

5. preparation method according to claim 4 is characterized in that above-mentioned silicon chip surface natural oxidizing layer SiO ₂Remove with the HF acid vapor, surperficial dangling bonds are saturated by hydrogen, become hydrophobic surface.