CN1445858A - Nonvolatile memory and its manufacturing method - Google Patents
Nonvolatile memory and its manufacturing method Download PDFInfo
- Publication number
- CN1445858A CN1445858A CN02107552.2A CN02107552A CN1445858A CN 1445858 A CN1445858 A CN 1445858A CN 02107552 A CN02107552 A CN 02107552A CN 1445858 A CN1445858 A CN 1445858A
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- substrate
- ditches
- bit line
- irrigation canals
- embedded type
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000002262 irrigation Effects 0.000 claims description 35
- 238000003973 irrigation Methods 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
A structure of non-volatility internal memory can be built by making a ditch in a substrate with a buried bit line overspanning this ditch and a character line covering the ditch as well as spanning the buried bit line, and setting an arresting layer for layer charge between the substrate and the character line.
Description
Technical field
The invention relates to a kind of structure and manufacture method thereof of semiconductor device, and be particularly to structure and the manufacture method thereof of a kind of non-voltile memory (non-volatile memory).
Background technology
A kind of substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) internal memory is arranged in the non-voltile memory, and its known configurations as shown in Figure 1.
Fig. 1 is the section of structure of known a kind of substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) internal memory.
Please refer to Fig. 1, the structure of substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) internal memory normally has one deck word line 112 in substrate 100, and between substrate 100 and word line 112, have one deck silicon oxide/silicon nitride/silicon oxide (ONO) layer 104 as electric charge capture layer (charge trapping layer), and in silicon oxide/silicon nitride/silicon oxide (ONO) layer 104 substrate on two sides 100, have embedded type bit line (buried bit line) 108, and between embedded type bit line 108 and word line 112, embedded type bit line oxide layer 110 is arranged.
In traditional substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) internal memory, because its channel region (channel region) all is smooth, so channel current (channel current) will dwindle and reduces along with the size of memory cell (memory cell), make in the memory cell that the difference between the channel current of the channel current of state " 1 " and state " 0 " also is lowered.
Summary of the invention
The purpose of this invention is to provide a kind of non-voltile memory and manufacture method thereof, can prevent that channel current from dwindling along with the size of memory cell and reduce.
A further object of the present invention provides a kind of non-voltile memory and manufacture method thereof, can increase channel current under the constant situation of memory cell size.
Another object of the present invention provides a kind of non-voltile memory and manufacture method thereof, can avoid because the size of memory cell is dwindled, and cause the problem of the difference reduction of memory cell between the channel current of the channel current of state " 1 " and state " 0 ".
Another purpose of the present invention provides a kind of non-voltile memory and manufacture method thereof, can make in the memory cell difference between the channel current of the channel current of state " 1 " and state " 0 " become big.
According to above-mentioned and other purpose, the present invention proposes a kind of non-voltile memory, and its structure has irrigation canals and ditches in a substrate, and has an embedded type bit line to cross this irrigation canals and ditches, and have a word line to cover these irrigation canals and ditches at least and cross embedded type bit line, one deck electric charge capture layer is arranged between substrate and word line again.In addition, between embedded type bit line and word line, also comprise one deck embedded type bit line oxide layer.
The present invention proposes a kind of manufacture method of non-voltile memory in addition, is included in the substrate and forms irrigation canals and ditches, forms an electric charge capture layer again in substrate, and covers the irrigation canals and ditches surface.Subsequently, utilize the lithography manufacture craft to expose the part substrate, cross the zone of irrigation canals and ditches with formation.Then, in the substrate in zone, form an embedded type bit line, and form one deck embedded type bit line oxide layer in the surface that embedded type bit line exposed.At last, on electric charge capture layer, form a word line,, and cross embedded type bit line with the covering irrigation canals and ditches.
And advantage of the present invention is formed at the word line of non-voltile memory on the irrigation canals and ditches of substrate, and the embedded type bit line of crossing irrigation canals and ditches.Because the channel of internal memory is bending in the direction of its width, thus channel current can be increased, and then cause in the memory cell difference between the channel current of the channel current of state " 1 " and state " 0 " to become big.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, elaborate.
Description of drawings
Fig. 1 is the section of structure of known a kind of substrate/silicon oxide/silicon nitride/silicon oxide/silicon internal memory;
Fig. 2 A to Fig. 2 F is the manufacturing process schematic perspective view of a kind of substrate/silicon oxide/silicon nitride/silicon oxide/silicon non-voltile memory according to preferred embodiment of the present invention;
Fig. 3 is the structural representation according to the III-III section of Fig. 2 F;
Fig. 4 is the structural representation according to the IV-IV section of Fig. 2 F.Label declaration:
100,200: substrate 104,204: electric charge capture layer
108,208: embedded type bit line 110,210: the embedded type bit line oxide layer
112,212: word line 202: irrigation canals and ditches
206: zone 214: wordline width
Embodiment
Dwindle along with the size of memory cell (memory cell) and reduce for fear of channel current (channel current), and cause the too small problem of the difference of memory cell between the channel current of the channel current of state " 1 " and state " 0 " to produce, preferred embodiment of the present invention provides a kind of substrate/silicon oxide/silicon nitride/silicon oxide/silicon (substrate/oxide/nitride/oxide/silicon is called for short SONOS) non-voltile memory (non-volatile memory) and manufacture method thereof.
Fig. 2 A to Fig. 2 F is the manufacturing process schematic perspective view according to a kind of substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) non-voltile memory of preferred embodiment of the present invention.
Please refer to Fig. 2 A, in a substrate 200, form irrigation canals and ditches 202, the shape of irrigation canals and ditches is a U-shaped for example, and the formation method of irrigation canals and ditches 202 can be prior to forming one deck photoresist layer in the substrate 200, utilize little shadow manufacture craft to become the part substrate 200 of irrigation canals and ditches 202 to come out preboarding then, utilize anisotropic etching manufacture craft (anisotropic etch process) to form irrigation canals and ditches 202 again, remove photoresist layer at last and get final product.
Then, please refer to Fig. 2 B, in substrate, form one deck electric charge capture layer (chargetrapping layer) 204, and cover irrigation canals and ditches 202 surfaces.Wherein electric charge capture layer 204 for example is silicon oxide/silicon nitride/silicon oxide layer (oxide/nitride/oxide layer, be called for short ONO layer), its formation method for example utilizes boiler tube to form layer of oxide layer earlier in substrate, rely on low-pressure chemical vapor deposition (low pressure chemical vapor deposition again, be called for short LPCVD) on oxide layer, form one deck silicon nitride layer, utilize thermal oxidation method on silicon nitride layer, to form one deck silicon oxide layer afterwards again.
Then, please refer to Fig. 2 C, utilize the lithography manufacture craft, come out in the predetermined zone 206 that forms embedded type bit line (buried bit line is called for short buried B/L) in the substrate 200.Wherein, irrigation canals and ditches 202 are crossed in the predetermined zone 206 that forms embedded type bit line.
Then, please refer to Fig. 2 D, form embedded type bit line 208 in the zone 206 that substrate 200 exposes, its method for example ion is implanted manufacture craft.
Subsequently, please refer to Fig. 2 E, form one deck embedded type bit line oxide layer 210 in the surface that embedded type bit line 208 is exposed, its formation method for example is to utilize the boiler tube heated oxide to form.
At last, please refer to Fig. 2 F, form word line (word line is called for short W/L) 212 in irrigation canals and ditches 202 tops, word line 212 covers irrigation canals and ditches 202 and crosses embedded type bit line 208, and wherein the material of word line 212 for example is a polysilicon.In addition, wordline width 214 in Fig. 2 F for example is the same with the wordline width of known substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) non-voltile memory, thus, under the situation that does not change the memory devices size, word line of the present invention is because be to be formed on the irrigation canals and ditches of substrate, make channel on its Width, also be bending, so have more known many channel currents.
For describing in detail, please refer to Fig. 3 and shown in Figure 4 according to the formed substrate/silicon oxide/silicon nitride/silicon oxide of the present invention/silicon (SONOS) non-volatile internal memory structure.
Fig. 3 is the structural representation according to the III-III section of Fig. 2 F.
Please refer to Fig. 3, word line 212 is arranged in substrate 200, and between substrate 200 and word line 212, has one deck electric charge capture layer 204, and in electric charge capture layer 204 substrate on two sides 200, have embedded type bit line 208, and between embedded type bit line 208 and word line 212, embedded type bit line oxide layer 210 is arranged.Structure by Fig. 3 also can't clearly demonstrate feature of the present invention, so please continue with reference to shown in Figure 4.
Fig. 4 is the structural representation according to the IV-IV section of Fig. 2 F.
Please refer to Fig. 4, substrate 200 has irrigation canals and ditches 202, and the embedded type bit line 208 vertical with irrigation canals and ditches 202 directions arranged in substrate 200, have word line 212 to be covered with in addition on irrigation canals and ditches 202, and word line 212 is crossed embedded type bit line 208.In addition, one deck embedded type bit line oxide layer 210 is arranged between embedded type bit line 208 and word line 212.
Therefore, feature of the present invention comprises:
1. the present invention is formed at the word line of substrate/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) non-voltile memory on the irrigation canals and ditches of substrate, and crosses the embedded type bit line of irrigation canals and ditches.Because the channel of internal memory is bending in the direction of its width, so under the situation of the size constancy of memory devices, can increase channel current.
2. because the present invention can increase channel current, so can make the difference change of memory cell between the channel current of the channel current of state " 1 " and state " 0 " greatly.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly has the knack of this operator, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention defines and is as the criterion when looking claims.
Claims (12)
1. non-voltile memory comprises:
One substrate has irrigation canals and ditches in this substrate;
One embedded type bit line is crossed this irrigation canals and ditches;
One word line covers these irrigation canals and ditches at least and crosses this embedded type bit line;
One electric charge capture layer is between this substrate and this word line.
2. non-voltile memory as claimed in claim 1 is characterized in that: wherein the shape of these irrigation canals and ditches comprises U-shaped.
3. non-voltile memory as claimed in claim 1 is characterized in that: wherein this electric charge capture layer comprises the silicon oxide/silicon nitride/silicon oxide layer.
4. non-voltile memory as claimed in claim 1 is characterized in that: wherein also comprise an embedded type bit line oxide layer between this embedded type bit line and this word line.
5. non-voltile memory as claimed in claim 1 is characterized in that: wherein the material of this word line comprises polysilicon.
6. the manufacture method of a non-voltile memory is characterized in that: comprising:
One substrate is provided;
In this substrate, form irrigation canals and ditches;
In this substrate, form an electric charge capture layer, and cover this irrigation canals and ditches surface;
Expose this substrate of part to form a zone, wherein this irrigation canals and ditches are crossed in this zone;
In this substrate in this zone, form an embedded type bit line;
Form an embedded type bit line oxide layer in the surface that this embedded type bit line exposed;
On this electric charge capture layer, form a word line, covering this irrigation canals and ditches, and cross this embedded type bit line.
7. the manufacture method of non-voltile memory as claimed in claim 6, it is characterized in that: wherein the shape of these irrigation canals and ditches comprises U-shaped.
8. the manufacture method of non-voltile memory as claimed in claim 7 is characterized in that: this step that wherein forms these irrigation canals and ditches in this substrate comprises the anisotropic etching manufacture craft.
9. the manufacture method of non-voltile memory as claimed in claim 6, it is characterized in that: wherein this electric charge capture layer comprises the silicon oxide/silicon nitride/silicon oxide layer.
10. the manufacture method of non-voltile memory as claimed in claim 9 is characterized in that: wherein form this step of this electric charge capture layer in this substrate, comprising:
Utilize boiler tube in this substrate, to form one first oxide layer;
Rely on low-pressure chemical vapor deposition on this first oxide layer, to form a silicon nitride layer;
Utilize thermal oxidation method on this silicon nitride layer, to form one second silicon oxide layer.
11. the manufacture method of non-voltile memory as claimed in claim 6 is characterized in that: this step that wherein forms this embedded type bit line in this substrate in this zone comprises ion implantation manufacture craft.
12. the manufacture method of non-voltile memory as claimed in claim 6 is characterized in that: wherein the material of this word line comprises polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02107552.2A CN1260821C (en) | 2002-03-15 | 2002-03-15 | Nonvolatile memory and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02107552.2A CN1260821C (en) | 2002-03-15 | 2002-03-15 | Nonvolatile memory and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1445858A true CN1445858A (en) | 2003-10-01 |
| CN1260821C CN1260821C (en) | 2006-06-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02107552.2A Expired - Fee Related CN1260821C (en) | 2002-03-15 | 2002-03-15 | Nonvolatile memory and its manufacturing method |
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| Country | Link |
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| CN (1) | CN1260821C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309053C (en) * | 2004-03-26 | 2007-04-04 | 力晶半导体股份有限公司 | Method for producing flash storing device |
| CN116940120A (en) * | 2023-09-18 | 2023-10-24 | 上海领耐半导体技术有限公司 | NOR flash memory with pairing structure and manufacturing method thereof |
-
2002
- 2002-03-15 CN CN02107552.2A patent/CN1260821C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309053C (en) * | 2004-03-26 | 2007-04-04 | 力晶半导体股份有限公司 | Method for producing flash storing device |
| CN116940120A (en) * | 2023-09-18 | 2023-10-24 | 上海领耐半导体技术有限公司 | NOR flash memory with pairing structure and manufacturing method thereof |
| CN116940120B (en) * | 2023-09-18 | 2024-01-05 | 上海领耐半导体技术有限公司 | NOR flash memory with pairing structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1260821C (en) | 2006-06-21 |
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Granted publication date: 20060621 Termination date: 20210315 |