CN1441478A - Vertical semiconductor variable resistor device and its making process - Google Patents
Vertical semiconductor variable resistor device and its making process Download PDFInfo
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- CN1441478A CN1441478A CN 02105193 CN02105193A CN1441478A CN 1441478 A CN1441478 A CN 1441478A CN 02105193 CN02105193 CN 02105193 CN 02105193 A CN02105193 A CN 02105193A CN 1441478 A CN1441478 A CN 1441478A
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Abstract
This invention provides a vertical semiconductor variable resistance device including a basis, an insulation layer, a first and second doped zones in which, the basis has a slot filled up with the insulation layer, the first and second doped zones are set at both sides of the slot. The first doped zone has a control potential influencing a resistor between the second doped zone and the basis which gets varied, in addition, this invention also provides a reference voltage generator desiged on the vertical semiconductor variable resistance device with good voltage stability.
Description
Technical field
The invention relates to a kind of semiconductor device, be particularly to a kind of vertical semiconductor variable resistor device and manufacture method thereof, can use less circuit area to finish and the identical function of electric crystal.
Background of invention
Shallow ridges completely cuts off method (STI) because it can reach minimum isolation spacing, splendid flatness and anti-breech lock ability, makes it become the most frequently used method of coming isolated component in the small size complementary metal oxide semiconductor (CMOS).
Figure 1A and Figure 1B have shown the semiconductor device profile that may form in the isolated method of shallow ridges.
Four in Figure 1A, in the substrate 1 of using the N passage area, have been occurred by groove 111a-111d and fill up the shallow isolating trough layer 11a-11d that the silicon oxide layer 112 of those grooves is formed.These shallow isolating trough layers 11a-11d is in order to the employed active region of each element (Active Area) is kept apart, to provide appropriate insulation at each interelement.Because the cmos element of each mutually insulated, the relative position of its gate and source, drain does not have certain relation, may occur the position relation as shown in Figure 1A between three elements, promptly source/the drain area 13,14 of the channel region of gate 12 belows of a certain element and other two elements is adjacent.This kind situation is in greater than the processing procedure more than the 0.13 μ m, and shallow isolating trough layer 11a-11d still can provide suitable isolation and make these three elements can the phase mutual interference.
Figure 1B has then shown the profile in using the P passage area.Similarly, four have been occurred in the substrate 1 by groove 111e-111h and fill up the shallow isolating trough layer 11e-11h that the silicon oxide layer 112 of those grooves is formed.These shallow isolating trough layers 11e-11h is in order to the employed active region of each element is kept apart, to provide appropriate insulation at each interelement.Because the cmos element of each mutually insulated, the relative position of its gate and source, drain does not have certain relation, may occur the position relation as shown in Figure 1B between three elements, promptly source/the drain area 16,17 of the channel region of gate 15 belows of a certain element and other two elements is adjacent.This kind situation is in greater than the processing procedure more than the 0.13 μ m, and shallow isolating trough layer 11e-11h still can provide suitable isolation and make these three elements can the phase mutual interference.
Yet, in less than the processing procedure below the 0.13 μ m, because the spacing that shallow structure is isolated has been contracted to below about 0.1 μ m, making the effect of its isolation begin to produce goes down, wear the problem of tunnel (fieldpenetration) and produce and have electric field, meaning is promptly in Figure 1A or Figure 1B, doped region 13,14 or 16,17 and gate 12 or 15 below channel regions between potential difference may produce one and pass the electric field of shallow isolating trough layer 11b, 11c or 11f, 11g and below gate 12 or 15, generate an exhaustion region, the situation of generating device phase mutual interference.What is more, the electric field that potential difference produced between gate 12 or 15 edges and gate lower zone also can make this kind phenomenon more serious.
Traditionally, the phenomenon that this kind electric field is worn tunnel is regarded as and must eliminates, as J.H.Sim, J.K.Lee and K.Kim disclosed [High-perforance cell transistor design usingmetallic shield embedded shallow trench isolation for Gbit generationDRAM ' s], IEEE Transaction on Electron Devices, Vol.46, No.6, p.1212-1217,1999.After wherein being lining oxide layer (linear oxide) formation that utilizes in shallow ridges, form the metal level of a ground connection again, the effect of coming reinforced insulation.Yet, the not positive new circuit element of phenomenon design that utilizes this kind electric field to wear tunnel.
Summary of the invention
In order to address the above problem, the invention provides a kind of vertical semiconductor variable resistor device and manufacture method thereof, the shallow isolating trough layer electric field that direct utilization is regarded as being eliminated traditionally worn the tunnel phenomenon and designed the element that makes new advances, variable-resistance function can be provided in analogous circuit, the function of similar general electric crystal switch also can be provided in logical circuit.
First purpose of the present invention is to provide a kind of vertical semiconductor variable resistor device, comprises a substrate, an insulating barrier, first and second doped region.Substrate has a groove.Insulating barrier fills up the groove of this substrate.First and second doped region lays respectively at the both sides of this groove.Wherein, this first doped region has a CONTROLLED POTENTIAL, and the resistance between this second doped region and this substrate is subjected to the influence of this CONTROLLED POTENTIAL and changes.
Second purpose of the present invention is to provide a kind of manufacture method of vertical semiconductor variable resistor device, may further comprise the steps.One substrate is provided.In this substrate, form a groove.Form the groove that an insulating barrier fills up this substrate.Form first and second doped region in these groove both sides.Wherein, this first doped region has a CONTROLLED POTENTIAL, asks a resistance between second doped region and this substrate to be subjected to the influence of this controlling resistance and changes.
The 3rd purpose of the present invention is to provide a kind of reference voltage generator, comprises a substrate, an insulating barrier, first, second, third, fourth, the 5th doped region, a differential amplifier, first and second current source.Substrate has a wellblock that is connected to one first current potential, and tool has one first, second and third groove in this wellblock.Insulating barrier fills up this first, second and third groove respectively.The first, second, third, fourth and the 5th doped region, be formed between the side, first and second groove of first groove, between the second and the 3rd groove respectively, the 3rd groove one side and this first doped region below, and this first doped region connects and receives one second current potential.Two inputs of differential amplifier electrically connect with this second and third doped region respectively, and output then electrically connects with the 4th doped region.First and second current source then is connected between one the 3rd current potential and this differential amplifier two inputs.
The 4th purpose of the present invention is to provide a kind of reference voltage generator, comprises a substrate, an insulating barrier, the one first, second, third, fourth, the 5th doped region, a differential amplifier, first and second current source.Substrate has one first, second and third groove, connects to receive one first current potential.Insulating barrier fills up this first, second and third groove respectively.The first, second, third, fourth and the 5th doped region is formed between the side, first and second groove of first groove, between the second and the 3rd groove respectively, the 3rd groove one side and this first doped region below, and this first doped region connects and receives one second current potential.Two inputs of differential amplifier electrically connect with this second and third doped region respectively, and output then electrically connects with the 4th doped region.First and second current source is connected between one the 3rd current potential and this differential amplifier two inputs.
By this, the present invention utilizes the electric field of shallow isolating trough layer to wear the tunnel phenomenon and can control resistance value in the groove opposite side zone by the other doped region current potential of groove, forms a variable resistor device and can be applied in the analogous circuit; Simultaneously, if the rate of change of this variable resistor device is designed when very high, its performance is a similar electric crystal switch, and can be applied in the logical circuit.
Description of drawings
Figure 1A, 1B show the profile of a conventional semiconductor device;
Fig. 2 A-2K shows the manufacturing process of the vertical-type variable resistor device in one embodiment of the invention;
Fig. 3 shows the vertical-type variable resistor device in one embodiment of the invention;
Fig. 4 A-4B shows the operation when the vertical-type variable resistor device is used as switching device in one embodiment of the invention;
Fig. 5 A-5B shows reference voltage generator and equivalent electric circuit thereof in one embodiment of the invention;
Fig. 6 A-6B shows reference voltage generator and equivalent electric circuit thereof in one embodiment of the invention
Symbol description:
1,21,51,61---substrate;
111a-111d, 111e-111h, 24a-24i---groove;
112,22,25,28---silicon oxide layer;
11a-111d, 11e-11h, 53a-53e, 63a-63e---shallow isolating trough layer;
12,15,29---gate;
23---nitration case;
26,52---N type wellblock
271,272,301-308,541-545,641-645---doped region;
31---segregant;
321,322---exhaustion region;
323,324---accumulation region;
55,65---differential amplifier;
561,562,661,662---current source.
Embodiment
Below, with regard to the embodiment of graphic explanation a kind of vertical semiconductor variable resistor device of the present invention and manufacture method thereof.
Fig. 2 A to Fig. 2 K shows the manufacturing process of one embodiment of the invention.
At first, shown in Fig. 2 A, provide a P type silicon substrate 21.
Then, shown in Fig. 2 B, in P type silicon substrate 21, form a pad oxide (Pad Oxide) 22 and one nitration case (Si
3N
4) 23.
Then, shown in Fig. 2 C, etching is carried out in nitration case 23, oxide layer 22 and substrate 21, and in substrate 21, formed groove 24a-24i.
Moreover, shown in Fig. 2 D, continue groove 24b-24i is carried out etching, making its degree of depth is dark than groove 24a.
Then, shown in Fig. 2 E, in groove 24a-24i, form the silicon oxide layer 25 that fills up those grooves.Groove 24a-24i and insert that wherein silicon oxide layer 25 is common to be formed the shallow isolating trough layers and define the active region at element place.
Then, shown in Fig. 2 F, in substrate 21, form N type wellblock 26, two groove 24a and groove 24b-24e are positioned among the N type wellblock 26.
Moreover, shown in Fig. 2 G, between groove 24c and 24d, and in the substrate between groove 24g and the 24h 21, form the light doped region 271 of a N type and P type and 272 respectively.
Then, shown in Fig. 2 H, carry out the formation step of traditional cmos gate, promptly in substrate 21, form a gate pole oxidation layer 28, on gate pole oxidation layer 28, deposit the usefulness of a polysilicon layer 29 afterwards again as gate.
Then, shown in Fig. 2 I, proceeding the making step of traditional cmos, is shade with gate 29 promptly, uses ionic-implantation to form light doped region 301 of N type and the light doped region 302 of P type in substrate 21, and forms segregant (spacer) 31 in gate 29 both sides.
Moreover, shown in Fig. 2 J, in substrate 21, form dense doped region 303 of N type and the dense doped region 304 of P type with ionic-implantation again, and form source/drain of two P, N type MOS, simultaneously, also form dense doped region 305 of P type and the dense doped region 306 of N type in the substrate 21 between groove 24b and 24c, groove 24d and 24e groove 24f and 24g and groove 24h and 24i.
At last, shown in Fig. 2 K, dense doped region 305 of the darker P type of depth of drive and the dense doped region 306 of N type in the substrate 21 between groove 24b and 24C, groove 24d and 24e, groove 24f and 24g and groove 24h and 24i again.
From the above, in the present embodiment, the processing procedure of cooperation traditional cmos can form vertical-type variable resistor device as shown in Figure 3.Below will cooperate Fig. 3 that the operation of this device is described.
As shown in Figure 3, have a dead resistance Rn and a Rp respectively between N type doped region 271 and N type wellblock 26 and P type doped region 272 and P type substrate 21, meaning promptly has resistance R n and Rp respectively between end points Xn and Ynw and Xp and Ypsub.Dense doped region 305 and 306 receive a current potential Vp and a Vn respectively.Because the current potential of Vp and Vn can produce an electric field and pass through groove 24c, 24d, 24g, 24h and oxide layer 25 formed shallow isolating trough layers, therefore exhaustion region (depletion region) 321 and 322 can appear in the sidewall between groove 24C, 24d and groove 24g, 24h.Exhaustion region 321 and 322 size can be in order to the sizes of controlling resistance Rn and Rp, and meaning is that Vp and Vn are the CONTROLLED POTENTIAL of controlling resistance Rn and Rp size.In addition, can also adjust the rate of change of its resistance value by the doping content of controlling resistance Rn and Rp region.
In addition, in the above-described embodiment, with the dense doped region 305 of P type be replaced by the dense doped region of N type and with the dense doped region 306 of N type more mould be the dense doped region of P type, and in 2K figure an extra respectively P type and the N type doped region 307 of forming in the wellblock below dense doped region 305 and 306 26 and the substrate 21,308, as dense doped region 305,306 and the isolation of 21 of N type wellblock 26 and substrates, give resistance R n and Rp region one suitable doping content simultaneously, obtain a high resistance rate of change, the switching device that variable resistor device formation one that so promptly can be above-mentioned and electric crystal have said function is shown in Fig. 4 A and 4B.Below will cooperate the operation of this device of 4A and 4B figure explanation.
Shown in Fig. 4 A, when the current potential of the Vn current potential less than end points Ynw, and the current potential of Vp can make the sidewall between groove 24c, 24d and groove 24g, 24h exhaustion region (depletion region) 321 and 322 occur during greater than the current potential of end points Ypsub.Because the variable resistor device among Fig. 4 A has a high resistance rate of change, will make this moment between end points Xn, Ynw and end points Xp, the Ypsub resistance very big and be similar to and open circuit.
Shown in Fig. 4 B, when the current potential of the Vn current potential greater than end points Ynw, and the current potential of Vp can make the sidewall between groove 24c, 24d and groove 24g, 24h accumulation region (accumulation region) 323 and 324 occur during less than the current potential of end points Ypsub.Accumulation region 323 and 324 generation are owing to wear the tunnel electric field and electronics or electric hole are attracted to trenched side-wall cause, and this zone has very good electrical conductivity.Therefore, make resistance between end points Xn, Ynw and end points Xp, Ypsub very little and be similar to short circuit.
From the above, variable resistor device in the present embodiment is after the doping content of the electrical and resistance region of suitably revising doped region, can become the controllable switch device of a similar electric crystal, use Vn or Vp as CONTROLLED POTENTIAL, the conducting in decision-making circuit path and disconnection.
In addition, because the variable resistor device among the present invention can have the characteristic of similar electric crystal, therefore can use it in the reference voltage generator.
Fig. 5 A and 5B have shown the reference voltage generator in one embodiment of the invention.Wherein, Fig. 5 B is the equivalent circuit diagram of Fig. 5 A.
Reference voltage generator comprises a P type substrate 51, a N type wellblock 52, five shallow isolating trough layer 53a-53e, three N type doped region 541-543, two P type doped regions 544,545, a differential amplifier 55 and two current sources 561,562.Wherein, substrate 51 is to be connected to current potential Vss, and wellblock 52 is connected to current potential Vcc, doped region 541 ground connection, and two current sources 561,562 are connected between the positive and negative input and current potential Vss of differential amplifier 55.The positive and negative input of differential amplifier also is connected to N type doped region 542 and 543 respectively.544 outputs that are connected to differential amplifier 55 of P type doped region.In wellblock 52, have four dead resistance Rv1, Rv2, Rnw1, Rnw2.P type doped region 545 is in order to electrical isolation doped region 541 and wellblock 52.
In Fig. 5 A, P type substrate 51, N type wellblock 52, five shallow isolating trough layer 53a-53e, three N type doped region 541-543 and P type doped region 544 have constituted the variable resistor device of two high resistance rates of change jointly, its equivalent electric circuit below cooperates Fig. 5 B that its operation is described shown in Fig. 5 B.
Owing to there is current source 561 that the electric current variable resistor device Rv1 that flows through is provided, and its CONTROLLED POTENTIAL is zero (ground connection), make differential amplifier 55 positive input terminals and the potential difference of its CONTROLLED POTENTIAL end should equal the potential difference (even potential difference that the accumulation region 57 among meaning Fig. 5 A produces) that makes variable resistor device Rv1 become conducting state, if this potential difference is Vtacn, then V
+=-Vtacn=V
-In addition, current source 562 also produces an electric current of flowing through variable resistor device Rv2, so the negative input end of differential amplifier 55 and its CONTROLLED POTENTIAL end, be Vo, also having one and make variable resistor device Rv2 become the potential difference of conducting state, is Vtacp, then Vo=V as if this potential difference
-Ten Vtacp.With V
-=-Vtacn substitution following formula obtains Vo=Vtacp-Vtacn.The magnitude of voltage of this Vo is owing to be make critical voltage value that accumulation region produces in two variable resistor devices poor, therefore can be as the usefulness of a fixing reference voltage.Simultaneously, owing to structurally be to be vertical-type and traditional less contact hole and line of FET electric crystal needs that use, so the circuit area that uses is less, and because the reference voltage Vo of output utilizes the difference of two flat-band potentials (flat-band voltage) to produce, so also more traditional reference voltage device temperature influence and changing not.
Fig. 6 A and Fig. 6 B have then shown the reference voltage generator in another embodiment of the present invention.Wherein, Fig. 6 B figure is the equivalent circuit diagram of Fig. 6 A.
Reference voltage generator comprises a P type substrate 61, five shallow isolating trough layer 63a-63e, three P type doped region 641-643, two N type doped regions 644,645, a differential amplifier 65 and two current sources 661,662.Wherein, substrate 61 is to be connected to current potential Vss, doped region 641 ground connection, and two current sources 661,662 are connected between the positive and negative input and current potential Vcc of differential amplifier 65.The positive and negative input of differential amplifier 65 also is connected to P type doped region 642 and 643 respectively.644 outputs that are connected to differential amplifier 65 of N type doped region.In substrate 61, have four dead resistance Rv1, Rv2, Rnw1, Rnw2.N type doped region 645 is in order to electrical isolation doped region 641 and substrate 61.
In Fig. 6 A, P type substrate 61, five shallow isolating trough layer 63a-63e, three P type doped region 641-643 and N type doped region 644 have constituted the variable resistor device of two high resistance rates of change jointly, its equivalent electric circuit below cooperates Fig. 6 B that its operation is described shown in Fig. 6 B.
Owing to there is current source 661 that the electric current variable resistor device Rv1 that flows through is provided, and its CONTROLLED POTENTIAL is zero (ground connection), make differential amplifier 65 positive input terminals and the potential difference of its CONTROLLED POTENTIAL end should equal the potential difference (even potential difference that the accumulation region 67 among meaning Fig. 6 A produces) that makes variable resistor device Rv1 become conducting state, if this potential difference is Vtacp, then V
+=-Vtacp=V
-In addition, current source 662 also produces an electric current of flowing through variable resistor device Rv2, so the negative input end of differential amplifier 65 and its CONTROLLED POTENTIAL end, be Vo, also having one and make variable resistor device Rv2 become the potential difference of conducting state, is Vtacn, then Vo=V as if this potential difference
-+ Vtacn.With V
-=-Vtacp brings following formula into, obtains Vo=Vtacn-Vtacp.Similarly, the magnitude of voltage of this Vo is owing to be make critical voltage value that accumulation region produces in two variable resistor devices poor, therefore can be as the usefulness of a fixing reference voltage.Simultaneously, owing to structurally be to be vertical-type and to use less contact hole and the line of FET electric crystal needs than system, so the circuit area that uses is less, and because the reference voltage Vo of output utilizes the difference of two flat-band potentials (flat-band voltage) to produce, so also more traditional reference voltage device temperature influence and changing not.
Reference voltage generator among Fig. 5 A, 5B and 6A, the 6B can also current potential Vss and Vcc are exchanged, the direction counter-rotating of current source 561,562,661,662 and obtain having the reference voltage generator of identical function, this kind is to operate in the saturation region (Saturation region) with reference to voltage generator.Detailed structure repeats no more with operation herein.
Comprehensively above-mentioned, the present invention utilizes the electric field tunneling effect of shallow isolating trough layer to design a kind of variable resistor device of vertical-type, can control resistance value between two-end-point via a CONTROLLED POTENTIAL, and after giving the suitable doping content of resistance area, can present an extreme high resistance rate of change, and can further provide the switching function of similar electric crystal, when this variable resistor device is applied to replace traditional FET electric crystal in the reference voltage generator, not only can save circuit area, also have the characteristic that is difficult for temperature influence and produces change in voltage because of its vertical stratification.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.
Claims (24)
1. vertical semiconductor variable resistor device comprises:
One substrate has a groove;
One insulating barrier fills up the groove of this substrate; And
One first and second doped region lays respectively at the both sides of this groove;
Wherein, this first doped region has a CONTROLLED POTENTIAL, between this second doped region and this substrate
One resistance is subjected to the influence of this CONTROLLED POTENTIAL and changes.
2. vertical semiconductor variable resistor device as claimed in claim 1, wherein this insulating barrier is one to have the insulating barrier of high k value.
3. vertical semiconductor variable resistor device as claimed in claim 1, wherein this CONTROLLED POTENTIAL makes generation one exhaustion region in this substrate and the resistance between this second doped region and this substrate is increased.
4. vertical semiconductor variable resistor device as claimed in claim 1, wherein this CONTROLLED POTENTIAL makes generation one accumulation region in this substrate and the resistance between this second doped region and this substrate is reduced.
5. vertical semiconductor variable resistor device as claimed in claim 1 wherein more comprises one the 3rd doped region, is positioned at this first doped region below.
6. vertical semiconductor variable resistor device as claimed in claim 5, wherein this substrate is a P type substrate, and this first, second doped region is a P type doped region, and the 3rd doped region is a N type doped region.
7. vertical semiconductor variable resistor device as claimed in claim 1 wherein more comprises a wellblock, is formed in this substrate, and this groove and this first, second doped region all are positioned among this wellblock.
8. vertical semiconductor variable resistor device as claimed in claim 7, wherein this substrate is a P type substrate, and this first, second doped region is a P type doped region, and this wellblock is a N type wellblock.
9. vertical semiconductor variable resistor device as claimed in claim 7 wherein more comprises one the 3rd doped region, is positioned at this first doped region below.
10. vertical semiconductor variable resistor device as claimed in claim 9, wherein this substrate is a P type substrate, and this first, the 3rd doped region is a N type doped region, and the 3rd doped region is a P type doped region, and this wellblock is a N type wellblock.
11. the manufacture method of a vertical semiconductor variable resistor device may further comprise the steps:
One substrate is provided;
In this substrate, form a groove;
Form the groove that an insulating barrier fills up this substrate; And
Form first and second doped region in these groove both sides;
Wherein, this first doped region has a CONTROLLED POTENTIAL, and the resistance between this second doped region and this substrate is subjected to the influence of this CONTROLLED POTENTIAL and changes.
12. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 10, wherein this insulating barrier is one to have the insulating barrier of high k value.
13. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 10 wherein more may further comprise the steps:
Form one the 3rd doped region in this substrate below this first doped region.
14. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 13, wherein this substrate is a P type substrate, and this first, second doped region is a P type doped region, and the 3rd doped region is a N type doped region.
15. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 10 wherein more may further comprise the steps:
In this substrate, form a wellblock, this groove and this first, second doped region all are positioned among this wellblock.
16. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 15, wherein this substrate is a P type substrate, and this first, second doped region is a P type doped region, and this wellblock is a N type wellblock.
17. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 15 wherein more may further comprise the steps:
Form one the 3rd doped region in this wellblock below this first doped region.
18. the manufacture method of vertical semiconductor variable resistor device as claimed in claim 17, wherein this substrate is a P type substrate, and this first, second doped region is a N type doped region, and the 3rd doped region is a P type doped region, and this wellblock is a N type wellblock.
19. a reference voltage generator comprises:
One substrate has one and is connected to the wellblock of one first current potential, and have one first, second and third groove in this wellblock;
One insulating barrier fills up this first, second and third groove respectively;
The one first, second, third, fourth and the 5th doped region, be formed between the side, first and second structure list of first groove, between the second and the 3rd groove respectively, the 3rd groove one side and this first doped region below, and this first doped region connects and receives one second current potential;
One differential amplifier, two inputs electrically connect with this second and third doped region respectively, and output then electrically connects with the 4th doped region; And
One first and second current source is connected between one the 3rd current potential and this differential amplifier two inputs.
20. reference voltage generator as claimed in claim 19, wherein this insulating barrier is one to have the insulating barrier of high k value.
21. reference voltage generator as claimed in claim 19, wherein this substrate is a P type substrate, and this wellblock is a N type wellblock, and this first, second and third doped region is a N type doped region, and the 4th and the 5th doped region is a P type doped region.
22. a reference voltage generator comprises:
One substrate has one first, second and third groove, connects to receive one first current potential;
One insulating barrier fills up this first, second and third groove respectively;
The one first, second, third, fourth and the 5th doped region, be formed between the side, first and second groove of first groove, between the second and the 3rd groove respectively, the 3rd groove one side and this first doped region below, and this first doped region connects and receives one second current potential;
One differential amplifier, two inputs electrically connect with this second and third doped region respectively, and output then electrically connects with the 4th doped region; And
One first and second current source is connected between one the 3rd current potential and this differential amplifier two inputs.
23. reference voltage generator as claimed in claim 22, wherein this insulating barrier is one to have the insulating barrier of high k value.
24. reference voltage generator as claimed in claim 22, wherein this substrate is a P type substrate, and this first, second, third doped region is a P type doped region, and the 4th and the 5th doped region is a N type doped region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021051933A CN1189933C (en) | 2002-02-26 | 2002-02-26 | Vertical semiconductor variable resistor device and its making process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021051933A CN1189933C (en) | 2002-02-26 | 2002-02-26 | Vertical semiconductor variable resistor device and its making process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1441478A true CN1441478A (en) | 2003-09-10 |
| CN1189933C CN1189933C (en) | 2005-02-16 |
Family
ID=27768435
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021051933A Expired - Lifetime CN1189933C (en) | 2002-02-26 | 2002-02-26 | Vertical semiconductor variable resistor device and its making process |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171748B (en) * | 2005-06-07 | 2010-05-19 | 索尼株式会社 | Resistor circuit |
| CN108511422A (en) * | 2017-02-28 | 2018-09-07 | 意法半导体(克洛尔2)公司 | Integrated circuit with improved resistance region |
-
2002
- 2002-02-26 CN CNB021051933A patent/CN1189933C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171748B (en) * | 2005-06-07 | 2010-05-19 | 索尼株式会社 | Resistor circuit |
| CN108511422A (en) * | 2017-02-28 | 2018-09-07 | 意法半导体(克洛尔2)公司 | Integrated circuit with improved resistance region |
| CN108511422B (en) * | 2017-02-28 | 2021-11-12 | 意法半导体(克洛尔2)公司 | Integrated circuit with improved resistance area |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1189933C (en) | 2005-02-16 |
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