CN1437436A - Circuit board design method - Google Patents
Circuit board design method Download PDFInfo
- Publication number
- CN1437436A CN1437436A CN 02103656 CN02103656A CN1437436A CN 1437436 A CN1437436 A CN 1437436A CN 02103656 CN02103656 CN 02103656 CN 02103656 A CN02103656 A CN 02103656A CN 1437436 A CN1437436 A CN 1437436A
- Authority
- CN
- China
- Prior art keywords
- layer
- reference planes
- circuit board
- copper
- signal lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
A design method of circuit board carries on surface set-up of the circuit board and wiring set-up of routing layer first and divided out the signal routing which can not be finished at routing layer but to be finished in reference plane layer where should be carried on with copper cladding that its nature should be keps as original nature of the reference plane layer. The routing layer adjacent to the reference plane layer set with signal routing will also be cladded with copper. Which has its nature as "earth" and at least the optical plotting file will be produced as well as platemaking of the circuit board should be carried on according to the produced file.
Description
Technical field
The present invention relates to the method for designing of the circuit board in the electronic equipment.
Background technology
In the board design in existing communication apparatus and high speed measuring equipment, the integrality of signal and electromagnetic compatibility (EMC) performance requirement is more and more higher, signal density is increasing, and the cost requirement of design is more and more lower, this just requires, and will satisfy signal lead has good reference planes on the one hand in the design of circuit board, the design number of plies that need as far as possible reduce circuit board is arranged in addition on the one hand, lower the board design cost.But, adopt existing circuit board designing method, be difficult to make above-mentioned contradiction to reach unified.For example, in the back plate design of communication apparatus, the backboard signal has that kind is few, classification is clear, cabling can not have characteristics such as via hole.So just may have following special circumstances: most of signal can be finished cabling at the routing layer of estimating in back plate design, but when planning owing to backboard, remaining a few signals can't pass through the holding wire of other types, for example therefore distributed clock must be provided with the wiring that special signals layer is finished these a few signals lines.These need the signal of special wiring, control signal for example, and it is few to have quantity usually, impedance is had requirement, and signal quality also needs characteristics such as assurance, if adopt existing circuit board designing method, can only increase the wiring number of plies of backboard, therefore will cause the design cost of circuit board to increase.
For the wiring layer in the multilayer circuit board design, for the integrality and the impedance requirement that guarantee signal, each wiring layer requires the reference planes of its adjacent layer as it usually.According to traditional circuit board requirement is set, has reference planes at least in order to guarantee each signals layer, the reference planes number that the entire circuit plate needs is: n=[rounds (N/3)]+1, wherein: N is the circuit board number of plies, n is theoretical minimum reference planes number.That is to say, wherein to have n reference planes at least for the circuit board of a N layer.With one ten layer circuit board is example, wherein has 4 layers to be reference planes.In the reality, have the signal of gigabit with upper frequency in the ifs circuit plate, the both sides that then require this signal routing plane all are reference planes, and two reference planes are promptly arranged, and make that reference planes will be more in the number of plies of entire circuit plate.
In existing circuit board designing method, reference planes can only be as the power supply or the ground level of strictness, can not cabling in reference planes, if two problems below the reference planes cabling will produce: the one, the reference planes of the circuit signal of original signals layer are destroyed, and its integrality and impedance might be able to not meet the demands; The 2nd, for the wiring in reference planes, this layer both sides all are former signals layers, just do not have reference planes, its signal integrity not to guarantee at all, simultaneously also with radiation and power supply that disturbs the original reference planes of introducing and ground.Therefore in existing board design, if there is a spot of holding wire not finish cabling at the prearranged signal layer, can only increase wiring layer in circuit board, certainly corresponding reference planes also must increase, thereby have increased the circuit board cost.
Summary of the invention
The object of the present invention is to provide a kind of method for designing that can reduce the circuit board cost.
For achieving the above object, the method for designing of circuit board provided by the invention comprises:
(1) requires to finish the aspect setting of circuit board and the wiring setting of routing layer according to common board design, mark off and to be scheduled to the signal lead that routing layer is finished;
(2) can't be arranged in the reference planes layer in the signal lead that predetermined routing layer is finished and finish;
(3) the reference planes layer that is provided with signal lead is applied copper, and the attribute of deposited copper keeps original attribute of this reference planes layer;
(4) the adjacent traces layer to the reference planes layer that is provided with signal lead applies copper, the attribute that applies copper be " ";
(5) require to generate light according to common board design and paint file, and carry out the plate-making of circuit board according to this document.
Described adjacent traces layer to reference planes layer that signal lead is arranged applies copper, is that two the adjacent routing layer of reference planes layer that signal lead is arranged are applied copper, also can apply copper by adjacent routing layer to the reference planes layer that signal lead is arranged.
Because the present invention can not finish in the reference planes layer in the signal lead design that predetermined routing layer is finished, and by the reference planes layer that signal lead is arranged is applied copper, and the method that the adjacent traces layer of reference planes layer that signal lead is arranged is applied copper, the cabling that has guaranteed the cabling of signals layer and reference planes all has the reference planes of oneself, thereby can guarantee the signal quality of cabling, and do not need to increase the board design number of plies, therefore adopt the present invention to help when not increasing design difficulty, reduce the cost of circuit board.
Description of drawings
Fig. 1 is the embodiment flow chart of the method for the invention;
Fig. 2 is that the layer of a specific boards is provided with and signal reference planes distribution instance graph.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Essence of the present invention is to adopt deposited copper technology at the reference planes layer of circuit board and routing layer, and making to increase a small amount of cabling at the reference planes layer, and guarantees that the cabling of routing layer and reference planes layer all has reference planes.
Fig. 1 is the embodiment flow chart of the method for the invention, to the understanding of the described method of Fig. 1 with reference to figure 2.According to Fig. 1, at first require to finish the aspect setting of circuit board and the wiring setting of routing layer according to common board design in the 1st step, mark off and can't be scheduled to the signal lead that routing layer is finished.In step 2, can't be arranged on the reference planes cabling at the cabling that predetermined routing layer is finished.Suppose in Fig. 2, can't finish the holding wire of wiring setting on the wiring plane at internal layer reference planes 4 enterprising row wirings, in step 3, the reference planes 4 that are provided with signal lead are applied copper, the attribute that applies copper is identical with original attribute of these reference planes, promptly no matter the attribute of original these reference planes be " power supply " still " ", the attribute behind the deposited copper is constant.Like this, make original routing layer can substitute complete reference planes in the past with the deposited copper of reference planes; Outside two, when reference planes were applied copper, for reducing the influence to signal lead, the copper cash size of applying copper should be provided with as far as possible for a short time.
In Fig. 2, if behind original internal layer reference planes layer 4 enterprising row wiring, the attribute of original ground of this aspect or power supply is destroyed, therefore reference planes 4 are applied copper according to original attribute, if and there was cutting apart of ground or power supply on this plane in the past, also carry out identical cutting apart when applying copper, still can make the reference planes of reference planes layer 4, that is to say that the reference planes of routing layer 3,5 remain complete by applying copper as 3,5 two routing layers of routing layer.
Then the adjacent traces layer that pair is provided with the reference planes layer of signal lead in step 4 applies copper, the attribute of deposited copper be " ".Adjacent traces layer to reference planes layer that signal lead is arranged described here applies copper, be that two the adjacent routing layer of reference planes layer that signal lead is arranged are applied copper, can certainly only apply copper to its adjacent routing layer, will be better but two adjacent routing layers are applied the effect of copper.The copper cash size of applying copper should be as far as possible little, apply copper to the distance of cabling satisfy the circuit board cabling and should be as far as possible little during the requiring of spacing, like this, by applying copper, promptly can simulate reference planes at the signal of reference planes cabling at the adjacent signals layer of reference planes.
Among Fig. 2, because 3,5 layers all is signals layer, the cabling of such 4 layers of increase does not just have reference planes, impedance and signal integrity all can not be guaranteed, in order to make 4 layers reference planes are arranged, handle at 3, the 5 two-layer copper that all apply, because " " reference performance be better than " power supply ", so will apply the attribute of copper all be set to " ", the copper cash that applies copper is simultaneously tried one's best carefully, tries one's best to the distance of cabling little of to guarantee that abundant deposited copper also can be arranged between cabling, after 3 and 5 layers of deposited copper that carries out are finished dealing with, can think that promptly 3 and 5 layers is the reference planes of 4 layers of cabling.
Do the back in step 5, require to generate light according to common board design and paint file, and carry out the plate-making of circuit board according to this document.
Claims (3)
1, a kind of method for designing of circuit board comprises:
(1) carries out the aspect setting of circuit board and the wiring setting of routing layer, mark off and to be scheduled to the signal lead that routing layer is finished;
(2) can't be arranged in the reference planes layer in the signal lead that predetermined routing layer is finished and finish;
(3) the reference planes layer that is provided with signal lead is applied copper, and the attribute of deposited copper keeps original attribute of this reference planes layer;
(4) the adjacent traces layer to the reference planes layer that is provided with signal lead applies copper, the attribute that applies copper be " ";
(5) generate light and paint file, and carry out the plate-making of circuit board according to this document.
2, the method for designing of circuit board according to claim 1 is characterized in that: described adjacent traces layer to the reference planes layer that is provided with signal lead applies copper, is that two the adjacent routing layer of reference planes layer that signal lead is arranged are applied copper.
3, the method for designing of circuit board according to claim 1 is characterized in that: described adjacent traces layer to the reference planes layer that is provided with signal lead applies copper, is that the adjacent routing layer of reference planes layer that signal lead is arranged applied copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02103656XA CN1194591C (en) | 2002-02-04 | 2002-02-04 | Circuit board design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02103656XA CN1194591C (en) | 2002-02-04 | 2002-02-04 | Circuit board design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1437436A true CN1437436A (en) | 2003-08-20 |
| CN1194591C CN1194591C (en) | 2005-03-23 |
Family
ID=27627906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02103656XA Expired - Fee Related CN1194591C (en) | 2002-02-04 | 2002-02-04 | Circuit board design method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1194591C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101175377B (en) * | 2006-10-30 | 2010-08-25 | 英业达股份有限公司 | System and method for removing electronic components |
| CN102291951A (en) * | 2011-06-20 | 2011-12-21 | 华为终端有限公司 | Impedance control method and structure of FPC (Flexible Printed Circuit) |
| CN103167719A (en) * | 2011-12-19 | 2013-06-19 | 联想(北京)有限公司 | Novel wiring method of printed circuit board, printed circuit board and electronic device |
| CN103889140A (en) * | 2012-12-20 | 2014-06-25 | 深圳市共进电子股份有限公司 | Wiring method for double-face printed circuit board |
| US9519308B2 (en) | 2007-03-23 | 2016-12-13 | Huawei Technologies Co., Ltd. | Printed circuit board, design method thereof and mainboard of terminal product |
| CN106446429A (en) * | 2016-09-29 | 2017-02-22 | 全球能源互联网研究院 | Method for partitioning complicated plane of printed circuit board |
| CN107135454A (en) * | 2017-06-13 | 2017-09-05 | 南京钟山苑航空技术有限公司 | A kind of public address set for SUAV |
| CN110035606A (en) * | 2019-03-18 | 2019-07-19 | 武汉精立电子技术有限公司 | A kind of folded method and structure of PCB layer suitable for including analog sensed device circuit |
-
2002
- 2002-02-04 CN CNB02103656XA patent/CN1194591C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101175377B (en) * | 2006-10-30 | 2010-08-25 | 英业达股份有限公司 | System and method for removing electronic components |
| US9519308B2 (en) | 2007-03-23 | 2016-12-13 | Huawei Technologies Co., Ltd. | Printed circuit board, design method thereof and mainboard of terminal product |
| CN102291951A (en) * | 2011-06-20 | 2011-12-21 | 华为终端有限公司 | Impedance control method and structure of FPC (Flexible Printed Circuit) |
| CN102291951B (en) * | 2011-06-20 | 2014-10-08 | 华为终端有限公司 | Impedance control method and structure of FPC (Flexible Printed Circuit) |
| CN103167719A (en) * | 2011-12-19 | 2013-06-19 | 联想(北京)有限公司 | Novel wiring method of printed circuit board, printed circuit board and electronic device |
| CN103167719B (en) * | 2011-12-19 | 2016-07-06 | 联想(北京)有限公司 | The wiring method of printed circuit board (PCB), printed circuit board (PCB) and electronic equipment |
| CN103889140A (en) * | 2012-12-20 | 2014-06-25 | 深圳市共进电子股份有限公司 | Wiring method for double-face printed circuit board |
| CN106446429A (en) * | 2016-09-29 | 2017-02-22 | 全球能源互联网研究院 | Method for partitioning complicated plane of printed circuit board |
| CN106446429B (en) * | 2016-09-29 | 2023-07-21 | 全球能源互联网研究院 | Method for dividing complex plane of printed circuit board |
| CN107135454A (en) * | 2017-06-13 | 2017-09-05 | 南京钟山苑航空技术有限公司 | A kind of public address set for SUAV |
| CN110035606A (en) * | 2019-03-18 | 2019-07-19 | 武汉精立电子技术有限公司 | A kind of folded method and structure of PCB layer suitable for including analog sensed device circuit |
| CN110035606B (en) * | 2019-03-18 | 2023-11-28 | 武汉精立电子技术有限公司 | PCB lamination method and structure suitable for circuit comprising analog sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1194591C (en) | 2005-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5502644A (en) | Process and apparatus for auditing crosstalk and characteristic impedances of printed wiring boards | |
| CN111278227B (en) | Layout and wiring method for PCB Layout of SMT32 system mainboard | |
| US20060061432A1 (en) | Two-layer PCB with impedence control and method of providing the same | |
| CN1194591C (en) | Circuit board design method | |
| CN115329712B (en) | PCB wiring generation method, device, equipment and server board card | |
| CN102291951B (en) | Impedance control method and structure of FPC (Flexible Printed Circuit) | |
| EP1011039A1 (en) | Gap-coupling bus system | |
| CN115510801A (en) | Data transmission system, method, device and storage medium | |
| US7533005B2 (en) | System and method for checking a reference plane of a signal trace in a PCB | |
| CN1719447A (en) | Board pattern designing method of integrated designing element in printed circuit board and its device | |
| Blackwell | Circuit boards | |
| US6917848B1 (en) | Production system for printed wiring board | |
| CN1265689C (en) | Copper-cladding method in circuit board design | |
| US5504423A (en) | Method for modeling interactions in multilayered electronic packaging structures | |
| CN114580337B (en) | Design method of signal reference ground plane, circuit board and server | |
| CN113609808A (en) | PCIExpress signal integrity improvement method for navigation display system | |
| US20040246689A1 (en) | Apparatus and method for mounting a surface mount component in an etched well in a printed circuit board | |
| Raj et al. | Elegant Way of Designing Printed Circuit Board via Multilayer Technique Using Ultiboard 12.0 | |
| CN110337174A (en) | A kind of pcb board and a kind of preparation method of pcb board | |
| Silvestre Bergés et al. | Printed Circuit Board (PCB) design process and fabrication | |
| Belous et al. | Basics of Designing Structures of Printed Circuit Boards of High-Speed Electronic Devices | |
| CN210641126U (en) | PCB board | |
| JP3069422B2 (en) | Method and apparatus for pattern design processing of multilayer printed wiring board | |
| Mardiguian et al. | Printed Circuit Board Design | |
| CN117709166A (en) | Vibration simulation method of circuit board based on multilayer PCB |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HUIZHOU ZHONGJING ELECTRONIC SCIENCE CO., LTD. Free format text: FORMER OWNER: HUAWEI TECHNOLOGY CO., LTD. Effective date: 20090508 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090508 Address after: Guangdong goose Ling Nan Lu Huizhou 7, Lane 3, Beijing Science and Technology Park Patentee after: Huizhou China Eagle Electronic Technology Co., Ltd. Address before: Guangdong Shenzhen science and Technology Park HUAWEI road user service center building intellectual property department Patentee before: Huawei Technologies Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050323 Termination date: 20130204 |