CN1431712A - Random programmable non-volatile semi-conductor storage - Google Patents
Random programmable non-volatile semi-conductor storage Download PDFInfo
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- CN1431712A CN1431712A CN 02100986 CN02100986A CN1431712A CN 1431712 A CN1431712 A CN 1431712A CN 02100986 CN02100986 CN 02100986 CN 02100986 A CN02100986 A CN 02100986A CN 1431712 A CN1431712 A CN 1431712A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000015654 memory Effects 0.000 claims description 79
- 238000002955 isolation Methods 0.000 claims description 10
- 230000005689 Fowler Nordheim tunneling Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- FEWHDZOJQQLPEN-UHFFFAOYSA-N [O].[N].[O] Chemical compound [O].[N].[O] FEWHDZOJQQLPEN-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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Abstract
The non-volatile semi-conductor storage includes the first electric type semi-conductor substrate with the storage area, the second electric type deep well of the semi-conductor substrate being set up at the said storage area and the first electric type shallow ell being setup at the said deep well and separated by a shallow trough insulation layer. Multiple NAND cellblocks are setup at the semi-conductor substrate within the shallow well. Above the substrate of the semi-conductor substrate, there is the bit wire extended to the plug in the shallow well, providing the first prearranged voltage for the shallow well at the programming mode and the second prearranged voltage for the shallow well at the erasion mode.
Description
Technical field
The invention provides a kind of non-volatile semiconductor memory (non-volatile semiconductormemory), but especially relate to the NAND type non-volatile semiconductor memory of a kind of stochastic programming (random programming).
Background technology
Because quickflashing (flash) electro-erasable programmable read-only memory (electrically erasableprogrammable read-only memory, EEPROM) have advantages such as high density, aspect repeated electronically written now non-volatile (or claiming permanent) data storing purposes, have quite widely and use.The main manufacture craft framework of flash memory can be divided into two kinds on NOR type and NAND type, and the product program of being respectively is converted to main stored routine flash memory (code flash), and data access is main storage data flash memory (data flash).The former is used for mobile phone because program conversion, read fast more, and is higher as for latter Ze Yin density, so be that the storage card of products such as digital camera, information household electrical appliances is used.Wherein, NAND type flash memory increases day by day owing to demand, so the potentiality of its development are unlimited.With regard to present quickflashing EEPROM, can be divided into several different forms again, one of them is utilizes two-way (bi-directional) Fule nuohan tunnelling mechanism (Fowler-Nordheim tunnelingmechanism, the EEPROM that FN) operates.
See also Fig. 1, Fig. 1 is the generalized section of existing NAND type EEPROM 10.As shown in Figure 1, NAND type EEPROM 10 includes semiconductor substrate 12, has a memory areas; Semiconductor well (semiconductor well) 14 is located at at the semiconductor-based end 12 in this memory areas; A plurality of NAND storage string block (NAND cell block) B are located on the semiconductor wells 14 at the semiconductor-based end 12; And bit line (bit line) BL1, be located at top, the semiconductor-based ends 12.And, NAND storage string block B includes a plurality of memory cell that repeat to write (memory cell) M, and it is along the direction of bit line BL1, be connected with the series connection form to each other, simultaneously, at the shared doped region under it of the adjacent memory M below the same bit line BL1 to form NAND type memory cell as source electrode (source) and drain electrode (drain).For example, memory cell M114 with doped region 16 as source electrode, and with doped region 18 as drain electrode, yet doped region 18 also is the source electrode of memory cell M115 simultaneously.In addition, memory cell M has the grid of piling up (stacked gate) structure, and for example, the upper strata of memory cell M114 is a control gate (control gate) 20, lower floor is the floating grid (floating gate) 22 of store charge, separates with a dielectric film (insulator film) 24 therebetween.And an end of this series connected memory cell is electrically connected on bit line BL1 by a connector 26, and one select transistor (selecting transistor) ST to be located at the other end of this series connected memory cell, and is electrically connected with one source pole line (source line) SL.Simultaneously, the control gate of memory cell M is electrically connected on a word line perpendicular to bit line BL1 (word line) (not shown).So, then promptly be defined as NAND storage string block by all series connected memory cells that same word line drove.
For existing NAND type EEPROM 10, when carrying out a programming mode, must apply a high voltage (as 20V) can drive memory to selected word line running.Simultaneously, for non-selected word line, also need the no small voltage (as 12V) could be with passage (channel) conducting.So then very power consumption, and because every word line all must apply voltage, it is slow also can to seem on speed.In addition, because high-tension existence also problem might take place aspect reliability, for example, knot collapse situations such as (junction breakdown) takes place.
Summary of the invention
Therefore but main purpose of the present invention is to provide the non-volatile semiconductor memory (non-volatile semiconductor memory) of a kind of stochastic programming (random programming), to solve the problem that above-mentioned prior art exists.
In most preferred embodiment of the present invention, a kind of non-volatile semiconductor memory that carries out stochastic programming (random programming) includes: one first conductive-type semiconductor substrate has a memory areas; One second conductivity type deep ion well was located in this semiconductor-based end in this memory areas; One first conductivity type shallow ion well (shallow well) is located in this deep ion well, and is isolated by a shallow trench isolation layer (STI layer); At least one NAND storage string block (NAND cell block) was located on this semiconductor-based end in this shallow ion well; An and bit line, be located at this top, semiconductor-based end, be used for the connector (plug) that extends to this shallow ion well by one, this shallow ion well one first predetermined voltage be provided under a programming mode, and this shallow ion well one second predetermined voltage is provided under an erasing mode.
Because non-volatile semiconductor memory of the present invention is to form a shallow ion well in the deep ion well again, and connector extended in this shallow ion well and as community electrode (common electrode), therefore can avoid in the existing method every word line all must apply the needs of voltage.That is to say, according to structure of the present invention, when this non-volatile semiconductor memory carries out a programming mode, only needing that selected word line is applied a suitably big or small voltage gets final product, thus, then can save electric power significantly, and shorten the access time (access time), and then improve the usefulness of memory.
Description of drawings
Fig. 1 is the generalized section of existing NAND type EEPROM.
Fig. 2 is the equivalent circuit diagram of NAND type non-volatile semiconductor memory of the present invention.
Fig. 3 is the layout of NAND type non-volatile semiconductor memory of the present invention.
Fig. 4 be among Fig. 3 NAND type non-volatile semiconductor memory along the cutaway view of bit line.
Fig. 5 is another embodiment of NAND type non-volatile semiconductor memory of the present invention.
Fig. 6 is for having the operating condition of the non-volatile semiconductor memory of stacked gate architectures among the present invention.
Fig. 7 is for having the operating condition of the non-volatile semiconductor memory of SONOS memory cell among the present invention.
The reference numeral explanation
10 NAND type EEPROM
12,32 semiconductor wells of the semiconductor-based ends 14
16,18 doped regions, 20,46 control gates
22,48 floating grids, 24 dielectric films
26,40,52 connectors
30,50 non-volatile semiconductor memories
34 deep ion wells, 36 shallow ion wells
38 shallow trench isolation layer
42,44,54 heavily doped regions
B NAND storage string block
M memory cell SL source electrode line
SL ' plain conductor ST selects transistor
Embodiment
See also Fig. 2, Fig. 2 is the equivalent circuit diagram of NAND type non-volatile semiconductor memory 30 of the present invention.As shown in Figure 2, NAND storage string block B includes a plurality of memory cell that repeat to write (memory cell) M, and it is connected with the series connection form to each other along the direction of bit line (bit line) BL1.And an end of this series connected memory cell is electrically connected on bit line BL1, and one selects transistor (selecting transistor) ST then to be located at the other end of this series connected memory cell, and is electrically connected with one source pole line (sourceline) SL.
See also Fig. 3 and Fig. 4, Fig. 3 is the layout of NAND type non-volatile semiconductor memory 30 of the present invention.Fig. 4 is NAND type non-volatile semiconductor memory 30 cutaway views along bit line BL1 among Fig. 3.As shown in Figures 3 and 4, NAND type non-volatile semiconductor memory 30 includes one first conductive-type semiconductor substrate 32, and it has a memory areas; One second conductivity type deep ion well 34 was located in this semiconductor-based end 32 in this memory areas; One first conductivity type shallow ion well (shallowwell) 36 is located in this deep ion well, and by 38 isolation of a shallow trench isolation layer (STI layer); A plurality of NAND storage string block (NAND cell block) B were located on this semiconductor-based end 32 in this shallow ion well 36; An and bit line BL, be located at this top, semiconductor-based ends 32, be used for the connector (plug) 40 that extends to this shallow ion well 36 by one, under a programming mode, provide this shallow ion well 36 one the first predetermined voltages, and under an erasing mode, provide this shallow ion well 36 one the second predetermined voltages.
According to a preferred embodiment of the invention, the semiconductor-based end 32 is a P type semiconductor substrate, and deep ion well 34 is a N type conductivity type, is the P-type conduction type as for 36 in shallow ion well.Certainly, the present invention is applicable to that also with N type conductivity type be the situation at the semiconductor-based end 32, and at this moment, deep ion well 34 is the P-type conduction type, and shallow ion well 36 then is a N type conductivity type.And shallow ion well 36 has the thickness of a well depth (well depth) less than shallow trench isolation layer 38, and in present embodiment, the thickness of shallow trench isolation layer 38 is about 3000 to 4000 .Simultaneously, the dopant dose of deep ion well 34 is about 1 * 10
12To 1 * 10
13Atoms/m
2, the dopant dose of shallow ion well then is 1 * 10
13To 1 * 10
14Atoms/m
2About.
In addition, NAND storage string block B includes a plurality of memory cell M that repeat to write, and it is along the direction of bit line BL, be connected with the series connection form to each other, simultaneously, at the shared doped region under it of the adjacent memory M below the same bit line BL to form NAND type memory cell as source electrode (source) and drain electrode (drain).For example, memory cell M114 with doped region 42 as source electrode, and with doped region 44 as drain electrode, yet doped region 44 also is the source electrode of memory cell M115 simultaneously.And, according to a preferred embodiment of the invention, memory cell M has the grid of piling up (stacked gate) structure, for example, the upper strata of memory cell M114 is the control gate (control gate) 46 that forms with polysilicon (polysilicon), and lower floor is the floating grid (floating gate) 48 of store charge, separates with a dielectric film (insulator film) 50 therebetween, this dielectric film 50 can be an oxygen nitrogen oxygen film (oxide-nitride-oxide, ONO).Certainly, grid structure of the present invention also can be the grid structure of a SONOS, that is, on shallow ion well 36, directly deposit an ONO layer, then deposit one deck polysilicon layer again as control gate 46.Simultaneously, each control gate perpendicular to the memory cell M of bit line BL is electrically connected on corresponding word line (word line) WL respectively.So, then promptly be defined as NAND storage string block by all series connected memory cells that same word line drove.
And, one end of this series connected memory cell is electrically connected on bit line BL by a connector 40, for this connector 40 is extended in the shallow ion well 36, need after contact hole (contact hole) is etched to shallow ion well 36 surfaces, etching runs through the memory cell drain doping region to shallow ion well 36 vertically down again.In addition, as shown in Figure 5, the form of source electrode line SL represented embedded (buried) heavily doped region SL1, also can be connected with heavily doped region 54 via connector 52 by a plain conductor (metal wiring) SL1 ' in non-volatile semiconductor memory 30.
Fig. 6 is for having the operating condition of the non-volatile semiconductor memory of stacked gate architectures among the present invention.As shown in Figure 6 and with non-volatile semiconductor memory 30 is example, and when non-volatile semiconductor memory 30 carried out a programming mode, the voltage that need apply 5V was on bit line BL.Because bit line BL is electrically connected with shallow ion well 36 by the connector 40 that extends to shallow ion well 36, so bit line BL also will provide the voltage of shallow ion well 5V, and visual this shallow ion well 36 is community electrode (common electrode).So, then when a selected memory cell M programmes, only need on selected word line WL, to apply a suitably big or small voltage, and needn't apply voltage to all word line WL, (Fowler-Nordheim tunneling mechanism FN) makes electronics write just can to utilize Fule nuohan tunnelling mechanism.In most preferred embodiment of the present invention, this voltage that puts on selected word line WL is about-10V, and source electrode line SL selects the grid voltage of transistor ST to be all 0V for floating (floating).
When non-volatile semiconductor memory 30 carries out an erasing mode, then need apply in addition ,-voltage of 10V is on source electrode line SL.Because erasing mode is that all memory cell M are wiped in the lump, so all word line WL apply the voltage of 10V.Similarly, the bit line BL of this moment is float (floating), selects transistor ST to be all 0V, also is to utilize FN tunnelling mechanism to wipe.Anticipate promptly, the running of this non-volatile semiconductor memory 30 is to utilize two-way FN tunnelling mechanism to carry out.
And, when non-volatile semiconductor memory 30 carries out a read mode, then apply 0V voltage on bit line BL, and the grid of selected selection transistor ST is applied the voltage of 5V, then remain 0V as for the grid of the selection transistor STx of choosing not.Simultaneously, the word line WLx of not choosing is also applied the voltage of 5V, and selected word line WL is made as 0V reading, and apply 1 to 5V voltage in source electrode line SL.
As previously mentioned, except stacked gate architectures, non-volatile semiconductor memory of the present invention also can utilize the SONOS memory cell to constitute.As for this have the SONOS memory cell non-volatile semiconductor memory operating condition then as shown in Figure 7.By finding out among Fig. 7, in programming and erasing mode, utilize the required voltage of non-volatile semiconductor memory of SONOS memory cell can have stacked gate architectures person for low.That is to say, the non-volatile semiconductor memory that this utilizes the SONOS memory cell to constitute, not only manufacture craft is comparatively simple, also more power saving simultaneously.
Than existing non-volatile semiconductor memory, the present invention forms a shallow ion well again in the deep ion well, and the connector that will be connected in bit line extends in this shallow ion well and as community electrode, and is like this then can avoid in the method that has now every word line all must apply the needs of voltage.And,, also can exempt high driving voltage needed in the art by the disclosed non-volatile semiconductor memory structure of the present invention.In other words, according to structure of the present invention, when this non-volatile semiconductor memory carries out a programming mode, only needing that selected word line is applied a suitably big or small voltage gets final product, thus, then can save electric power significantly, and shorten the access time (access time), and then promote the usefulness of memory.
The above only is the preferred embodiments of the present invention, and all equivalences of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (16)
1. a non-volatile semiconductor memory can carry out stochastic programming (random programming), and this non-volatile semiconductor memory comprises:
One first conductive-type semiconductor substrate has a memory areas;
One second conductivity type deep ion well was located in this semiconductor-based end in this memory areas;
One first conductivity type shallow ion well (shallow well) is located in this deep ion well, and is isolated by a shallow trench isolation layer (STI layer);
At least one NAND storage string block (NAND cell block) was located on this semiconductor-based end in this shallow ion well; And
One bit line is located at this top, semiconductor-based end, is used for the connector (plug) that extends to this shallow ion well by one, this shallow ion well one first predetermined voltage is provided under a programming mode, and this shallow ion well one second predetermined voltage is provided under an erasing mode.
2. non-volatile semiconductor memory as claimed in claim 1, wherein this shallow ion well has the thickness of a well depth (well depth) less than this shallow trench isolation layer.
3. non-volatile semiconductor memory as claimed in claim 1, wherein this first conductivity type is the P type, this second conductivity type is the N type.
4. non-volatile semiconductor memory as claimed in claim 1, wherein this NAND storage string block comprises and a plurality ofly repeats to write (rewritable) series connected memory cell (memory cells) and and select transistor (selecting transistor) to be located at an end of this series connected memory cell, and should insert the other end that base is located at this series connected memory cell.
5. non-volatile semiconductor memory as claimed in claim 4 wherein should select transistor AND gate one source pole line (source line) to be electrically connected.
6. non-volatile semiconductor memory as claimed in claim 4, wherein this memory cell comprises and piles up grid structure.
7. non-volatile semiconductor memory as claimed in claim 4, wherein this memory cell is a SONOS memory cell.
An Erasable Programmable Read Only Memory EPROM (electrically erasable programmable read-only memory EEPROM) includes:
The semiconductor substrate has a memory areas;
One shallow ion well is located in this memory areas, and is isolated by a shallow trench isolation layer;
One deep ion well is located at this shallow ion downhole in this memory areas;
A plurality of NAND storage string blocks (NAND cell block) were located on this semiconductor-based end in this shallow ion well; And
At least one bit line is located at this top, semiconductor-based end, and this bit line is electrically connected with this shallow ion well by a connector (plug) that extends to this shallow ion well.
9. Erasable Programmable Read Only Memory EPROM as claimed in claim 8, wherein respectively this shallow ion well has the thickness of a well depth (well depth) less than this shallow trench isolation layer.
10. Erasable Programmable Read Only Memory EPROM as claimed in claim 8, wherein this bit line provides this shallow ion well one first predetermined voltage under a programming mode, and this shallow ion well one second predetermined voltage is provided under an erasing mode.
11. Erasable Programmable Read Only Memory EPROM as claimed in claim 10, wherein this programming mode utilizes a Fule nuohan tunnelling mechanism (Fowler-Nordheim tunneling mechanism) to carry out.
12. Erasable Programmable Read Only Memory EPROM as claimed in claim 10, wherein this first predetermined voltage is 5 volts, and this second predetermined voltage is-10 volts.
13. Erasable Programmable Read Only Memory EPROM as claimed in claim 8, wherein respectively this NAND storage string block comprises and a plurality ofly repeats to write (rewritable) series connected memory cell (memory cells) and and select transistor (selecting transistor) to be located at an end of this series connected memory cell.
14. Erasable Programmable Read Only Memory EPROM as claimed in claim 13 wherein should select transistor AND gate source electrode line (source line) to be electrically connected.
15. Erasable Programmable Read Only Memory EPROM as claimed in claim 13, wherein this memory cell comprises and piles up grid structure.
16. Erasable Programmable Read Only Memory EPROM as claimed in claim 13, wherein this memory cell is a SONOS memory cell.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02100986 CN1215561C (en) | 2002-01-11 | 2002-01-11 | Random programmable non-volatile semi-conductor storage |
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|---|---|---|---|
| CN 02100986 CN1215561C (en) | 2002-01-11 | 2002-01-11 | Random programmable non-volatile semi-conductor storage |
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| CN1431712A true CN1431712A (en) | 2003-07-23 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100370599C (en) * | 2004-12-28 | 2008-02-20 | 旺宏电子股份有限公司 | Method for operating memory element array,Non-volatile memory device and method producing the same |
| CN100382320C (en) * | 2003-11-24 | 2008-04-16 | 夏普株式会社 | 3d rram |
| CN100423230C (en) * | 2004-12-28 | 2008-10-01 | 旺宏电子股份有限公司 | Method for operating a memory element,Non-volatile memory device and method producing the same |
| CN101361136B (en) * | 2005-12-20 | 2011-07-06 | 美光科技公司 | Nand architecture memory devices and operation |
| CN101395673B (en) * | 2006-03-03 | 2011-09-21 | 桑迪士克股份有限公司 | Read operation for non-volatile storage with compensation for floating gate coupling |
-
2002
- 2002-01-11 CN CN 02100986 patent/CN1215561C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100382320C (en) * | 2003-11-24 | 2008-04-16 | 夏普株式会社 | 3d rram |
| CN100370599C (en) * | 2004-12-28 | 2008-02-20 | 旺宏电子股份有限公司 | Method for operating memory element array,Non-volatile memory device and method producing the same |
| CN100423230C (en) * | 2004-12-28 | 2008-10-01 | 旺宏电子股份有限公司 | Method for operating a memory element,Non-volatile memory device and method producing the same |
| CN101361136B (en) * | 2005-12-20 | 2011-07-06 | 美光科技公司 | Nand architecture memory devices and operation |
| CN101395673B (en) * | 2006-03-03 | 2011-09-21 | 桑迪士克股份有限公司 | Read operation for non-volatile storage with compensation for floating gate coupling |
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| CN1215561C (en) | 2005-08-17 |
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