CN1423321A - Embedded source/drain electrode zone memory assembly manufacture method - Google Patents
Embedded source/drain electrode zone memory assembly manufacture method Download PDFInfo
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- CN1423321A CN1423321A CN01139869.8A CN01139869A CN1423321A CN 1423321 A CN1423321 A CN 1423321A CN 01139869 A CN01139869 A CN 01139869A CN 1423321 A CN1423321 A CN 1423321A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims description 56
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 238000005516 engineering process Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 94
- 239000011247 coating layer Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- -1 phosphorous ion Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The manufacturing method includes following steps. The dielectric layer is formed on the substrate. Next, the character line is formed on the substrate. Then the flush typed source/drain electrode area is formed on the substrate, and the barrier layer is formed on the surface of the character line exposed. With being formed on the substrate, the metal layer is redefined making the leaving metals layer cover the flush typed source/drain electrode area on the side of the character line and step over the character line.
Description
Technical field
The invention relates to a kind of manufacturing method of semiconductor module, and particularly relevant for a kind of manufacture method with memory assembly of embedded source/drain electrode zone (Buried Source/Drain).
Background technology
Known flush type diffusion zone, just source/drain region or flush type lead (Buried Line), often form with the arsenic ion (Arsenic Ion) of high concentration or phosphorous ion (Phosphorous Ion) doping, its sheet resistor (Sheet Resistance) is usually greater than 50ohm/cm
2Because the flush type diffusion zone has so high sheet resistor, so the speed of assembly is difficult for improving.For instance, (its high resistance will make the service speed of memory reduce for Nitride Read Only Memory, the NROM) embedded type bit line in for mask-type ROM (Mask ROM) or silicon nitride ROM.
Summary of the invention
Purpose of the present invention just is to provide a kind of manufacture method with memory assembly of embedded source/drain electrode zone, so that the sheet resistor of source/drain electrode reduces.
Another purpose of the present invention just provides a kind of manufacture method with memory assembly of embedded source/drain electrode zone, along with the sheet resistor of reduction source/drain electrode, can increase the maximum line width (The Maximum Line Width) of character line (WordLine).
Another object of the present invention just provides a kind of manufacture method with memory assembly of embedded source/drain electrode zone, to promote the operation rate (Operation Speed) of memory assembly.
According to above-mentioned and other purpose, the present invention proposes a kind of manufacture method with memory assembly of embedded source/drain electrode zone, this method is to form a dielectric layer in substrate, forms a character line again in substrate, forms an embedded source/drain electrode zone then in substrate.Then form a barrier layer (Barrier Layer), in substrate, form a metal level subsequently, define metal level again, make the metal level that stays cover the embedded source/drain electrode zone of character line both sides and stride across character line in exposed character line surface.Because metal level is in parallel with the source/drain electrode of flush type, makes the sheet resistor of bit line be able to a large amount of reductions, improve the service speed of memory.
The present invention proposes the manufacture method of a kind of mask-type ROM (Mask ROM) assembly again, comprise a substrate is provided, in substrate, form a dielectric layer then, in substrate, form several embedded type bit line again, and form several character lines in substrate, and character line interlocks with embedded type bit line.Then form a barrier layer, in substrate, form a metal level in exposed character line surface.Define metal level subsequently, make the metal level that stays cover the embedded type bit line of character line both sides and stride across these character lines, carry out a coding technology again, in substrate, to form several code areas.
The present invention proposes a kind of silicon nitride ROM (Nitride Read OnlyMemory again, abbreviation NROM) manufacture method, comprise a substrate is provided, in this substrate, form several embedded type bit line then, form one again and catch layer in substrate, catching layer for example is silica-silicon-nitride and silicon oxide structure (Oxide-Nitride-Oxide Structure, ONO structure), and in catching upward several character line of formation of layer, these character lines and embedded type bit line are staggered.Then form a barrier layer, in substrate, form a metal level again in exposed character line surface.Define metal level afterwards, make the metal level that stays cover the embedded type bit line of these character line both sides and stride across these character lines.
In preferred embodiment of the present invention, be that the manufacture method with mask-type ROM (Mask ROM) assembly with embedded type bit line is an example.This method is included in and forms a gate insulator (Gate Insulator) in the substrate, forms the grid structure as character line again in substrate.Then, form a barrier layer, in substrate, form inner layer dielectric layer again in exposed grid structure surface.Then, carry out little shadow and implant technology,, remove inner layer dielectric layer again in substrate, to form an embedded type bit line.Then, in this substrate, form a metal level, define this metal level again, make this metal level that stays cover this flush type source electrode/drain region of these character line both sides and stride across this character line.
As mentioned above, the invention has the advantages that to form one deck metal level in parallel, so that the sheet resistor of this conductive structure reduces several times with the flush type diffusion zone.And along with the low sheet resistor of bit line, the operation rate that can increase the maximum line width of character line and promote assembly.
Description of drawings
Figure 1 shows that a kind of assembly layout schematic diagram of a preferred embodiment of the present invention with mask-type ROM of embedded type bit line;
Fig. 2 A～Figure 10 A and Fig. 2 B～Figure 10 B are depicted as in the preferred embodiment of the present invention, have the manufacturing process profile of the hood curtain type read only storage assembly parts of embedded type bit line, wherein
After Fig. 2 A left side and Fig. 2 B left side were depicted as just step process, along the generalized section in the memory module district 20 of the I-I section gained of Fig. 1, Fig. 2 A and Fig. 2 B right-hand part then showed the situation in the perimeter component district 22;
Be respectively after the deposit barrier layers shown in Fig. 3 A and Fig. 3 B, along the generalized section of I-I section and the II-II section gained of Fig. 1;
Be respectively shown in Fig. 4 A and Fig. 4 B that (Inter-LayerDielectrics 1 through first inner layer dielectric layer, abbreviation ILD1) deposition is removed step with part, deposit second inner layer dielectric layer (ILD2) more afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1;
The little shadow (Photo) that is respectively bit line shown in Fig. 5 A and Fig. 5 B with implant technology (Implantation) afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1;
Be respectively first and second inner layer dielectric layer of etching (terminating on the barrier layer) shown in Fig. 6 A and Fig. 6 B afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1;
Be respectively after the etch barrier shown in Fig. 7 A and Fig. 7 B, along the generalized section of I-I section and the II-II section gained of Fig. 1;
The deposition and the part that are respectively metal level shown in Fig. 8 A and Fig. 8 B are removed after the step, along the generalized section of I-I section and the II-II section gained of Fig. 1;
Be respectively shown in Fig. 9 A and Fig. 9 B after the read-only memory coding technology, along the generalized section of I-I section and the II-II section gained of Fig. 1;
Be respectively deposition the 3rd inner layer dielectric layer (ILD3) shown in Figure 10 A and Figure 10 B afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1.
10,200: substrate
20: the memory module district
22: the perimeter component district
100: character line
102,226: embedded type bit line
104,228: metal level
202: gate insulator
204: grid structure
206: conductor layer
208: the multi-crystal silicification metal level
210: cap layer
212: clearance wall
214: source/drain region
216,216a, 216b: barrier layer
218,220,220a, 232: inner layer dielectric layer
222,222a: reflection coating layer
224: the patterning photoresist layer
230: the read-only memory code area
Embodiment
Figure 1 shows that a kind of hood curtain type read only storage assembly parts schematic layout pattern of a preferred embodiment of the present invention with embedded type bit line.
Please refer to Fig. 1, the structure of memory assembly of the present invention comprises the character line 100 that is arranged in the substrate 10, is positioned at substrate 10 and the embedded type bit line 102 vertical with character line 100 directions, and on embedded type bit line 102 and stride across character line 100 and the metal level 104 in parallel with embedded type bit line 102, its material is preferably tungsten (Tungsten).For describing the manufacture method with memory assembly of embedded type bit line of the present invention in detail, please refer to shown in follow-up each figure.
After Fig. 2 A left side and Fig. 2 B left side were depicted as just step process, along the generalized section in the memory module district 20 of the I-I section gained of Fig. 1, Fig. 2 A and Fig. 2 B right-hand part then showed the situation in the perimeter component district 22.
Please refer to Fig. 2 A and Fig. 2 B, existing one dielectric layer 202 is as gate insulator (Gate Insulator) in a substrate 200, form a grid structure 204 then in substrate 200, this grid structure 204 is as character line (Word Line) in memory module district 20.The technology of grid structure 204 for example is that its material for example is polysilicon (Poly-Si) prior to formation one conductor layer 206 in the substrate 200, forms one deck cap layer (Cap) 210 again on conductor layer 206, for example is silicon nitride (SiN); In addition, better grid structure 204 technologies for example are to form one deck multi-crystal silicification metal (Polycide) layer 208 between the conductor layer 206 of polysilicon material and cap layer 210.Afterwards, definition cap layer 210 and conductor layer 206 are to form grid structure 204.
Then, please refer to Fig. 2 B, 20 form clearance wall 212, formation source/drain region 214 in the substrate 200 in perimeter component district 22 again with grid structure 204 sidewalls in perimeter component district 22 in the memory module district.
Be respectively after the deposit barrier layers shown in Fig. 3 A and Fig. 3 B, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 3 A and Fig. 3 B, in substrate 200, form one deck barrier layer (BarrierLayer) 216 and overlies gate structure 204.Wherein, the formation method of barrier layer 216 can for example be a silicon nitride prior to forming a resistance barrier material layer in the substrate 200 also, to cover substrate 200 surfaces and exposed surface as the grid structure 204 of character line; Then, carry out etch-back (Etch Back) technology, form a resistance barrier clearance wall 216b (asking for an interview shown in follow-up Fig. 7 B) with sidewall at character line.
Be respectively shown in Fig. 4 A and Fig. 4 B that (Inter-LayerDielectrics 1 through first inner layer dielectric layer, abbreviation ILD1) deposition is removed step with part, deposit second inner layer dielectric layer (ILD2) more afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 4 A and Fig. 4 B, form first inner layer dielectric layer (ILD1) 218 in substrate 200, this first inner layer dielectric layer (ILD1) can be silica.Remove first inner layer dielectric layer 218 of part then, till barrier layer 216 exposed, method can barrier layer 216 be to grind suspension layer, and first inner layer dielectric layer 218 is carried out chemical mechanical milling tech (CMP).Then, form second inner layer dielectric layer 220 in substrate 200, its material also for example is a silica, and second inner layer dielectric layer (ILD2) 220 covers first inner layer dielectric layer 218 and barrier layer 216.
Be respectively shown in Fig. 5 A and Fig. 5 B through little shadow (Photo) of bit line with implant technology (Implantation) afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 5 A and Fig. 5 B, on second inner layer dielectric layer 220, form one deck reflection coating layer (Anti-Reflection Coating, be called for short ARC) 222, on reflection coating layer 222, form one deck patterning photoresist layer 224 again, to expose part reflection coating layer 222.Then, serve as the cover curtain with patterning photoresist layer 224, in substrate 200, form embedded type bit line 226.
Be respectively the etching first (ILD1) 218 and second inner layer dielectric layer (ILD2) 220 (terminating on the barrier layer) shown in Fig. 6 A and Fig. 6 B afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 6 A and Fig. 6 B, serves as the cover curtain with patterning photoresist layer 224, and first and second inner layer dielectric layer 218 and 220 that exposes is removed in etching, and exposes the barrier layer 216 of part.Afterwards, patterning photoresist layer 224 is removed, and be patterned the second inner layer dielectric layer 220a and the reflection coating layer 222a that photoresist layer 224 covers before staying.
Be respectively after the etch barrier shown in Fig. 7 A and Fig. 7 B, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 7 A and Fig. 7 B, the barrier layer 216 expose is removed in etching, and lasting etching removes the gate insulator 202 that exposes, till exposing embedded type bit line 226.
The deposition and the part that are respectively metal level shown in Fig. 8 A and Fig. 8 B are removed after the step, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 8 A and Fig. 8 B, then remove remaining reflection coating layer 222a, form layer of metal layer 228 again in substrate 200, its material is preferably tungsten.Remove the metal level 228 of part then, till the second inner layer dielectric layer 220a exposed, its method for example was to serve as to grind suspension layer with the second inner layer dielectric layer 220a, and metal level 228 is carried out chemical mechanical milling tech.
Be respectively shown in Fig. 9 A and Fig. 9 B after the read-only memory coding technology, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Fig. 9 A and Fig. 9 B, then carry out a coding technology (Coding Process), to form read-only memory coding (ROM code) district 230 in substrate 200.In addition, coding technology also can be carried out before the step that forms embedded type bit line 226.
Be respectively deposition the 3rd inner layer dielectric layer 232 (ILD3) shown in Figure 10 A and Figure 10 B afterwards, along the generalized section of I-I section and the II-II section gained of Fig. 1.
Please refer to Figure 10 A and Figure 10 B, in substrate 200, form the 3rd inner layer dielectric layer 232.And the last part technology that continues (Back-End Process) should be and is familiar with known to this operator, therefore repeats no more.
So the present invention forms the layer of metal layer and is used in parallel with the flush type diffusion zone that for example is embedded type bit line 226.Can make the sheet resistor (SheetResistance) of bit line reduce several times by the present invention.Along with the low sheet resistor of bit line, can increase the maximum line width (The Maximum Line Width) of character line and the operation rate (Operation Speed) of promoting assembly.
Claims (35)
1. the manufacture method with memory assembly of embedded source/drain electrode zone is characterized in that, this method comprises:
One substrate is provided;
In this substrate, form a dielectric layer;
In this substrate, form a character line;
In this substrate, form an embedded source/drain electrode zone;
Form a barrier layer in this exposed character line surface;
In this substrate, form a metal level; And
Define this metal level, make this metal level that stays cover this embedded source/drain electrode zone of these character line both sides, and stride across this character line.
2. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 1 is characterized in that the material of this metal level comprises tungsten.
3. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 1 is characterized in that, the method that forms this character line comprises:
In this substrate, form a conductor layer;
On this conductor layer, form a cap layer;
Define this cap layer and this conductor layer, to form this character line; And
Form a clearance wall in the cap layer of this patterning and the sidewall of this character line.
4. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 3 is characterized in that the material of this conductor layer comprises polysilicon.
5. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 4 is characterized in that, after forming this step of this conductor layer in this substrate, more is included in and forms a multi-crystal silicification metal level on this conductor layer.
6. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 3 is characterized in that the material of this cap layer comprises silicon nitride.
7. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 1 is characterized in that, the method that forms this barrier layer comprises:
In this substrate, form surface and exposed this character line surface of resistance barrier material layer to cover this substrate; And
Carry out etch-back, form a resistance barrier clearance wall with sidewall at this character line.
8. the manufacture method with memory assembly of embedded source/drain electrode zone as claimed in claim 7 is characterized in that, the material of this resistance barrier material layer comprises silicon nitride.
9. the manufacture method of a hood curtain type read only storage assembly parts is characterized in that, this method comprises:
One substrate is provided;
In this substrate, form a dielectric layer;
In this substrate, form a plurality of embedded type bit line;
Form a plurality of character lines in this substrate, these character lines and those embedded type bit line are staggered;
Form a barrier layer in these exposed character line surfaces;
In this substrate, form a metal level;
Define this metal level, make this metal level that stays cover this embedded type bit line of these character line both sides and stride across these character lines; And
Carry out a coding technology, in this substrate, to form a plurality of code areas.
10. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 9 is characterized in that, this coding technology is to form this flush type source electrode/drain region step to implement before in this substrate.
11. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 9 is characterized in that, this coding technology is to implement after this defines this metal level step.
12. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 9 is characterized in that, the material of this metal level comprises tungsten.
13. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 9 is characterized in that, the method that forms those character lines comprises:
In this substrate, form a conductor layer;
On this conductor layer, form a cap layer;
Define this cap layer and this conductor layer, to form those character lines; And
Form a plurality of clearance walls in the cap layer of this patterning and the sidewall of those character lines.
14. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 13 is characterized in that, the material of this conductor layer comprises polysilicon.
15. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 14 is characterized in that, after forming this step of this conductor layer in this substrate, more is included in and forms a multi-crystal silicification metal level on this conductor layer.
16. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 13 is characterized in that, the material of this cap layer comprises silicon nitride.
17. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 9 is characterized in that, the formation method of this barrier layer comprises:
In this substrate, form surface and exposed those the character line surfaces of resistance barrier material layer to cover this substrate; And
Carry out etch-back and form a plurality of resistance barrier clearance walls with sidewall at those character lines.
18. the manufacture method of hood curtain type read only storage assembly parts as claimed in claim 17 is characterized in that, the material of this resistance barrier material layer comprises silicon nitride.
19. the manufacture method of a silicon nitride ROM is characterized in that, this method comprises:
One substrate is provided;
In this substrate, form a plurality of embedded type bit line;
In this substrate, form one and catch layer;
Catch layer in this and go up a plurality of character lines of formation, those character lines and those embedded type bit line are staggered;
Form a barrier layer in those exposed character line surfaces;
In this substrate, form a metal level; And
Define this metal level, make this metal level that stays cover this embedded type bit line of those character line both sides and stride across those character lines.
20. the manufacture method of silicon nitride ROM as claimed in claim 19 is characterized in that, this seizure layer comprises silica-silicon-nitride and silicon oxide structure.
21. the manufacture method of silicon nitride ROM as claimed in claim 19 is characterized in that, the material of this metal level comprises tungsten.
22. the manufacture method of silicon nitride ROM as claimed in claim 19 is characterized in that, the method that forms those character lines comprises:
In this substrate, form a conductor layer;
On this conductor layer, form a cap layer;
Define this cap layer and this conductor layer, to form those character lines; And
Form a plurality of clearance walls in the cap layer of this patterning and the sidewall of those character lines.
23. the manufacture method of silicon nitride ROM as claimed in claim 22 is characterized in that, the material of this conductor layer comprises polysilicon.
24. the manufacture method of silicon nitride ROM as claimed in claim 23 is characterized in that, after forming this step of this conductor layer in this substrate, more is included in and forms a multi-crystal silicification metal level on this conductor layer.
25. the manufacture method of silicon nitride ROM as claimed in claim 22 is characterized in that, the material of this cap layer comprises silicon nitride.
26. the manufacture method of silicon nitride ROM as claimed in claim 19 is characterized in that, the method that forms this barrier layer comprises:
In this substrate, form surface and exposed those the character line surfaces of resistance barrier material layer to cover this substrate; And
Carry out etch-back and form a plurality of resistance barrier clearance walls with sidewall at those character lines.
27. the manufacture method of silicon nitride ROM as claimed in claim 26 is characterized in that, the material of this resistance barrier material layer comprises silicon nitride.
28. the memory assembly with embedded source/drain electrode zone is characterized in that, this assembly comprises:
One character line is positioned in the substrate;
One embedded source/drain electrode zone is positioned at this substrate, and this embedded source/drain electrode zone is perpendicular to this character line;
One dielectric layer is between this character line and this substrate;
One metal level is covered on this character line, and this metal level is parallel to this embedded source/drain electrode zone, and this metal level and this embedded source/drain electrode electric connection; And
One resistance barrier clearance wall is between this character line sidewall and this metal level.
29. the memory assembly with embedded source/drain electrode zone as claimed in claim 28 is characterized in that the material of this metal level comprises tungsten.
30. the memory assembly with embedded source/drain electrode zone as claimed in claim 28 is characterized in that the material of this character line comprises polysilicon.
31. the memory assembly with embedded source/drain electrode zone as claimed in claim 28 is characterized in that, the material of this resistance barrier clearance wall comprises silicon nitride.
32. the memory assembly with embedded source/drain electrode zone as claimed in claim 28 is characterized in that, the structure of this character line comprises:
One conductor layer;
One cap layer is positioned on this conductor layer; And
One clearance wall is positioned at the sidewall of this cap layer and this conductor layer.
33. the memory assembly with embedded source/drain electrode zone as claimed in claim 32 is characterized in that the material of this conductor layer comprises polysilicon.
34. the memory assembly with embedded source/drain electrode zone as claimed in claim 32 is characterized in that, more comprises a multi-crystal silicification metal level between this conductor layer and this cap layer.
35. the memory assembly with embedded source/drain electrode zone as claimed in claim 32 is characterized in that the material of this cap layer comprises silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN01139869.8A CN1205668C (en) | 2001-12-03 | 2001-12-03 | Embedded source/drain electrode zone memory assembly manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN01139869.8A CN1205668C (en) | 2001-12-03 | 2001-12-03 | Embedded source/drain electrode zone memory assembly manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1423321A true CN1423321A (en) | 2003-06-11 |
| CN1205668C CN1205668C (en) | 2005-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN01139869.8A Expired - Lifetime CN1205668C (en) | 2001-12-03 | 2001-12-03 | Embedded source/drain electrode zone memory assembly manufacture method |
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| Country | Link |
|---|---|
| CN (1) | CN1205668C (en) |
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2001
- 2001-12-03 CN CN01139869.8A patent/CN1205668C/en not_active Expired - Lifetime
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| CN1205668C (en) | 2005-06-08 |
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Granted publication date: 20050608 |