CN1417805A

CN1417805A - Device and method for controlling active terminal resistance in memory system

Info

Publication number: CN1417805A
Application number: CN 02157515
Authority: CN
Inventors: 庆桂显
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2001-10-19
Filing date: 2002-10-19
Publication date: 2003-05-14
Anticipated expiration: 2022-10-19
Also published as: CN100492533C

Abstract

Provided is a control device and method for an active termination resistor, capable of controlling an on/off state of the active termination resistor of a DRAM irrespective of an operation mode of DRAMs mounted in a memory module. A buffer circuit mounted in a memory circuit includes: a signal terminal; a synchronous input buffer having an input coupled to the signal terminal; an asynchronous input buffer having an input coupled to the signal terminal; and a switching circuit which selectively outputs an output of the synchronous input buffer or an output of the asynchronous input buffer according to an operational mode of the memory circuit. Devices and methods for controlling active termination resistors can control on/off of the active termination resistors irrespective of an operational mode of a delay locked loop or a phase locked loop, and thus reduce data bubbles.

Description

The devices and methods therefor that is used for the positive terminal resistance of control store system

Technical field

The present invention relates generally to memory circuit and system, and more particularly, the present invention relates to the actively devices and methods therefor of (active) terminal resistance of control, and described positive terminal resistance is used for improving the characteristics of signals of memory circuit and system.

Background technology

Usually, the bus frequency along with storage system (for example, using the storage system of dynamic RAM (DRAM) device) increases the just decline of signal integrity (integrity) that storage system is interior.So, developed the various omnibus configurations that can reduce distorted signals.For example, people know, thereby the use of the side among receiver in storage system and/or transmitter resistive terminal is to be used to absorb the effective means that reflection also improves signal performance.Such resistive terminal structure is generally two types of promptly passive (passive) terminals and positive a kind of among the terminal.

Fig. 1 shows an example of passive resistive terminal in the storage system.Specified a kind of so-called stub (stub) series connection (series) terminating (terminated) logic (SSTL) standard, therein, the bus of storage system 100 is connected to terminal voltage Vterm by terminal resistance Rterm, and the memory module insertion of installation dynamic RAM has in the slot of predetermined stub resistance R stub.In this case, stub resistance R stub is not installed on the dynamic random access memory chip, and correspondingly, the example here is the passive resistive terminal of a kind of " closing-chip " (" off-chip ").

When being used for Double Data Rate (DDR) storage system, the passive resistive terminal of SSTL standard can guarantee the data rate of about 300 megabyte/seconds (Mbps).Yet the load by increase has the bus of resistive stub all can cause the deterioration of signal integrity above any increase of 300Mbps at data rate.In fact, can not realize 400Mbps or higher data rate usually with the SSTL bus structure.

Fig. 2 shows an example of the storage system with positive resistive terminal, and especially, the bus structure of positive terminal stub.Here, be used for the control store module work each chipset and be installed in dynamic RAM in each module, include a positive terminal resistance Rterm.Actively terminal resistance Rterm is installed on " conducting chip " (" on-chip "), and can be realized by complementary metal oxide semiconductor (CMOS) (CMOS) device.In this storage system, actively bus termination is by realizing by I/O (I/0) port that is installed in the module.

Each of the combination of one or more resistance element Rterm in each dynamic RAM and one or more on/off switch devices is commonly referred to as " actively terminator device (terminator) " here.Can adopt the positive terminator device of any numerical value of different structure.Fig. 3 illustrated at United States Patent (USP) the 4th, 748, an example of the positive terminator device of the terminal of describing in No. 426 with center tap (center-tapped).In this embodiment, according to the startup/closed condition of signal ON/OFF-1 and ON/OFF-2, the effectively actively terminal impedance Rterm of circuit can change between different value (for example, 150 ohm and 75 ohm).

When the dynamic RAM in being installed in memory module can not access (for example, can not read or write), by being connected to bus, its positive terminal resistance Rterm opens this positive terminal resistance Rterm, to improve the integrality of signal.On the contrary, when dynamic RAM access (for example, reading or writing), its positive terminal resistance Rterm closes and disconnects to reduce load from bus.

Yet, respond positive terminal control signal, the positive terminal resistance that unlatching is installed in the dynamic RAM circuit needs the considerable time, and when write/read operation that execution module intersects, this time delay can cause data foam (bubble), thereby worsens the performance of storage system.

The dynamic RAM that comprises a delay locked loop (DLL) or phased lock loop (PLL), by synchronously controlling the On/Off of its positive terminal resistance with an external clock, can overcome this problem, yet, under the situation that DLL or PLL lost efficacy during the power down of the dynamic RAM of corresponding memory module or the standby, can not control the On/Off of positive terminal resistance.

Summary of the invention

Correspondingly, the invention provides the devices and methods therefor that is used for not considering the mode of operation of dynamic RAM and controls the open/close state of the positive terminal resistance that is installed in memory module.

According to an aspect of the present invention, a kind of buffer circuit is installed in the memory circuit, and comprises: Signal Terminal; Synchronous input buffer with input end that is coupled to Signal Terminal; Asynchronous input buffer device with input end that is coupled to Signal Terminal; And on-off circuit, be used for according to the mode of operation of memory circuit selectively exporting the output of synchronous input buffer or the output of asynchronous input buffer device.

In buffer circuit, a terminal resistance of the output opening and closing memory circuit of on-off circuit.The mode of operation signal that on-off circuit response is provided by the memory circuit outside is with the output of selectively exporting synchronous input buffer or the output of asynchronous input buffer device.On-off circuit response is stored in the value in the mode register of memory circuit, with the output of selectively exporting synchronous input buffer or the output of asynchronous input buffer device.

According to another aspect of the present invention, a kind of positive terminating circuit is installed in the memory circuit, and comprises: terminal resistance is used to memory circuit that terminal impedance is provided; And control circuit, be used to receive the positive terminal control signal that the outside provides, and respond positive terminal control signal and selectively switch on and off terminal resistance.This control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, its mode of operation according to memory circuit is selectively exported the output of synchronous input buffer or the output of asynchronous input buffer device.The open/close state of the output control terminal resistance of on-off circuit.

According to a further aspect of the invention, a kind of positive terminating circuit is installed in the memory circuit, and comprises: terminal resistance, and it provides terminal impedance for memory circuit; Mode register, the data of the mode of operation of its storage indication memory circuit; And control circuit, the outside positive terminal control signal that provides and the output of mode register are provided for it.This control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, it selectively exports the output of synchronous input buffer or the output of asynchronous input buffer device according to the output of mode register.The open/close state of the output control terminal resistance of on-off circuit.

According to a further aspect of the invention, a kind of storage system comprises: bus; Be coupled to a plurality of memory circuits on the bus; And being coupled to chipset on the bus, it provides a plurality of positive terminal control signals for memory circuit.Each of these a plurality of memory circuits comprises a terminal resistance and a control circuit.Control circuit receives and to offer the positive terminal control signal of its memory circuit, and responds positive terminal control signal and selectively switch on and off terminal resistance.And control circuit also comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, it selects among the output of the output of synchronous input buffer or asynchronous input buffer device one according to the mode of operation of the memory circuit that comprises synchronous input buffer and asynchronous input buffer device.The open/close state of the output control terminal resistance of on-off circuit.

According to another aspect of the present invention, a kind of storage system comprises: bus; Be coupled to a plurality of memory circuits on the bus; And being coupled to chipset on the bus, it provides a plurality of positive terminal control signals for memory circuit.Each of these a plurality of memory circuits comprises: a terminal resistance; Control circuit; And mode register, the data of the mode of operation of its storage indication memory circuit.This control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, it selects among the output of the output of synchronous input buffer or asynchronous input buffer device one according to the data of mode register.The open/close state of the output control terminal resistance of on-off circuit.

According to another aspect of the present invention, a kind of method of operating that is used for the control store circuit comprises: apply synchronous input buffer and the asynchronous input buffer device of an input signal to memory circuit; And selectively export the output of synchronous input buffer or the output of asynchronous input buffer device according to the mode of operation of memory circuit.

The method of operating that is used for the control store circuit also comprises: according to the output of selected synchronous input buffer or asynchronous input buffer device, the terminal resistance of opening and closing memory circuit.

Control method also comprises: receive the mode of operation signal that is provided by the memory circuit outside, wherein the value of mode of operation signal and control selection output to the output of the output of synchronous input buffer or asynchronous input buffer device.

Control method also comprises: receive the value in the mode register be stored in memory circuit, wherein the control of the value of mode register is to the selection output of the output of the output of synchronous input buffer or asynchronous input buffer device.

According to a further aspect of the invention, a kind of method of open/close state of terminal resistance of control store circuit comprises: synchronous input buffer and the asynchronous input buffer device to memory circuit applies a positive terminal control signal simultaneously; When memory circuit is in the pattern following time of working hard, select the output of synchronous input buffer; And await orders or power down operations pattern following time when memory circuit is in, select the output of asynchronous input buffer device; And among the output according to the output of synchronous input buffer or asynchronous input buffer device selected one and the open/close state of terminal resistance is set.

According to a further aspect of the invention, provide a kind of method of a plurality of terminal resistances that are used for a plurality of memory circuits in the control store system, here, storage system has a plurality of memory modules that are connected on the data bus.Each memory module is used for installing therein at least one among a plurality of memory circuits.This method comprises: synchronous input buffer and the asynchronous input buffer device of while to each memory circuit of each memory module applies a positive terminal control signal; In each memory circuit,, select the output of synchronous input buffer when memory circuit is in the pattern following time of working hard; And await orders or power down operations pattern following time when memory circuit is in, select the output of asynchronous input buffer device; And in each memory circuit, among the output according to the output of synchronous input buffer or asynchronous input buffer device selected one and the open/close state of terminal resistance is set.

According to another aspect again of the present invention, a kind of method of a plurality of terminal resistances that are used for a plurality of memory circuits in the control store system is provided, wherein storage system has at least one first memory module and second memory module that is connected on the data bus, and each memory module is used to install among a plurality of memory circuits at least one to it.This method comprises: respond the read/write instruction of first memory module, to positive terminal control signal of each memory circuit transmission of second memory module; Apply a positive terminal control signal simultaneously in the synchronous input buffer and asynchronous input buffer device of each memory circuit of second memory module; In each memory circuit of second memory module,, select the output of synchronous input buffer when second memory module is in the pattern following time of working hard; And await orders or power down operations pattern following time when second memory module is in, select the output of asynchronous input buffer device; And in each memory circuit of second memory module, among the output according to the output of synchronous input buffer or asynchronous input buffer device selected one and the open/close state of terminal resistance is set.

According to another aspect of the present invention, provide and be installed in the memory circuit so that for memory circuit provides a terminal resistance of terminal impedance, this terminal resistance comprises: a node; Be connected a plurality of first terminal resistances of the corresponding control signal of response between supply voltage and this node; Be connected a plurality of second terminal resistances of the corresponding control signal of response between ground voltage and this node.

In this terminal resistance, respond corresponding control signal, be connected impedance between this node and the supply voltage by being connected a plurality of first terminal resistance adjustment between this node and the supply voltage; Respond corresponding control signal, be connected impedance between this node and the ground voltage by being connected a plurality of second terminal resistance adjustment between this node and the ground voltage.

According to another aspect of the present invention, provide and be installed in the memory circuit so that a terminal resistance of terminal impedance is provided for memory circuit.This terminal resistance comprises: a node; Be connected first between supply voltage and this node and open (UP) resistance; Be connected second opening resistor of response first control signal between supply voltage and this node; Be connected the 3rd opening resistor of response second control signal between supply voltage and this node.

This terminal resistance also comprises: be connected first between ground voltage and the node and close (DOWN) resistance; Be connected second of response the 3rd control signal between ground voltage and this node and close resistance; Be connected the 3rd of response the 4th control signal between ground voltage and this node and close resistance.

This terminal resistance also comprises: first on-off circuit, and it responds start signal, and Switching power voltage is to first opening resistor; The second switch circuit responds first control signal, and Switching power voltage is to second opening resistor; The 3rd on-off circuit responds second control signal, Switching power voltage to the three opening resistors.Since it is so, terminal resistance also comprises: the 4th on-off circuit, and the response shutdown signal is switched first and is closed resistance to ground voltage; The 5th on-off circuit responds the 3rd control signal, switches second and closes resistance to ground voltage; The 6th on-off circuit responds the 4th control signal, switches the 3rd and closes resistance to ground voltage.Described first to the 6th on-off circuit is metal-oxide semiconductor (MOS) (MOS) transistor.

According to another aspect of the present invention, provide a kind of be used for regulating be installed in memory circuit so that the method for impedance of the terminal resistance of terminal impedance is provided for memory circuit, this method comprises:

Respond corresponding signal, measure one impedance among a plurality of first terminal resistances be connected between supply voltage and this node; Use measured impedance, respond corresponding control signal, regulate the quantity that is connected first terminal resistance between supply voltage and this node.This impedance adjustment method also comprises: respond corresponding control signal, measure one impedance among a plurality of second terminal resistances be connected between ground voltage and this node; Use measured impedance, respond corresponding control signal, regulate the quantity that is connected second terminal resistance between ground voltage and this node.

Description of drawings

To the detailed description of the preferred embodiments of the present invention, above-mentioned purpose of the present invention and advantage will become more obvious by with reference to the accompanying drawings, wherein:

Fig. 1 shows a storage system with the series terminated logic of traditional stub (SSTL) structure;

Fig. 2 illustrates the bus-structured storage system with traditional positive terminal stub;

Fig. 3 has illustrated the example of the traditional positive terminator device with a centre tapped terminal;

Fig. 4 shows the bus-structured storage system according to an embodiment of the invention with a positive terminal stub;

Fig. 5 A show be equipped with therein dual inline type module (DiMM) according to first storage system of the present invention;

Fig. 5 B is the table of control model of first storage system of Fig. 5 A;

Fig. 5 C show be equipped with therein memory module DiMM according to second storage system of the present invention;

Fig. 5 D is the table of control model of second storage system of Fig. 5 C;

Fig. 6 has illustrated according to positive terminator device control input buffer of the present invention;

Fig. 7 A and Fig. 7 B are respectively the positive sequential charts of terminal resistance control (ATC) pattern synchronously in read and write operating period;

Fig. 8 is the sequential chart of asynchronous ATC pattern;

Fig. 9 A to Fig. 9 C is the sequential chart of the work of the storage system when module DiMM0 and module DiMM1 all are in aggressive mode;

Figure 10 A to Figure 10 C is in aggressive mode and the sequential chart of the work of the storage system of DiMM1 when being in power down or standby as DiMM0;

Figure 11 shows the bus-structured storage system according to another embodiment of the invention with a positive terminal stub;

Figure 12 A to Figure 12 E is the table according to the control model of the state of each DiMM of the present invention and positive terminator device;

Figure 13 to Figure 17 shows the storage system according to the invention that different DiMM is installed therein;

Figure 18 shows another embodiment of the bus-structured storage system according to the invention with a positive terminal stub;

Figure 19 is the detail circuits figure of the terminal resistance of Figure 13;

Figure 20 shows an example with control signal generation circuit of fuse (fuse); With

Figure 21 illustrates another example with control signal generation circuit of fuse.

Embodiment

Following embodiment and accompanying drawing are provided, comprehensive so that advantages and features of the invention become thoroughly, and fully notion of the present invention is conveyed to those skilled in the art.To describe more fully the present invention with reference to the accompanying drawings, therein, show the preferred embodiments of the present invention.In the accompanying drawings, all the time with identical reference number indication components identical.

Fig. 4 shows the preferred embodiment of the bus-structured storage system according to an embodiment of the invention 400 of having used positive terminal stub therein.Referring to Fig. 4, storage system 400 comprises: chipset 410, data bus 420, second memory module 450 of first memory module 440 of

dynamic RAM

460 and 470 being installed and

dynamic RAM

480 and 490 are installed therein therein.

Memory module

440 and 450 can be installed in the groove (not shown) of storage system 400.

For example, can realize first and

second memory modules

440 and 450 by dual inline type memory module or Single in-line memory module (SIMM).And, though each two dynamic RAM 460 (480) and 470 (490) that are used for

module

440 and 450 have been described in Fig. 4, can also in each of first and

second memory modules

440 and 450, other dynamic RAM be installed.And for the read and write of data, each of giving chipset 410 and dynamic RAM 460,470,480 and 490 is all installed a driver 401 and an input buffer 402.

Chipset 410 comprises a positive terminator device 430, and it is by an ATC_Chip_Set (ATC_CS) unblanking and closing.In addition, in the

dynamic RAM

460 and 470 of module 440 each all comprises by the ATC_0 unblanking and the positive terminator device 431 of closing, and in the

dynamic RAM

480 and 490 of module 450 each all comprises by the ATC_1 unblanking and the positive terminator device 432 of closing.And, chipset 410 comprises an ATC signal generator 411, signal generator 411 as mentioned below produces chipset control signal ATC_CS, the first control signal ATC_0 and the second control signal ATC_1 according to the read/write mode of

memory module

440 and 450.

Usually, when from

dynamic RAM

460 and 470, writing into or during sense data chipset 410 dynamic RAM 460 and data write/read command of 470 outputs in being installed in first memory module 440.In addition, for closing the positive terminator device 431 of

dynamic RAM

460 and 470, chipset 410 is to

dynamic RAM

460 and 470 outputs, the first control signal ATC_0, and be the positive terminator device 432 of opening

dynamic RAM

480 and 490, chipset 410 is to

dynamic RAM

480 and 490 outputs, the second control signal ATC_1.

In other words, the positive terminator device of accepting the memory module of data write or read operation is closed, and does not have the positive terminator device of other memory module that data write into or read to be unlocked therein.And, according to present embodiment, selectively asynchronous or synchronously control positive terminator device according to the mode of operation of each memory module.Here, " mode of operation " speech is meant, for example memory module actively, power down and standby.

" synchronously ATC pattern " is meant: therein when the DLL of dynamic RAM or PLL are in positive state, synchronously open or close the pattern of the positive terminator device of dynamic RAM with the clock signal clk of outside.In other words, under this control model, synchronously open or close the terminal resistance of dynamic RAM with the clock signal clk of outside.

" asynchronous ATC pattern " is meant: therein when the DLL of dynamic RAM or PLL are in disarmed state (being in power down (Pdn) pattern or (Stby) pattern of awaiting orders), open or close the pattern of the terminal resistance of dynamic RAM asynchronously with the clock signal clk of outside.In other words, under this control model, open or close the terminal resistance of dynamic RAM asynchronously with the clock signal clk of outside.

For example, with reference to figure 5A, DiMM0 and DiMM1 represent the first and second dual inline type memory modules respectively.Each module all is equipped with dynamic RAM (arrange (rank) 0 and arrange (rank) 1) as shown, and is connected to chipset 520 by the mode of data bus 520.In addition, each dynamic RAM all comprises the synchronizing circuit that is used for an internal clocking synchronously producing with external clock CLK, for example, and delay locked loop or phased lock loop.Because DLL and PLL circuit are well-known to those skilled in the art, so omitted detailed description here to DLL and PLL operation.

Fig. 5 B is the state of above-mentioned DLL or PLL and the positive table of the control model of terminator device.As shown in Figure 5, when each of memory module DiMM0 and DiMM1 all is in power down or standby, control the positive terminator device of a module asynchronously; And when each of memory module DiMM0 and DiMM1 all is in aggressive mode, the positive terminator device of a module of synchro control.Module is in aggressive mode, standby or power-down mode and depends on the DLL of memory module or the state of PLL.

Similarly, when memory module DiMM0 and DiMM1 all are in positive state, just synchronously control the positive terminator device of two modules.Be in power down or standby and other module when being in aggressive mode when one in the module, just control the positive terminator device of a module asynchronously.In this way, be under the invalid situation of DLL during power down or the standby or PLL, can control the On/Off of positive terminator device in corresponding memory module.Therefore, need before the control of the positive terminator device of beginning, not open DLL or PLL earlier.

The situation of the module DiMM1 that Fig. 5 C has illustrated in storage system when empty, and Fig. 5 D be a DiMM0 or a DiMM1 for empty situation under the state and the positive table of the control model of terminator device of DLL or PLL.

With reference now to Fig. 6,, it shows the functional diagram of controlling (ATC) input buffer synchronously with asynchronous positive terminator device of the present invention.ATC impact damper 601 receives the first control signal ATC_0 (Fig. 4) from chipset 410.And with in parallel (synchronously) input buffer 602 and asynchronous input buffer device 603 that is applied to clock synchronization of the first control signal ATC_0.Multiplexer (MUX) 604 is selected the output of a synchronous input buffer 602 or the output of an asynchronous input buffer device 603 effectively according to being applied to the mode of operation signal on it.

In addition, the mode of operation signal that provides from the operational mode state mechanism of storage system also is used for On/

Off impact damper

602 and 603 effectively.With reference to figure 5B and Fig. 5 D, the ATC input buffer of Fig. 6 is worked as described above, so that selectively come the positive terminator device of control store module with synchronous or asynchronous mode.

Each the ATC control under synchronous mode that is used for read and write operation has been described respectively in the sequential chart of Fig. 7 A and Fig. 7 B.Here, suppose, and at clock edge read data, and dynamic RAM is that 8 Double Data Rate comes work with the burst length in the center of clock write data.

Within the second time cycle tON after the cycle very first time tTACT that the unlatching from the control signal ATC of chipset 410 output begins to count, preferably open the positive terminator device of dynamic RAM.Among the 4th time cycle tOFF after invalid the 3rd time cycle tTPRE that begins to count of control signal ATC, preferably close the positive terminator device of dynamic RAM.Cycle very first time tTACT and the 3rd time cycle tTPRE are set up as not based on the absolute time length of external timing signal CLK.

At first with reference to the read operation of figure 7A, ATC is the " high " state of ATC signal in the rising edge response of CLK2, to open positive terminator device after delay period tTACT.In this case, actively the terminator device is synchronously opened with the negative edge of CLK4 as shown in figure, and after longer time delay tON, actively the terminator device is considered to " opening ".

Then, ATC is the " low " state of ATC signal in the rising edge response of CLK7, to close positive terminator device after delay period tTPRE.And actively the terminator device synchronously cuts out with the negative edge of CLK9 as shown in figure, and after longer time delay tOFF, actively the terminator device is considered to " pass ".In this example, can set up following relational expression:

2.5tCC-500ps＜tTACT, tTPRE＜2.5tCC+500ps are here, tCC is between clock cycles.Equally, time cycle tON and/or time cycle tOFF can be configured to less than 2.5*tCC-500ps.

With reference now to the write operation of Fig. 7 B,, ATC is the " high " state of ATC signal in the rising edge response of CLK2, to open positive terminator device after delay period tTACT.In this case, actively the terminator device is synchronously opened with the rising edge of CLK4 as shown in figure, and after longer time delay tON, actively the terminator device is considered to " opening ".Then, ATC is the " low " state of ATC signal in the rising edge response of CLK7, to close positive terminator device after delay period tTPRE.And actively the terminator device synchronously cuts out with the rising edge of CLK9 as shown in figure, and after longer time delay tOFF, actively the terminator device is considered to " pass ".In this example, can set up following relational expression:

2.0tCC-500ps＜tTACT, tTPRE＜2.0tCC+500ps are here, tCC is between clock cycles.And time cycle tON and/or time cycle tOFF can be configured to less than 0.5*tCC-500ps.

Explanation is in the ATC control in the asynchronous mode in the sequential chart of Fig. 8.Here, the ATC response is the " high " state of ATC signal, with after delay period tTACT, opens positive terminator device.Here, it should be noted that actively the unlatching of terminator device is not synchronized with clock signal, but decide by the amount that postpones tTACT.Such as the aforementioned, after longer time delay tON, actively the terminator device is considered to " opening ".

Then, the ATC response is the " low " state of ATC signal, to close positive terminator device after delay period tTPRE.And actively closing of terminator device is not synchronized with clock signal, but decided by the amount that postpones tTPRE, and after longer time delay t0N, actively the terminator device is considered to " pass ".Here, for example, tTACT and tTPRE can be arranged between 2.5ns and the 5.0ns.And time cycle tON and/or time cycle tOFF can be configured to less than 0.5*tCC-500ps.

Fig. 9 A to 9C is the sequential chart of the work of the storage system when memory module DiMM0 and DiMM1 are in aggressive mode.As shown in Fig. 5 B,, then under synchronous mode, carry out the ATC of each module because two modules all are in aggressive mode.Fig. 9 A has illustrated the duty of chipset, and Fig. 9 B has illustrated the operation of the first memory module DiMM0, and Fig. 9 C has illustrated the operation of the second memory module DiMM1.As directed, chipset sends a series of order, comprises the read command RD to DiMM0, gives the write order WR of DiMM1, and another read command RD that gives DiMM0.

In order to read the first memory module DiMM0, must open the positive terminator device of the second memory module DiMM1.Correspondingly, chipset is exported read command RD to the first memory module DiMM0, and exports the second control signal ATC1 to the second memory module DiMM1.The second memory module DiMM1 responds the second control signal ATC1, so that open the positive terminator device by this module shown in the positive terminator device AT_DiMM1 of Fig. 9 C provisionally.Similarly, open in time of positive terminator device of the second memory module DiMM1 sense data Ri1 from the first memory module DiMM0 therein.

Similarly, in order to write into the second memory module DiMM1 next time, must open the positive terminator device of the first memory module DiMM0.Therefore, write order WR is input to the second memory module DiMM1, and will writes into the first memory module DiMM0 from the first control signal ATC0 of chipset output.The first memory module DiMM0 responds the first control signal ATC0, so that open the positive terminator device by this module shown in the positive terminator device AT_DiMM0 of Fig. 9 B provisionally.Similarly, open therein in time of positive terminator device of the first memory module DiMM0, in the second memory module DiMM1, write into data Di.

Along with the second memory module DiMM1 responds the second control signal ACT1 opening the positive terminator device AT_DiMM1 of Fig. 9 C, to carry out the second reading operation of the first memory module DiMM0 with the same mode of first read operation.

It should be noted equally, in Fig. 9 A, the positive terminator device AT_CS of opening chip group just when memory read operation only.When having the impedance matching of driver, then in write operation, actively terminal is essential frequently.

Figure 10 A to 10C is in aggressive mode and the sequential chart of the operation of the storage system of the second memory module DiMM1 when being in power down or standby as the first memory module DiMM0.In this case, shown in Fig. 5 B, the ATC of the first memory module DiMM0 closes, and the ATC of the second memory module DiMM1 carries out with asynchronous mode.Figure 10 A has illustrated the operation of chipset, and Figure 10 B has illustrated the operation of the first memory module DiMM0, and Figure 10 C has illustrated the operation of the second memory module DiMM1.As directed, chipset sends a series of orders to the first positive memory module DiMM0, comprises read command RD to DiMM0, gives the write order WR of DiMM0 and gives another read command RD of DiMM0.

In order to read the first memory module DiMM0, must open the positive terminator device of the second memory module DiMM1.Responsively, will be input to the first memory module DiMM0 from the first read command RD of chipset output, and will be input to the second memory module DiMM1 from the second control signal ATC1 of chipset output.As directed, the second memory module DiMM1 responds the second control signal ATC1 asynchronously, to open the positive terminator device by this memory module shown in the positive terminator device AT_DiMM1 of Figure 10 C provisionally.Similarly, open in time of positive terminator device of the second memory module DiMM1 sense data Ri1 from the first memory module DiMM0 therein.

Similarly, in order to write into the first memory module DiMM0 next time, must open the positive terminator device of the second memory module DiMM1.Correspondingly, will be input to the first memory module DiMM0 from the write order WR of chipset output, and the second control signal ATC1 will be input to the second memory module DiMM1.The first memory module DiMM0 responds the second control signal ATC1 again asynchronously, to open the positive terminator device by this memory module shown in the positive terminator device AT_DiMM1 of Figure 10 C.At this moment, data Di is write among the first memory module DiMM0.

In the example of Figure 10 A to 10C, second reading order RD follows closely after write order WR.Similarly, it is high that the second control signal ATC1 keeps, and the positive terminator device of the second memory module DiMM1 is in the unlatching attitude in whole second reading operating process.Equally, find out obviously from Figure 10 C that closing of the positive terminator device of the second memory module DiMM1 also is asynchronous.

Now, will begin 11 to describe the second embodiment of the present invention with reference to the accompanying drawings.In this embodiment, being arranged on dynamic random access memory chip on each side of each DiMM module carries out ATC with the combination of public ATC signal and mode register separately and controls.Especially, as shown in Figure 11, storage system 1100 comprises: chipset 1110; Data bus 1120; First memory module 1140 of

dynamic RAM

1160 and 1170 is installed therein; Second memory module 1150 of

dynamic RAM

1180 and 1190 is installed

therein.Memory module

1140 and 1150 can be installed in the draw-in groove (not shown) of storage system 1100.

For example, can realize first and

second memory modules

1140 and 1150 with a dual inline type memory module.And, though each two dynamic RAM 1160 (1180) and 1170 (1190) that are used for

module

1140 and 1150 have been described in Figure 11, can in each of first and

second memory modules

1140 and 1150, other dynamic RAM be installed.Equally, for the write and read of data, each of chipset 1110 and

dynamic RAM

1160,1170,1180 and 1190 has all been installed a driver 1101 and an input buffer 1102.

Compare with first embodiment,

dynamic RAM

1160,1170,1180 and 1190 has also been installed the mode register 1105 of the data that comprise the mode of operation that is used to indicate corresponding dynamic RAM (actively, power down, await orders) extraly.In the following method with reference to figure 12A to Figure 12 E, the operation of the MUX604 of each the ATC control circuit shown in Fig. 6 is being controlled in the output of each register, thereby selects synchronous or asynchronous control model.

Especially, Figure 13 has illustrated " 2r/2r " structure, and in this structure, each of the first and second memory module Dimm0 and DiMM1 all is equipped with two dynamic RAM circuits.In this case, as shown in following Figure 12 A, carry out the positive terminator device control of storage system.Here, arrange 0 (R0) and specify dynamic RAM 1160, arrange 1 (R1) and specify dynamic RAM 1170, arrange 2 (R2) and specify dynamic RAM 1180, and arrange 3 (R3) and specify dynamic RAM 1190.

In Figure 12 A, " close (mark) " means the resistance of closing a terminal uniquely that is provided with by mark, and " closing (ATC or mark) " means the resistance of selectively closing a terminal that is provided with of control signal by the user or mark.

When mode register indicates all arrangements all to be in positive attitude, just operating first and second memory module DiMM0 and the DiMM1 simultaneously under the ATC pattern synchronously.On the other hand, for example, when R3 is in power down/standby, will turn off the ATC of (or mark) R3, and with the remaining arrangement R0 to R2 of synchronous ATC pattern operation.And, when R2 and R3 all are in power down or standby, so, just turn off the ATC of the first memory module DiMM0, and operate arrangement R2 and the R3 of the second memory module DiMM1 with synchronous ATC pattern.

Figure 14 has illustrated " 2r/1r " structure, and in this structure, first memory module DiMM0 is equipped with two dynamic RAM circuits, and second memory module DiMM1 is equipped with a dynamic RAM circuit.In this case, carry out the positive terminator device control of storage system as shown in Figure 12B.Here, arrange 0 and specify dynamic RAM 1160, arrange 1 and specify dynamic RAM 1170, and arrange 2 and specify dynamic RAM 1180.

Figure 15 has illustrated " 1r/1r " structure, and therein, first memory module DiMM0 is equipped with a dynamic RAM circuit, and second memory module Dimm1 is equipped with a dynamic RAM circuit.In this case, as shown in Figure 12 C, carry out the positive terminator device control of storage system.Here, arrange 0 and specify the dynamic RAM 1160 of the first memory module DiMM0, and arrange 1 dynamic RAM 1180 of specifying the second memory module DiMM1.

Figure 16 has illustrated " 2r/ sky " structure, and therein, first memory module DiMM0 is equipped with two dynamic RAM circuits, and second memory module Dimm1 does not install dynamic RAM circuit.In this case, as shown in Figure 12 D, carry out the positive terminator device control of storage system.Here, arrange 0 and specify the dynamic RAM 1160 of the first memory module DiMM0, and arrange 1 dynamic RAM 1170 of specifying the first memory module DiMM0.

Figure 17 has illustrated " 1r/ sky " structure, and therein, first memory module Dimm0 is equipped with a dynamic RAM circuit, and second memory module Dimm1 does not install dynamic RAM circuit.In this case, carry out the positive terminator device control of storage system, to such an extent as to, carry out synchronous ATC as R0 when being positive; And when R0 is power down or standby, close ATC.Arrange 0 dynamic RAM 1160 of specifying the first memory module DiMM0 here.

Now, will 18 the third embodiment of the present invention be described with reference to the accompanying drawings.In the present embodiment, use independent ATC signal from chipset to come dynamic random access memory chip 1860 (1880) and 1870 (1890) on ATC control setting each side individually at each memory module DiMM.Especially, as shown in Figure 18, storage system 1800 comprises: chipset 1810; Data bus 1820; First memory module 1840 of dynamic RAM 1860 and 1870 is installed therein; Second memory module 1850 of

dynamic RAM

1880 and 1890 is installed

therein.Memory module

1840 and 1850 can be installed in the draw-in groove (not shown) of storage system 1800.

For example, can realize first and

second memory modules

1840 and 1850 with a dual inline type memory module.And, though each two dynamic RAM 1860 (1880) and 1870 (1890) that are used for

module

1840 and 1850 have been described in Figure 18, can also in each of first and

second memory modules

1840 and 1850, other dynamic RAM be installed.Equally, for the write and read of data, each of chipset 1810 and

dynamic RAM

1860,1870,1880 and 1890 all is equipped with a driver 1801 and an input buffer 1802.

Compare with first and second embodiment, the ATC signal generator 1811 of present embodiment as shown in Figure 18 provides ATC signal ATC_0_R0 and ATC_0_R1 to the dynamic RAM 1860 and 1870 of first memory module 1840 (DiMM0) individually, and provides ATC signal ATC_0_R2 and AT_C0_R3 to the

dynamic RAM

1880 and 1890 of second memory module 1850 (DiMM1) individually.In the method described in Figure 12 E,, be controlled at the operation of the MUX604 of each the ATC control circuit shown in Fig. 6, thereby select synchronous or asynchronous control model based on each duty of dynamic RAM (or arrange) independently.

Especially, " 2r/2r " structure of Figure 12 E response Figure 13, in this structure, each of the first and second memory module Dimm0 and DiMM1 all is equipped with two dynamic RAM circuits.Here, arrange 0 and specify dynamic RAM 1860, arrange 1 and specify dynamic RAM 1870, arrange 2 and specify dynamic RAM 1880, and arrange 3 and specify dynamic RAM 1890.

Figure 19 is terminal resistance Rterm_UP shown in Figure 13 and the detailed circuit diagram of Rterm_DN.With reference to Figure 19, the first opening resistor Ru ₀Be coupled to supply voltage VDDQ and node ND by PMOS transistor 1910.The second opening resistor Ru ₁Be coupled to supply voltage VDDQ and node VD by PMOS transistor 1930, and the 3rd opening resistor Ru ₂Being coupled to supply voltage VDDQ by PMOS transistor 1950 links to each other and node ND.

Difference responsive control signal UP, SU ₁And SU ₂, open or

close PMOS transistor

1910,1930 and 1950.

Preferably, design a dynamic RAM, make by following first, second and the 3rd opening resistor Ru of being provided with ₀, Ru ₁And Ru ₂Impedance.With the first opening resistor Ru ₀Impedance be provided with greatlyyer slightly than predetermined target value.As the second opening resistor Ru ₁With the first opening resistor Ru ₀When in parallel, its impedance is set to predetermined target value.As the 3rd opening resistor Ru ₂With the first opening resistor Ru ₀With the second opening resistor Ru ₁When in parallel, be provided with its impedance slightly littler than predetermined target value.Correspondingly, first, second and the 3rd opening resistor Ru are depended in the impedance of terminal resistance Rterm_UP ₀, Ru ₁And Ru ₂Combination.

First closes resistance R d ₀Be coupled to node ND and ground voltage VSSQ by nmos pass transistor 1920, second closes resistance R d ₁Be coupled to node ND and ground voltage VSSQ by nmos pass transistor 1940, and the 3rd closes resistance R d ₂Be coupled to ND and ground voltage VSSQ by nmos pass transistor 1960.

Difference responsive control signal DOWN, SD ₁And SD ₂, open or close nmos pass transistor 1920,1940 and 1960.

Preferably, at default conditions, MOS transistor 1930 and 1940 is opened and MOS transistor 1950 and 1950 is closed.Or, at default conditions, MOS transistor 1930 and 1940 can be closed and MOS transistor 1950 and 1950 is opened.

Preferably, design a dynamic RAM, make first, second to be set and the 3rd to close resistance R d by following ₀, Rd ₁And Rd ₂Impedance.Close resistance R d with first ₀Impedance be provided with greatlyyer slightly than predetermined target value.Close resistance R d when second ₁With first close resistance R d ₀When in parallel, its impedance is set to predetermined target value.Close resistance R d when the 3rd ₂With first close resistance R d ₀With second close resistance R d ₁When in parallel, be provided with its impedance slightly littler than predetermined target value.Correspondingly, the impedance of terminal resistance Rterm_DN is depended on first, second and the 3rd is closed resistance R d ₀, Rd ₁And Rd ₂Combination.

Figure 20 illustrates the example of the control signal generation circuit with a fuse.With reference to Figure 20, control signal generation circuit 2000 comprises: 2010,2030 and 2040, fuses of a plurality of transistors 2020, a logic gate 2050.

PMOS transistor 2010 is coupling between supply voltage VDDQ and fuse 2,020 one ends.Add the grid that electric signal VCCHB is imported into PMOS transistor 2010.Nmos pass transistor 2030 is connected between the other end and ground voltage VSSQ of fuse 2020.Add the grid that electric signal VCCHB is imported into nmos pass transistor 2030.As shown in Figure 20, the level that adds electric signal VCCHB increases when predetermined, descends then and keeps low level.

Fuse 2020 is connected between the drain electrode of the drain electrode of PMOS transistor 1020 and nmos pass transistor 2030.Can in all sorts of ways fuse 2020 is cut off, for example, use laser.Can or anti-gush fuse (anti-fuse) and realize fuse 2020 with fuse link (make-link).

Logic gate 2050 receives and adds electric signal VCCHB and from the signal of the drain electrode of nmos pass transistor 2030, carries out one non-(NOR) operation, and export F as a result ₁

Nmos pass transistor 2040 is connected between the drain electrode and ground power supply VSSQ of nmos pass transistor 2030, and has the grid of an output of logic gate of being connected in 2050.

With reference to Figure 20, after fuse 2020 is cut off and applies when adding electric signal VCCHB through one period schedule time, the output signal F of logic gate 2050 ₁Be in logic high.Compare, after fuse is not cut off and carries out when adding electric signal VCCHB through one period schedule time, the output signal F of logic gate 2050 ₁Be in logic low.

Figure 21 shows another example of the control signal generation circuit with a fuse.With reference to Figure 21, control signal generation circuit 2000 ' also comprises the phase inverter 2060 of the output terminal of the control signal generation circuit 2000 that is positioned at Figure 20.When the fuse 2020 of control signal generation circuit 2000 ' is not cut off, the output signal F of phase inverter 2060 ₂Be in logic high.When the fuse 3030 of control signal generation circuit 2000 ' is cut off, the output signal F of phase inverter 2060 ₂Be in logic low.

With reference to Figure 19 and 21, will describe the impedance of adjustment terminal resistance Rterm_UP and Rterm_DN in detail to predetermined target value.When all resistance R u are installed in semi-conductor chip ₀, Ru ₁, Ru ₂, Rd ₀, Rd ₁And Rd ₂The time, under detecting pattern, measure the first opening resistor Ru by using detecting device ₀Impedance and first close resistance R d ₀Impedance.

Here, since the difference in the manufacture process, the first opening resistor Ru ₀The impedance meeting be different from first and close resistance R d ₀Impedance.When PMOS transistor 1910 and nmos pass transistor 1920 do not match, the first opening resistor Ru ₀The impedance meeting be different from first and close resistance R d ₀Impedance.This at the first opening resistor Ru ₀With first close resistance R d ₀Between impedance on difference the integrality of signal is worsened.

When in test pattern, measuring the first opening resistor Ru ₀Impedance the time, nmos pass transistor 1920,1940 and 1960 is just closed.Close resistance R d when in test pattern, measuring first ₀Impedance the time,

PMOS transistor

1910,1930 and 1950 is just closed.

The first opening resistor Ru ₀The measurement impedance compare with the predetermined target value of terminal resistance Rterm_UP, and cut off the fuse 2020 of Figure 20 and Figure 21 rightly.Output signal F ₁And F ₂Logic state whether be cut off by fuse 2020 and decide.

Original state to MOS transistor 1930,1940,1950 and 1960 signals of importing is as described below.MOS transistor 1930 and 1960 each grid receive the output signal F of the control signal generation circuit 2000 of Figure 20 ₁, and each grid of MOS transistor 1940 and 1950 receives the output signal F of the control signal generation circuit 2000 ' of Figure 21 ₂

In the not cut original state of fuse, open MOS transistor 1930 and 1940, and close MOS transistor 1950 and 1960.

As the first opening resistor Ru ₀The measurement impedance greater than the predetermined target value of terminal resistance Rterm_UP, and the fuse 2020 of the control signal generation circuit 2000 ' that is connected with the grid of PMOS transistor 1950 is when being disconnected, control signal Su ₂Be closed (for example, being in logic low).Correspondingly, the 3rd opening resistor Ru ₂Be parallel-connected to the first opening resistor Ru ₀With the second opening resistor Ru ₁, and the impedance of terminal resistance Rterm_UP is reduced to and approaches predetermined target value.

Compare, as the first opening resistor Ru ₀The measurement impedance less than the predetermined target value of terminal resistance Rterm_UP, and the fuse 2020 of the control signal generation circuit 2000 that is connected with the grid of PMOS transistor 1930 is when being disconnected, control signal Su ₁Be unlocked, and the second opening resistor Ru ₁With the first opening resistor Ru ₀Disconnect.Correspondingly, the impedance of terminal resistance Rterm_UP rises to and approaches predetermined target value.

Close resistance R d when first ₀The measurement impedance greater than the predetermined target value of terminal resistance Rterm_DOWN, and the fuse 2020 of the control signal generation circuit 2000 that is connected with the grid of nmos pass transistor 1960 is when being disconnected, control signal Sd ₂Be unlocked.Correspondingly, the 3rd close resistance R d ₂Be parallel-connected to first and close resistance R d ₀With second close resistance R d ₁, and the impedance of terminal resistance Rterm_DN drops to and approaches predetermined target value.

Compare, close resistance R d when first ₀The measurement impedance less than the predetermined target value of terminal resistance Rterm_DOWN, and the fuse 2020 of the control signal generation circuit 2000 ' that is connected with the grid of nmos pass transistor 1940 is when being disconnected, control signal Sd ₁Be closed, and second closes resistance R d ₁With first close resistance R d ₀Disconnect.Correspondingly, the impedance of terminal resistance Rterm_DN rises to and approaches predetermined target value.

With reference to the accompanying drawings 19, though being illustrated as respectively, terminal resistance Rterm_UP and Rterm_DN comprise two resistance R u ₁And Ru ₂, with Rd ₁And Rd ₂, so that regulate its impedance, but present embodiment is to be used for illustration purpose, and is not that intention limits the scope of the invention.And in order accurately to regulate its impedance, each of terminal resistance Rterm_UP and Rterm_DN can comprise a plurality of resistance.

Under detecting pattern, can determine whether cutting off fuse 2020 with predetermined tracing table.

According to the present invention, can produce control signal UP, Su with a mode register set (MRS) ₁, Su ₂, DOWN, Sd ₁And Sd ₂According to the present invention, the impedance of each of terminal resistance Rterm_UP and Rterm_DN can be adjusted to predetermined target value in the chip testing process or after the Chip Packaging.

According to the present invention, can regulate each the impedance of terminal resistance Rterm_UP and Rterm_DN effectively, thereby increase the signal integrity of storage system.

Though described the present invention with reference to preferred embodiment, preferred embodiment only is to be used for descriptive purpose.Owing to, be obvious for the person of ordinary skill of the art, so the scope of claims can not be interpreted as only limiting to these embodiment without departing from the spirit and scope of the present invention to the modification of the foregoing description.

Aforesaid, in the apparatus and method that are used for controlling positive terminal resistance according to the present invention, need not consider the mode of operation of delay locked loop (DLL) or phase locking loop (PLL), get final product the ON/OFF of control terminal resistance, thereby reduced the data foam.

The device that is used to control positive terminal resistance according to the present invention has advantageously increased the data rate with the bus-structured storage system of stub.Can regulate each the impedance of terminal resistance Rterm_UP and Rterm_DN effectively, thereby improve the signal integrity of storage system.

Claims

1. buffer circuit that is installed in the memory circuit comprises:

Signal Terminal;

Synchronous input buffer has an input end that is coupled to described Signal Terminal;

The asynchronous input buffer device has an input end that is coupled to described Signal Terminal; And

On-off circuit, its mode of operation according to memory circuit is selectively exported the output of described synchronous input buffer or the output of described asynchronous input buffer device.

2. circuit as claimed in claim 1, wherein, the output of on-off circuit is opened (enable) and is closed the terminal resistance of (disable) memory circuit.

3. circuit as claimed in claim 2, wherein, the mode of operation signal that on-off circuit response is provided by the memory circuit outside is with the output of selectively exporting described synchronous input buffer or the output of described asynchronous input buffer device.

4. circuit as claimed in claim 1, wherein, on-off circuit response is stored in the value in the mode register of memory circuit, with the output of selectively exporting described synchronous input buffer or the output of described asynchronous input buffer device.

5. positive terminating circuit that is installed in the memory circuit comprises:

Terminal resistance, it provides terminal impedance for memory circuit; And

Control circuit, outside positive terminal control signal that provides is provided for it, and responds positive terminal control signal, selectively switches on and off terminal resistance;

Wherein, described control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, its mode of operation according to memory circuit is selectively exported the output of described synchronous input buffer or the output of described asynchronous input buffer device; And the open/close state of described terminal resistance is controlled in the output of wherein said on-off circuit.

6. circuit as claimed in claim 5, wherein, when memory circuit is in the pattern following time of working hard, on-off circuit is selected the output of synchronous input buffer; And await orders or power down operations pattern following time when memory circuit is in, on-off circuit is selected the output of asynchronous input buffer device.

7. circuit as claimed in claim 5, wherein, memory circuit is the dynamic RAM (DRAM) of single-row direct insertion (single in-line) memory module.

8. circuit as claimed in claim 5, wherein, memory circuit is the dynamic RAM of dual inline type (dual in-line) memory module.

9. positive terminating circuit that is installed in the memory circuit comprises:

Terminal resistance, it provides terminal impedance for memory circuit;

Mode register, its storage are used to indicate the data of the mode of operation of memory circuit; And

The outside positive terminal control signal that provides and the output of mode register are provided control circuit;

Wherein, described control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, the output of described synchronous input buffer or the output of described asynchronous input buffer device are selectively exported in its output according to described mode register; And the open/close state of described terminal resistance is controlled in the output of wherein said on-off circuit.

10. circuit as claimed in claim 9, wherein, when the output of mode register indication memory circuit is under the pattern of working hard constantly, on-off circuit is selected the output of synchronous input buffer; And await orders or power down operations pattern following time when the output of mode register indication memory circuit is in, on-off circuit is selected the output of asynchronous input buffer device.

11. circuit as claimed in claim 9, wherein, memory circuit is the dynamic RAM of Single in-line memory module.

12. circuit as claimed in claim 9, wherein, memory circuit is the dynamic RAM of dual inline type memory module.

13. a storage system comprises:

Bus;

Be coupled to a plurality of memory circuits of described bus;

Be coupled to the chipset of described bus, it provides a plurality of positive terminal control signals for described memory circuit;

Wherein, each of a plurality of memory circuits all comprises terminal resistance and control circuit, and the positive terminal control signal that is provided by its memory circuit is provided wherein said control circuit, and responds positive terminal control signal, selectively switches on and off terminal resistance.

Wherein, described control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, it selects in the output of the output of described synchronous input buffer or described asynchronous input buffer device one according to the mode of operation of the memory circuit that comprises described synchronous input buffer and described asynchronous input buffer device; And the open and closed of described terminal resistance are controlled in the output of wherein said on-off circuit.

14. as the storage system of claim 13, wherein, when memory circuit is in the pattern following time of working hard, on-off circuit is selected the output of synchronous input buffer; And await orders or power down operations pattern following time when memory circuit is in, on-off circuit is just selected the output of asynchronous input buffer device.

15. storage system as claim 13, also comprise: a plurality of memory modules, its each have among a plurality of memory circuits that are installed on it at least one, wherein a plurality of positive terminal control signals are applied to respectively in the memory circuit of a plurality of memory modules, make the memory circuit of each memory module receive identical among a plurality of positive terminal control signals.

16. storage system as claim 14, also comprise: a plurality of memory modules, its each have among a plurality of memory circuits that are installed on it at least one, wherein a plurality of positive terminal control signals are applied to respectively in the memory circuit of a plurality of memory modules, make the memory circuit of each memory module receive different among a plurality of positive terminal control signals.

17. as the storage system of claim 14, wherein, a plurality of memory circuits are mounted in the dynamic RAM circuit in the dual inline type memory module.

18. a storage system comprises:

Bus;

Be coupled to a plurality of memory circuits of described bus;

Wherein, each of a plurality of memory circuits comprises terminal resistance, control circuit and mode register, and the storage of described mode register is used to indicate the data of the mode of operation of memory circuit;

Wherein, described control circuit comprises: synchronous input buffer and asynchronous input buffer device, its each all receive positive terminal control signal; And on-off circuit, it selects among the output of the output of described synchronous input buffer or described asynchronous input buffer device one according to the data of mode register; And the open and closed of described terminal resistance are controlled in the output of wherein said on-off circuit.

19. storage system as claim 18, also comprise: a plurality of memory modules, each has among a plurality of memory circuits that are installed on it at least one, wherein a plurality of positive terminal control signals are applied to respectively in the memory circuit of a plurality of memory modules, make the memory circuit of each memory module receive identical among a plurality of positive terminal control signals.

20. as the storage system of claim 18, wherein, a plurality of memory circuits at least one side that is installed in corresponding memory module are in the pattern following time of working hard, described on-off circuit is just selected the output of described synchronous input buffer; And await orders or power down operations pattern following time when all memory circuits of corresponding memory module are in, described on-off circuit is just selected the output of described asynchronous input buffer device.

21. as the storage system of claim 18, wherein, a plurality of memory circuits are mounted in the dynamic RAM circuit in the dual inline type memory module.

22. method that is used for the work of control store circuit:

Apply synchronous input buffer and the asynchronous input buffer device of an input signal to memory circuit; And

Selectively export the output of synchronous input buffer or the output of asynchronous input buffer device according to the mode of operation of memory circuit.

23. the method as claim 22 also comprises: according to the output of selected synchronous input buffer or asynchronous input buffer device, the terminal impedance of opening and closing memory circuit.

24. the method as claim 23 also comprises: the mode of operation signal that is provided by the memory circuit outside is provided, and wherein the control of the value of mode of operation signal is to the selection output of the output of the output of synchronous input buffer or asynchronous input buffer device.

25. the method as claim 23 also comprises: receive the value in the mode register be stored in memory circuit, wherein the control of the value of mode register is to the selection output of the output of the output of synchronous input buffer or asynchronous input buffer device.

26. the method for the open/close state of the terminal resistance of a control store circuit, described method comprises:

Apply synchronous input buffer and asynchronous input buffer device that a positive terminal control signal arrives memory circuit simultaneously;

When memory circuit is in the pattern following time of working hard, select the output of synchronous input buffer; And await orders or power down operations pattern following time when memory circuit is in, select the output of asynchronous input buffer device; And

According to selected one and the open/close state of terminal resistance is set among the output of the output of synchronous input buffer or asynchronous input buffer device.

27. method that is controlled at a plurality of terminal resistances of a plurality of memory circuits in the storage system, this storage system has a plurality of memory modules that are connected to data bus, each memory module is used to install among a plurality of memory circuits at least one to it, and described method comprises:

Apply synchronous input buffer and asynchronous input buffer device that a positive terminal control signal arrives each memory circuit of each memory module simultaneously;

In each memory circuit,, select the output of synchronous input buffer when memory circuit is in the pattern following time of working hard; And await orders or power down operations pattern following time when memory circuit is in, select the output of asynchronous input buffer device; And

In each memory circuit, among the output according to the output of synchronous input buffer or asynchronous input buffer device selected one and the open/close state of terminal resistance is set.

28. method that is controlled at a plurality of terminal resistances of a plurality of memory circuits in the storage system, this storage system has at least one first memory module and one second memory module that is connected to data bus, each memory module is used to install among a plurality of memory circuits at least one to it, and described method comprises:

Respond the read/write instruction of first memory module, send positive terminal control signal to each memory circuit of second memory module;

Apply a positive terminal control signal simultaneously to the synchronous input buffer and the asynchronous input buffer device of each memory circuit of second memory module;

In each memory circuit of second memory module,, select the output of synchronous input buffer when second memory module is in the pattern following time of working hard; Await orders or power down operations pattern following time when second memory module is in, select the output of asynchronous input buffer device; And

In each memory circuit of second memory module, among the output according to the output of synchronous input buffer or asynchronous input buffer device selected one and the open/close state of terminal resistance is set.

29. a terminal resistance that is installed in the memory circuit is used to memory circuit that terminal impedance is provided, this terminal resistance comprises:

A node;

Be connected a plurality of first terminal resistances of the corresponding control signal of response between supply voltage and the described node; And

Be connected a plurality of second terminal resistances of the corresponding control signal of response between ground voltage and the described node.

30. as the terminal resistance of claim 29, wherein, respond corresponding control signal, regulate impedance between described node and the supply voltage by being connected a plurality of first terminal resistances between described node and the supply voltage.

31. as the terminal resistance of claim 29, wherein, respond corresponding control signal, regulate impedance between described node and the ground voltage by being connected a plurality of second terminal resistances between described node and the ground voltage.

32. a terminal resistance that is installed in the memory circuit is used to memory circuit that terminal impedance is provided, this terminal resistance comprises:

A node;

Be connected first between supply voltage and the described node and open (UP) resistance;

Be connected second opening resistor of response first control signal between supply voltage and the described node, and

Be connected the 3rd opening resistor of response second control signal between supply voltage and the described node.

33. the terminal resistance as claim 32 also comprises:

Be connected first between ground voltage and the described node and close (DOWN) resistance;

Be connected second of response the 3rd control signal between ground voltage and the described node and close resistance;

Be connected the 3rd of response the 4th control signal between ground voltage and the described node and close resistance.

34. the terminal resistance as claim 32 also comprises:

First on-off circuit, it responds start signal, and Switching power voltage is to first opening resistor;

The second switch circuit, it responds first control signal, and Switching power voltage is to second opening resistor; And

The 3rd on-off circuit, it responds second control signal, Switching power voltage to the three opening resistors.

35. the terminal resistance as claim 34 also comprises:

The 4th on-off circuit, it responds shutdown signal, switches first and closes resistance to ground voltage;

The 5th on-off circuit, it responds the 3rd control signal, switches second and closes resistance to ground voltage; And

The 6th on-off circuit, it responds the 4th control signal, switches the 3rd and closes resistance to ground voltage.

36. as the terminal resistance of claim 35, wherein, first to the 6th on-off circuit is metal-oxide semiconductor (MOS) (MOS) transistor.

37. an impedance that is used for regulating the terminal resistance that is installed in memory circuit is so that for memory circuit provides the method for terminal impedance, this method comprises:

Respond corresponding control signal, measure one impedance among a plurality of first terminal resistances, described a plurality of first terminal resistances are connected between supply voltage and the node;

Use the measured corresponding control signal of impedance response, regulate the quantity that is connected first terminal resistance between supply voltage and this node.

38. the method as claim 37 also comprises:

Respond corresponding control signal, measure one impedance among a plurality of second terminal resistances, described a plurality of second terminal resistances are connected between ground voltage and this node;

Use the measured corresponding control signal of impedance response, regulate the quantity that is connected second terminal resistance between ground voltage and this node.