CN1414617A - Method for forming MOS device on silicon substrate - Google Patents

Method for forming MOS device on silicon substrate Download PDF

Info

Publication number
CN1414617A
CN1414617A CN02147045A CN02147045A CN1414617A CN 1414617 A CN1414617 A CN 1414617A CN 02147045 A CN02147045 A CN 02147045A CN 02147045 A CN02147045 A CN 02147045A CN 1414617 A CN1414617 A CN 1414617A
Authority
CN
China
Prior art keywords
ion
doping
region
device active
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN02147045A
Other languages
Chinese (zh)
Other versions
CN1310296C (en
Inventor
井口胜次
许胜籐
大野芳睦
马哲申
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/035,503 external-priority patent/US6780700B2/en
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of CN1414617A publication Critical patent/CN1414617A/en
Application granted granted Critical
Publication of CN1310296C publication Critical patent/CN1310296C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the device active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one device active area and implanting ions of a second type to form a source region and a drain region in the other device active area.

Description

A kind of method that on silicon substrate, forms the MOS device
Cross reference with relevant application
The application is based on the subsequent application of 09/649, No. 382 application of " Methedof Febricating Deep Sub-Micron CMOS Source/Drain with MDD andSelective CVD Silicide " by name that people such as Iguchi submits on August 28th, 2000.
Invention field
The present invention relates to metal-oxide semiconductor (MOS) (MOS) and complementary metal oxide semiconductors (CMOS) (CMOS) integrated circuit (IC) manufacture craft, specially refer to the sub-micron MOS of routine and compare a kind of new technology that needs less step with the CMOS manufacturing process.
Background of invention
In comprising the transistorized integrated circuit of MOS and CMOS, the known prior art processes that is used to make the source/drain regions of the active device low dose ion that need mix, this is called LDD and mixes, and will form gate lateral wall insulator and n+ and p+ ion doping then.After n+ and p+ ion doping, need carry out self-aligned silicide usually and handle with any dead resistance in the source/drain regions that reduces device.If adopt conventional manufacturing technology, this needs four to go on foot independently mask operation: the LDD ion doping needs two masks, and the n+ ion doping needs the 3rd mask, and the p+ ion doping needs the 4th mask.The example that self-aligned silicide is handled is a kind of refractory metal of deposit, handles forming a kind of single silicide then by rapid thermal annealing (RTA).After RTA, etch away nonreactive metal, handle forming the low resistance disilicide subsequently with next RTA.
A kind of more excellent method of making MOS device and COMS device should be to reduce the quantity and the ion doping step of mask level.
More excellent method also should be able to only form a silicide layer with a step selectivity CVD silicide deposition.
Summary of the invention
The invention provides a kind of method that on silicon substrate, forms the MOS device.The step of an embodiment who illustrates of the present invention comprises substrate of preparation, to hold a conduction region of first conduction type with first device active region; Form gate electrode structure on first device active region, gate electrode structure comprises gate electrode and insulative sidewall; Doping and the ion that above-mentioned first device active region has films of opposite conductivity form source electrode and drain region in the relative both sides of above-mentioned grid structure in the exposure portion of above-mentioned conduction region; And use silicide layer of selectivity CVD deposit at above-mentioned source electrode with above the drain region.
The preferred method of the present invention also is included in the doping step and immerses ion doping with plasma, and according to the energy range dopant ion of 0.5keV to 2keV, the scope of dosage is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2, the surface ion concentration range that produces in source electrode and drain region is 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3
Another optional preferred embodiment of the present invention is to carry out the doping step with the low energy ion doping before forming gate lateral wall.When adopting low energy ion to mix, be in the energy range of 10keV, to carry out dopant ion at about 0.5keV, the scope of dosage approximately is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2, the surface ion concentration range that produces in source electrode and drain region approximately is 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3
In another embodiment of the present invention, provide a kind of method that on silicon substrate, forms cmos device.In the present embodiment, the substrate of preparation comprises the conduction region that inside has the first kind of first device active region; And comprise the conduction region that inside has second type of second device active region.Its step further is included in and forms a gate electrode on first and second active areas; Deposit and form a gate electrode sidewalls insulator layer on each gate electrode; Conduction region mask to the first kind; The ion of second type of mixing in the exposure portion of the conduction region of the first kind forms source electrode and drain region; Lift off mask; And use silicide layer of selectivity CVD deposit at the source electrode of first and second device active regions with above the drain region.
Additional step among the optional embodiment comprises that immersing ion doping with plasma as mentioned above comes dopant ion, forms source/drain regions.
According to another embodiment of the present invention, form cmos device with above-mentioned step, ion doping is to carry out ion doping before the formation gate lateral wall that mixes with low energy ion only, and forms gate lateral wall after the ion doping step.
Brief description
Fig. 1-6 expression is used for the step that plasma immerses the inventive method of ion doping.
Fig. 7-11 expression is used for the step of the inventive method of low energy ion doping.
The explanation of preferred embodiment
At first describe and on substrate, form cmos device with method of the present invention.The invention provides a kind of technology of making cmos device, wherein saved mask and these two steps of photoresist lift off of adopting in the conventional cmos manufacture method at least.In addition, self-aligned silicide layer of deposit in single chemical vapor deposition (CVD) processing step, thus reduce time and the cost of making.One embodiment of the present of invention using plasma immerses ion doping, and it is effectively general to forming required CMOS, and is a preferred embodiment.Can also adopt low energy ion to mix, and in another embodiment of the present invention, be used.
" sub-micron " means that the width of the gate electrode that uses is below 1000nm in structure of the present invention.Any suitable integrated circuit interconnection material that comprises all refractory metals is all available, and aluminium is the most frequently used.Be in n type substrate, to form the p-trap in the example that this paper provides, also can adopt this structure and manufacture craft in p type substrate, to form the n-trap certainly, thereby make a kind of complementary metal oxide semiconductors (CMOS) (CMOS) device.
Plasma immerses ion doping
Referring to Fig. 1, structure 10 comprises the substrate 12 that can be monocrystalline silicon, and it is a n type substrate in a preferred embodiment.Adopt the technology of prior art, be also referred to as herein in the n channel region of first kind conduction region and form a p-trap 14, just first device active region.Being also referred to as in substrate 12 in the p channel region of the second type conduction region provides a n-trap 16 as second device active region.Term " first kind " and " second type " are meant " first conduction type " and " second conduction type " herein respectively, and represent n type or p N-type semiconductor N material separately respectively, and wherein first conduction type is relative with second conduction type.Substrate is taked suitable device isolation and threshold voltage adjustment and the isolated area 21 that forms, be gate oxide then, and the formation gate electrode forms a p-trap gate electrode 18 on gate regions 17, and forms a n-trap gate electrode 20 on gate regions 19.
With thin layer insulator of CVD deposit for example is silica or silicon nitride, as shown in Figure 2, uses the plasma anisotropic etching, to form gate electrode sidewalls insulator layer 22,24 respectively on gate electrode 18,20.
Referring to Fig. 3, on the p channel region, form one deck photoresist 26, it is used as second device active region in the present embodiment.Immerse ion doping by plasma, Doped n-type ion in the exposed region of first device active region 14 is referred to as the ion of second type in the present embodiment.Immerse ion doping to the implant energy of 2keV scope with plasma according to 0.5keV and come arsenic doped or phosphonium ion, the surface of doping p-trap 14.The optimal dose of dopant ion generally is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Scope in.According to this and other embodiment of the present invention, the technology that forms the n+ source/drain regions is to form drain electrode (MDD) device that a kind of medium (or mitigation) mixes.Lift off mask 26 then.
Then referring to Fig. 4, at n channel region photoresist mask 34 of deposit above first device active region 14 just.Immerse ion doping, doped p type ion in the exposed region of second device active region 16 by plasma.Immerse ion doping with plasma and come doped with boron or BF2 ion, the surface of doping p channel region 16, the scope of implant energy is still 0.5keV to 2keV.The optimal dose of dopant ion generally is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Scope in.The result has just formed a p+ drain region 38 and a p+ source area 40.Surface ion concentration range in the p+ source/drain regions is 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3Lift off mask 34 then.
Referring to Fig. 5,, form silicide layer 42 in the n channel region and the silicide layer 44 in the p channel region at source electrode and depositing silicide layer above the drain region.Selectivity CVD with silicide only comprises source electrode, depositing silicide above the conduction region of gate electrode and drain region on substrate.The selectivity CVD of silicide is depositing silicide on insulating surfaces such as insulation layer 21 and gate lateral wall 22,24 not.The selectivity CVD of silicide is the known prior art processes of technical staff in the IC manufacturing field.For example can be referring to " Selective Deposition of TiSi2 OnUltra-Thin Silicon-on-Insulator (SOI) Wafers, " Thin SolidFilms of people such as Maa, Vol.332, pp.412-417,1998; People's such as Maa " Effects onSelective CVD of Titanium Disilicide by Substrate Dopingand Selective Silicon Deposition ", Mat.Res.Soc.Symp.Proc., Vol.564, pp.85-89,1999; " Prevention of CornerVoiding in Selective CVD of Titanium Silicide on SOI Device, " Mat.Res.Soc.Symp.Proc. of people such as Maa, Vol.564, pp.29-34,1999; And " Selective to Silicon Nitride in Chemical Vapor Depositionof Titanium Silicide, " J.Vac.Sci.Technology B17 (5) of people such as Maa, Sept/Oct1999, pp.2243-47.
Activate this structure by annealing in that selectivity CVD deposit is forward and backward.The annealing that suggestion is used in this and other embodiment of the present invention is to carry out with 10 seconds to 30 minutes to anneal in 600 ℃ to 1000 ℃ temperature ranges.
As shown in Figure 6, with CVD deposit one deck oxide 46, metallization then.Electrode is connected to nMOST source electrode 30 48 this moments, and electrode 50 is connected to nMOST grid 18, and electrode 52 is connected to nMOST drain electrode 32, and electrode 54 is connected to pMOST drain electrode 38, and electrode 56 is connected to DMOST grid 20, and electrode 58 is connected to pMOST source electrode 40.
The low-power plasma body immerses ion doping and can cause ion by the horizontal infiltration significantly of the insulator sidewall pad on the gate electrode.Therefore, with the known technology of selecting sidewall thickness obtain suitable lateral wall insulation body thickness and suitable grid overlapping to source/drain.Referring to N.W.Cheung, " Plasma Immersion Ion Implantation forSemiconductor Processing, " Materials Chemistry andPhysics, Vol.46, (1996), p.132-139.
Those skilled in the art finds out easily, and first and second device active regions 14,16 are covered and the order that mixes is random and can exchanges.For example this method can be made at first cover as shown in Figure 4 into first device active region 14, the ion of the doping first kind in second device active region 16, lift off mask, cover second device active region 16 then as shown in Figure 3, and the ion of second type of in first device active region 14, mixing.Other step of this method is constant.
Low energy ion mixes
If adopt traditional low energy ion to mix, the horizontal infiltration that mixes up ion is seldom.Revise the processing sequence of preferred embodiment, after forming source electrode and drain region, form side wall insulator, as the described situation of reference Fig. 7-11.
Referring to Fig. 7, structure 70 comprises the substrate 72 of monocrystalline silicon.Adopt prior art processes in the n of structure 70 channel region, to form a p-trap 74; In the p of structure 70 channel region, form a n-trap 76.Form isolated area 77 with suitable device isolation, and the adjusting threshold voltage is gate oxidation then, forms gate electrode, formation in the above has the p-trap gate regions 78 of p-trap gate electrode 80, and formation has the n-trap gate regions 82 of n-trap gate electrode 84 in the above.Do not form the sidewall adjacent at this moment with gate electrode 80,84.
As shown in Figure 7, form one deck photoresist 86 on n channel region (first device active region 74 just) and above the p channel region (second device active region 76 just).Etch away that a part of photoresist above the n raceway groove, expose the surface that first device active region is a p-trap 74.The low energy ion of carrying out phosphorus or arsenic ion to the scope of 10keV according to about 0.5keV mixes the surface of doping p-trap 74.The optimal dose scope of dopant ion is normally about 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Scope in.The result has just formed n+ source area 90 and n+ drain region 92.Surface ion concentration in the n+ source/drain regions is greatly about 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3Between.Lift off mask 86 then.
Referring to Fig. 8, be deposit one deck photoresist mask 94 above first device active region at n channel region 74.Still press 0.5keV and carry out boron or BF to the scope of 10keV 2The low energy ion of ion mixes, the surface of second device active region 76 that mixes.The optimal dose scope of dopant ion is normally 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Scope in.The result has just formed p+ drain region 98 and p+ source area 100.Surface ion concentration in the p+ source/drain regions is 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3Between.Lift off mask 94 then.
As shown in Figure 9, with the insulator of CVD deposit one deck thin layer, for example silica or silicon nitride, and with the plasma anisotropic etching respectively round gate electrode 80 and 84 formation side wall insulators 102 and 104.
Referring to Figure 10, after forming sidewall 102,104,, in the n channel region, form silicide layer 106, and in the p channel region, form silicide layer 108 at source electrode and drain region and gate electrode 80, the 84 top selectively deposited silicides of CVD of using.Preferred silicide film comprises Titanium silicide but is not limited only to Titanium silicide.Can be with comprising TiCl in the RTCVD reactor 4, silane, the mist of dichlorosilane and hydrogen carries out deposit.If select for use, need to substitute TiCl with suitable precursor such as other silicide films such as cobalt silicide, nickel silicides 4
As shown in figure 11, with CVD deposit one deck oxide 110, carry out passivation and metallization then.Electrode 112 is connected to CMOS124nMOST source electrode 90 at this moment, electrode 114 is connected to nMOST grid 80, and electrode 116 is connected to nMOST drain electrode 92, and electrode 118 is connected to pMOST drain electrode 98, electrode 120 is connected to pMOST grid 84, and electrode 122 is connected to pMOST source electrode 100.
Described above form the transistorized method of CMOS according to the present invention.The present invention also is fit to form the MOS device, and in this device, all devices that form in the substrate reactivity device region all have identical conduction type.Form the left half side of n channel device in need be referring to Fig. 1-11 only describing when forming MOS transistor according to the present invention.Should understand easily, the present invention can be applicable to equivalently by identical method and form the p channel device, but will adopt the substrate and the dopant ion of films of opposite conductivity.
Left half side referring to Fig. 1-6, it provides a kind of method that forms the MOS device on silicon substrate 12.Prepare the substrate with first device active region 14, said herein is p type conductivity.Form gate electrode structure on first device active region 14, this grid structure comprises electrode 1 and insulative sidewall 22.Form substrate, grid and insulative sidewall according to the method described in the previous embodiment.
Referring to Fig. 3,, form source electrode and drain region in the relative both sides of above-mentioned grid structure from the exposed region of substrate, mix a kind of ion of films of opposite conductivity of first device active region 14.In the present embodiment, be Doped n-type ion in p-trap 14.Immerse ion doping by plasma, in this enforcement in the exposed region of first device active region 14 ion of Doped n-type.Immerse ion doping to the implant energy of 2keV scope with plasma according to 0.5keV and come arsenic doped or phosphonium ion, the surface of doping p-trap 14.The optimal dose of dopant ion generally is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Scope in.The result just forms a n+ source area 30 and a n+ drain region 32.Surface ion concentration in the n+ source/drain regions is 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3Between.
As shown in Figure 5, at source electrode and drain region 30,32 top depositing silicide layers.CVD with silicide comprises source electrode on substrate, depositing silicide on the conduction region of gate electrode and drain region.
At last as described in Figure 6, with CVD deposit one deck oxide 46, metallization then.Be connected to nMOST source electrode 30 with electrode 48 this moment, and electrode 50 is connected to nMOST grid 18, and electrode 52 is connected to nMOST drain electrode 32.
Left half side referring to Fig. 7-11 provides a kind of the doping with low energy ion on silicon substrate 72 to replace plasma to immerse the method that ion doping forms the MOS device.Referring to Fig. 7, prepare a substrate with first device active region 74, said herein is p type conductivity.Form gate electrode structure on first device active region 74, this grid structure comprises electrode 80, but does not comprise insulative sidewall.Form substrate, grid and insulative sidewall according to the method described in the previous embodiment.
Referring to Fig. 8,, form source electrode and drain region in the relative both sides of above-mentioned grid structure from the exposed region of substrate, mix a kind of ion of films of opposite conductivity of first device active region 74.Be Doped n-type ion in p-trap 74 in the present embodiment.The execution low energy ion mixes, the ion of Doped n-type in the exposed region of first device active region 74.Mix arsenic doped or phosphonium ion with low energy ion, the surface of doping p-trap 74 according to 0.5keV to the implant energy of 10keV scope.The optimal dose of dopant ion generally is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Scope in.The result just forms a n+ source area 90 and a n+ drain region 92.Surface ion concentration in the n+ source/drain regions is 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3Between.
Shown in Fig. 9 left side is half side, form insulative sidewall 102 then round gate electrode 80.
Then as shown in figure 10 at source electrode and drain region 90,92 top and gate electrode 80 top silicide layers of deposit.CVD with silicide comprises source electrode on substrate, depositing silicide on the conduction region of gate electrode and drain region.
At last as shown in figure 11, with CVD deposit one deck oxide 110, metallization then.Be connected to nMOST source electrode 90 with electrode 112 this moment, and electrode 114 is connected to nMOST grid 80, and electrode 116 is connected to nMOST drain electrode 92.
Plasma immerses the penetrability of ion doping than much higher times of traditional ion doping.When adopting conventional ion to mix, the processing time can be with the proportional increase of chip area, and plasma to immerse the time of ion doping be constant, thereby tangible advantage is arranged along with substrate dimension increases.Therefore, it is more superior than traditional ion doping method that plasma immerses ion doping method.
A kind of method of making deep sub-micron MOS and CMOS source/drain with MDD and selectivity CVD silicide more than has been described.In the scope of the invention that claims limited, obviously can also carry out further modifications and changes to it.

Claims (22)

1. method that forms the MOS device on silicon substrate comprises:
A) substrate of preparation is to hold a conduction region of first conduction type with first device active region;
B) form gate electrode structure on first device active region, described gate electrode structure comprises gate electrode and insulative sidewall;
C) doping and the ion that described first device active region has films of opposite conductivity in the exposure portion of described conduction region forms source electrode and drain region with the relative both sides in described gate electrode structure; And
D) by chemical vapor deposition selectively at described source electrode and silicide layer of deposit above the drain region and above the described gate electrode.
2. in accordance with the method for claim 1, wherein said doping step c) comprises with plasma and immerses ion doping, the energy range dopant ion to 0.5keV to 2keV.
3. in accordance with the method for claim 1, wherein said doping step c) comprises that immersing ion doping with plasma comes dopant ion, comprises that dosage range is 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Doping.
4. in accordance with the method for claim 1, wherein said doping step c) comprises that immersing ion doping with plasma comes dopant ion, comprises that the surface ion scope of carrying out producing in above-mentioned source electrode and the drain region is about 1.0 * 10 19Cm -3To 1.0 * 10 22Cm -3Doping.
5. in accordance with the method for claim 1, be included in after the step d) of utilizing a silicide layer of chemical vapor deposition, carry out following steps, insulating barrier of deposit on the structure that obtains by step a)-d), and with this structural metalization.
6. on silicon substrate, form a kind of method of MOS device, comprising:
A) substrate of preparation is to hold a conduction region of first conduction type with first device active region;
B) on first device active region, form gate electrode;
C) doping and the ion that described first device active region has films of opposite conductivity in the exposed region of described conduction region forms source electrode and drain region with the relative both sides at described gate electrode;
D) form the insulated gate electrode sidewall adjacent with described gate electrode; And
E) by chemical vapor deposition at described source electrode and silicide layer of deposit above the drain region and above the described gate electrode.
7. in accordance with the method for claim 6, wherein said doping step c) comprises and utilizes low energy ion to be entrained in the energy range dopant ion of 0.5keV to 10keV.
8. in accordance with the method for claim 6, wherein said doping step c) comprises and mixes dopant ion with low energy ion, and comprises by about 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Dosage range mix.
9. in accordance with the method for claim 6, wherein said doping step c) comprises with low energy ion mixes dopant ion, and comprises that the surface ion concentration range of carrying out producing in described source electrode and drain region is 1.0 * 10 approximately 19Cm -3To 1.0 * 10 22Cm -3Doping.
10. in accordance with the method for claim 6, be included in after the described step e) of utilizing a silicide layer of CVD deposit, carry out following steps, insulating barrier of deposit on the structure that obtains by step a)-e), and with this structural metalization.
11. a method that forms cmos device on silicon substrate comprises:
A) substrate of preparation holding a conduction region of the first kind with first device active region, and holds a conduction region of second type with second device active region;
B) on first and second device active regions, form gate electrode;
C) deposit and form a gate electrode sidewalls insulator layer on each gate electrode;
D) cover first device active region;
E) ion of the doping first kind in the exposed region of second device active region forms source electrode and drain region in second device active region;
F) lift off mask;
G) cover second device active region;
H) ion of doping second type in the exposed region of first device active region forms source electrode and drain region in first device active region;
I) lift off mask; With
J) at gate electrode and source electrode and silicide layer of deposit above the drain region of first and second device active regions.
12. wherein said doping step e) and h in accordance with the method for claim 11) comprise that immersing ion doping with plasma comes dopant ion.
13. wherein said doping step e) and h in accordance with the method for claim 12) scope that is included in for about 0.5keV to the energy grade between the 2keV and scope about 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Between dosage mix.
14. in accordance with the method for claim 12, wherein said doping step e) and h) comprise, carry out the surface ion concentration range about 1.0 * 10 that in described source electrode and drain region, produces 19Cm -3To 1.0 * 10 22Cm -3Doping.
15. the described step j of depositing silicide layer wherein in accordance with the method for claim 11) comprise silicide layer of chemical vapor deposition with silicide.
16. in accordance with the method for claim 11, be included in the described step j of depositing silicide layer) afterwards, carry out following steps, insulating barrier of deposit on the structure that obtains by step a)-j), and with this structural metalization.
17. a method that forms cmos device on silicon substrate comprises:
A) substrate of preparation holding a conduction region of the first kind with first device active region, and holds a conduction region of second type with second device active region;
B) on first and second device active regions, form gate electrode;
C) cover first device active region;
D) ion of the doping first kind in the exposed region of second device active region forms source electrode and drain region in second device active region;
E) lift off mask;
F) cover second device active region;
G) ion of doping second type in the exposed region of first device active region forms source electrode and drain region in first device active region;
H) lift off mask;
I) deposit and form a gate electrode sidewalls insulator layer on each gate electrode; And
J) silicide layer of deposit on the exposed surface of the gate electrode of first and second device active regions and source electrode and drain region.
18. wherein said doping step d) and g in accordance with the method for claim 17) comprise and utilize low energy ion to mix dopant ion.
19. wherein said doping step d) and g in accordance with the method for claim 18) scope that is included in for about 0.5keV to the energy grade between the 10keV and scope about 1.0 * 10 14Cm -2To 1.0 * 10 15Cm -2Between dosage mix.
20. in accordance with the method for claim 18, wherein said doping step d) and g) comprise that the surface ion concentration range of carrying out producing in above-mentioned source electrode and drain region is 1.0 * 10 approximately 19Cm -3To 1.0 * 10 22Cm -3Doping.
21. the described step j of depositing silicide layer wherein in accordance with the method for claim 17) comprise that the selective chemical vapor deposition that utilizes silicide comes silicide layer of deposit.
22. in accordance with the method for claim 17, be included in the above-mentioned steps j of depositing silicide layer) afterwards, carry out following steps, insulating barrier of deposit on the structure that obtains by step a)-j), and with this structural metalization.
CNB021470456A 2001-10-25 2002-10-25 Method for forming MOS device on silicon substrate Expired - Fee Related CN1310296C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/035,503 US6780700B2 (en) 2000-08-28 2001-10-25 Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide
US10/035503 2001-10-25

Publications (2)

Publication Number Publication Date
CN1414617A true CN1414617A (en) 2003-04-30
CN1310296C CN1310296C (en) 2007-04-11

Family

ID=21883105

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021470456A Expired - Fee Related CN1310296C (en) 2001-10-25 2002-10-25 Method for forming MOS device on silicon substrate

Country Status (4)

Country Link
JP (1) JP2003179071A (en)
KR (1) KR100499755B1 (en)
CN (1) CN1310296C (en)
TW (1) TW589670B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100356550C (en) * 2004-12-15 2007-12-19 东部亚南半导体株式会社 CMOS image sensor and manufacturing method thereof
CN100394614C (en) * 2003-12-01 2008-06-11 台湾积体电路制造股份有限公司 Semiconductor device and methods of manufacture
CN101287304B (en) * 2006-12-18 2013-02-06 桑尼奥公司 Deep sub-micron MOS preamplifier with thick-oxide input stage transistor
CN103811420A (en) * 2012-11-08 2014-05-21 中芯国际集成电路制造(上海)有限公司 Preparation method of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101006439B1 (en) * 2003-11-12 2011-01-06 삼성전자주식회사 Method for manufacturing of Thin film transistor array panel

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980030449A (en) * 1996-10-29 1998-07-25 김영환 Manufacturing Method of CMOS Transistor
US6060345A (en) * 1997-04-21 2000-05-09 Advanced Micro Devices, Inc. Method of making NMOS and PMOS devices with reduced masking steps
US6218276B1 (en) * 1997-12-22 2001-04-17 Lsi Logic Corporation Silicide encapsulation of polysilicon gate and interconnect
US6242354B1 (en) * 1998-02-12 2001-06-05 National Semiconductor Corporation Semiconductor device with self aligned contacts having integrated silicide stringer removal and method thereof
US6187619B1 (en) * 1998-02-17 2001-02-13 Shye-Lin Wu Method to fabricate short-channel MOSFETs with an improvement in ESD resistance
TW437052B (en) * 1998-03-30 2001-05-28 United Microelectronics Corp Manufacturing method for electrostatic protection circuit with reduced photomask processing

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100394614C (en) * 2003-12-01 2008-06-11 台湾积体电路制造股份有限公司 Semiconductor device and methods of manufacture
CN100356550C (en) * 2004-12-15 2007-12-19 东部亚南半导体株式会社 CMOS image sensor and manufacturing method thereof
CN101287304B (en) * 2006-12-18 2013-02-06 桑尼奥公司 Deep sub-micron MOS preamplifier with thick-oxide input stage transistor
CN103811420A (en) * 2012-11-08 2014-05-21 中芯国际集成电路制造(上海)有限公司 Preparation method of semiconductor device
CN103811420B (en) * 2012-11-08 2016-12-21 中芯国际集成电路制造(上海)有限公司 A kind of preparation method of semiconductor device

Also Published As

Publication number Publication date
KR100499755B1 (en) 2005-07-07
KR20030033995A (en) 2003-05-01
CN1310296C (en) 2007-04-11
TW589670B (en) 2004-06-01
JP2003179071A (en) 2003-06-27

Similar Documents

Publication Publication Date Title
US6894357B2 (en) Gate stack for high performance sub-micron CMOS devices
US5877041A (en) Self-aligned power field effect transistor in silicon carbide
US6730584B2 (en) Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
EP0991114A2 (en) Ultra-low sheet resistance metal/poly-SI gate for deep sub-micron CMOS application
US6300205B1 (en) Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions
US20140106531A1 (en) Field effect transistor device having a hybrid metal gate stack
US7163878B2 (en) Ultra-shallow arsenic junction formation in silicon germanium
US6096647A (en) Method to form CoSi2 on shallow junction by Si implantation
US6677201B1 (en) Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors
CN1812060A (en) Manufacture method of semiconductor device
US5683920A (en) Method for fabricating semiconductor devices
CN112151367B (en) Semiconductor device and method of forming the same
US5723352A (en) Process to optimize performance and reliability of MOSFET devices
CN1310296C (en) Method for forming MOS device on silicon substrate
US5930632A (en) Process of fabricating a semiconductor device having cobalt niobate gate electrode structure
CN116504718A (en) Manufacturing method of semiconductor structure
US5976925A (en) Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode
US6780700B2 (en) Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide
US6406952B2 (en) Process for device fabrication
US7015088B2 (en) High-K gate dielectric defect gettering using dopants
US6232208B1 (en) Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile
US5923984A (en) Method of making enhancement-mode and depletion-mode IGFETS with different gate materials
CN1188982A (en) Semiconductor device and method for producing same
US5976924A (en) Method of making a self-aligned disposable gate electrode for advanced CMOS design
US6376311B2 (en) Vertical double diffused MOSFET and method for manufacturing same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070411

Termination date: 20111025