CN1414423A - Plane display device panel - Google Patents
Plane display device panel Download PDFInfo
- Publication number
- CN1414423A CN1414423A CN 02150430 CN02150430A CN1414423A CN 1414423 A CN1414423 A CN 1414423A CN 02150430 CN02150430 CN 02150430 CN 02150430 A CN02150430 A CN 02150430A CN 1414423 A CN1414423 A CN 1414423A
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- panel
- control circuit
- display control
- circuit
- display panel
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- Liquid Crystal Display Device Control (AREA)
Abstract
A display flat faceplate includes the following assemblies: The pixel matrix is set up on the base plate. The display control circuit set up on the base plate is connected to the pixel matrix electrically, in order to control the on/off of the pixel matrix. The embedded type testing circuit set up on the base plate is connected to the display control circuit, in order to test the display control circuit and output the tested result to outside the faceplate.
Description
Technical field
The present invention relates to a kind of display device, especially a kind of flat display panel with embedded testing circuit.
Background technology
See also Fig. 1, it is the function square configuration diagram of an at present common LCD panel of thin-film transistor, central part has a picture element matrix 10, and picture element matrix 10 is provided with horizontal scanning circuit 11 and vertical scanning circuit 12 on every side (if the size of picture element matrix 10 is very big, then must all be provided with horizontal scanning circuit in both sides and just have enough driving forces), and a drive integrated circult 13 (driver IC) that is arranged at panel 1 outside is connected with this panel by several signal wiring 14 (being generally a soft arranging wire), transmitting drive signal, and then drive this panel and show to this panel.
Because thin film transistor (TFT) improvement of Manufacturing Technology, feasible script is arranged in the vertical scanning circuit 11 of drive integrated circult 13 and horizontal scanning circuit 12 and can goes on the panel and finish, therefore when desire was finished sweep circuit on panel and carried out test procedure this type of, conventional means needed extra increasing on panel that the external test circuitry (not shown) is transmitted the required a plurality of tests signal pin 15 of signal.Thus, too much test will significantly increase the manufacturing cost of panel of LCD with the signal pin, but very few test pin number, but the speed and the accuracy of influence test under test structure commonly used.And how to improve this type of defective commonly used, for developing fundamental purpose of the present invention.
Summary of the invention
The object of the present invention is to provide a kind of flat display panel, its manufacturing cost can not increase with the signal pin because of increasing too much test, and the speed of test and accuracy can not be affected with the pin number because of very few test yet.
The present invention discloses a kind of flat display panel, and it includes following assembly: a substrate; One picture element matrix is arranged on this substrate; One display control circuit is arranged on this substrate and is electrically connected on this picture element matrix, and it controls the open and close of this picture element matrix; And an embedded testing circuit, being arranged on this substrate and being electrically connected on this display control circuit, it is tested this display control circuit and obtains after the test result to the outside output of panel.
Described flat display panel, wherein this substrate is a transparent substrates.
Described flat display panel, wherein this picture element matrix is for finishing the initiatively display pixel matrix of switch with thin film transistor (TFT).
Described flat display panel, wherein this display control circuit includes a horizontal scanning circuit at least.
Described flat display panel, wherein this display control circuit includes a vertical scanning circuit at least.
Described flat display panel, wherein this embedded testing circuit is exported this test result with the signal pin to the panel outside by a test.
Described flat display panel, wherein this embedded testing circuit and this display control circuit are shared a signal pin and are exported this test result to the panel outside.
Described flat display panel, wherein this display control circuit includes several offset buffer groups and a display drive logic circuit.
Described flat display panel, wherein this embedded testing circuit includes a combinational logic circuit, it receives these offset buffer groups and this display drive logic circuit are sent respectively in this display control circuit several signals judging, and then obtains after this test result to the outside output of panel.
Described flat display panel, wherein this embedded testing circuit includes a combinational logic circuit, and it receives several signals that this display control circuit sends judging in test procedure, and then obtains after this test result to the outside output of panel.
Description of drawings
The present invention is able to more deep understanding by following accompanying drawing and detailed description:
Fig. 1 is the function square configuration diagram of an at present common LCD panel of thin-film transistor;
Fig. 2 is a preferred embodiment function block schematic diagram of the present invention;
Fig. 3 is the example schematic of this embedded testing circuit in the above-mentioned preferred embodiment.
Assembly is as follows:
| Panel 1 | |
| | |
| Drive integrated | Signal wiring 14 |
| Test signal pin 15 | |
| | |
| | |
| Embedded | |
| | Display |
| | |
Embodiment
See also Fig. 2, the preferred embodiment function block schematic diagram that it for the present invention develops, similarly, panel 2 of the present invention has a picture element matrix 20 at central part, and picture element matrix 20 is provided with the display control circuit 21 that horizontal scanning circuit 211 and vertical scanning circuit 212 are constituted on every side.And the invention is characterized in and have additional an embedded testing circuit 22 on the panel 2, and this embedded testing circuit 22 all is arranged on the transparent substrates 23 jointly with other assembly.
See also Fig. 3 again, it is the function block schematic diagram of this embedded testing circuit 22 in the above-mentioned preferred embodiment, it is mainly finished with a combinational logic circuit 31, its can receive several offset buffer groups 301 in this display control circuit 21 ..., several output signals of being sent respectively of the built-in display drive logic circuit 40 of 30n and panel judge.For instance, several offset buffer groups 301, the built-in display drive logic circuit 40 of 30n and panel just begins to carry out test procedure after receiving test signal, to produce corresponding these output signals at last respectively judges to deliver to this combinational logic circuit 31, when the built-in display drive logic circuit 40 of all offset buffer groups and panel all during regular event, combinational logic circuit 31 just sends a test normal signal (for example logical zero), as long as and when wherein having the built-in display drive logic circuit 40 of an offset buffer group or panel to fail regular event, just combinational logic circuit 31 can send a test crash signal (for example logical one).Thus, the tester just can make things convenient for and learn whether operate as normal of this display control circuit 21 apace.
Because this embedded testing circuit 22 all finishes on transparent substrates 23 with testing component, therefore a plurality of tests that are provided with between the two all can directly be made in the inside of panel 2 with the signal wiring, just can not increase the number of panel 2 external pins.So the tester just can make things convenient for and only learn whether operate as normal of this display control circuit 21 by a test with test normal signal that is transmitted on the signal pin or test crash signal apace.And this root test can be shared a signal pin with this display control circuit 21 with the signal pin, or advancing the test that only need set up a special use gets final product with the signal pin.
In sum, the present invention can't increase too much test increases panel of LCD with the signal pin manufacturing cost, also can not have influence on the speed and the accuracy of test because of very few test with the pin number.
Claims (10)
1. a flat display panel is characterized in that, includes following assembly:
One substrate;
One picture element matrix is arranged on this substrate;
One display control circuit is arranged on this substrate and is electrically connected on this picture element matrix, and it controls the open and close of this picture element matrix; And
One embedded testing circuit is arranged on this substrate and is electrically connected on this display control circuit, and it is tested this display control circuit and obtains after the test result to the outside output of panel.
2. flat display panel as claimed in claim 1 is characterized in that, this substrate is a transparent substrates.
3. flat display panel as claimed in claim 1 is characterized in that, this picture element matrix is for finishing the initiatively display pixel matrix of switch with thin film transistor (TFT).
4. flat display panel as claimed in claim 1 is characterized in that this display control circuit includes a horizontal scanning circuit at least.
5. flat display panel as claimed in claim 1 is characterized in that, this display control circuit includes a vertical scanning circuit at least.
6. flat display panel as claimed in claim 1 is characterized in that, this embedded testing circuit is exported this test result with the signal pin to the panel outside by a test.
7. flat display panel as claimed in claim 1 is characterized in that, this embedded testing circuit and this display control circuit are shared a signal pin and exported this test result to the panel outside.
8. flat display panel as claimed in claim 1 is characterized in that, this display control circuit includes several offset buffer groups and a display drive logic circuit.
9. flat display panel as claimed in claim 8, it is characterized in that, this embedded testing circuit includes a combinational logic circuit, it receives these offset buffer groups and this display drive logic circuit are sent respectively in this display control circuit several signals judging, and then obtains after this test result to the outside output of panel.
10. flat display panel as claimed in claim 1, it is characterized in that, this embedded testing circuit includes a combinational logic circuit, and it receives several signals that this display control circuit sends judging in test procedure, and then obtains after this test result to the outside output of panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02150430 CN1203359C (en) | 2002-11-12 | 2002-11-12 | Plane display device panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02150430 CN1203359C (en) | 2002-11-12 | 2002-11-12 | Plane display device panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1414423A true CN1414423A (en) | 2003-04-30 |
| CN1203359C CN1203359C (en) | 2005-05-25 |
Family
ID=4751812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02150430 Expired - Fee Related CN1203359C (en) | 2002-11-12 | 2002-11-12 | Plane display device panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1203359C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426059C (en) * | 2005-12-08 | 2008-10-15 | 群康科技(深圳)有限公司 | Liquid-crystal display panel |
| WO2016123839A1 (en) * | 2015-02-04 | 2016-08-11 | 深圳市华星光电技术有限公司 | Detection line layout of array substrate and array substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452415B (en) * | 2007-11-30 | 2011-05-04 | 鸿富锦精密工业（深圳）有限公司 | Auxiliary device and method for testing embedded system |
-
2002
- 2002-11-12 CN CN 02150430 patent/CN1203359C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426059C (en) * | 2005-12-08 | 2008-10-15 | 群康科技(深圳)有限公司 | Liquid-crystal display panel |
| WO2016123839A1 (en) * | 2015-02-04 | 2016-08-11 | 深圳市华星光电技术有限公司 | Detection line layout of array substrate and array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1203359C (en) | 2005-05-25 |
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| C10 | Entry into substantive examination | ||
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050525 Termination date: 20151112 |
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| EXPY | Termination of patent right or utility model |