CN1405868A - 复合高密度构装基板与其形成方法 - Google Patents

复合高密度构装基板与其形成方法 Download PDF

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CN1405868A
CN1405868A CN02147141A CN02147141A CN1405868A CN 1405868 A CN1405868 A CN 1405868A CN 02147141 A CN02147141 A CN 02147141A CN 02147141 A CN02147141 A CN 02147141A CN 1405868 A CN1405868 A CN 1405868A
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substrate
viscosity
interconnect structure
formation method
multilayer interconnect
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CN1180461C (zh
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何昆耀
宫振越
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Via Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball

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Abstract

本发明涉及一种复合高密度内联线构装基板(Hybrid High Density Interconnect Substrate)与其形成方法，此复合多层内联线基板由将一载台基板(Carrier Substrate)与一形成于一操作基板(Handle Substrate)上的多层内联线结构(Multi－level Interconnect Structure)结合而形成，此多层内联线结构利用集成电路的沉积、微影与蚀刻制程形成。

Description

复合高密度构装基板与其形成方法
技术领域
本发明涉及一种构装基板与其形成方法，特别是一种具有高密度的复合多层内联线结构的构装基板与其形成方法。
背景技术
传统用于覆晶封装制程的基板包含增层结构(Build-up Structure)与压合结构(Laminate Structure)。图1显示一覆晶封装结构。如图1所示，一高密度多层内联线结构102形成于一基底材料(BaseMaterial)100上。高密度多层内联线结构102与基底材料100构成覆晶封装结构的基板。高密度多层内联线结构102与一覆置的芯片112由焊接凸块110与焊垫108的焊接结合以形成覆晶封装结构。多层内联线结构102包含一介电部份104与一电路部份106。多层内联线结构102具有多层介电层与电路层，而这些多层介电层与电路层由增层或压合的方式形成。
覆晶封装基板具有由一层接着一层直接形成于一基底材料上而成的多层内联线结构者为增层基板。该结构由直接形成多层内联线结构于一载台/核心基板(Carrier Substrate/Core Substrate)上而成，此载台基板为一印刷电路板。将多层内联线结构直接形成于载台基板上，此种增层基板结构具有精确的增层导线/间距及厚度控制、精准的阻抗控制与可直接将被动组件植入等优点。另外，增层基板的结构亦可同时直接形成多层内联线结构于一载台基板的两面上。尽管如此，此种增层基板会因为基板尺寸的更动而调整每次增层制程，故而会造成增加制造成本及降低良率等缺点。此外，由于多层内联线结构直接形成于载台基板上，增层基板的尺寸将受限于载台基板的尺寸，目前所用载台基板的尺寸最大限制约为610毫米×610毫米。
有鉴于上述传统基板结构与制程的缺点，因此有必要发展出一种新颖进步的基板结构与制程以克服传统基板结构与制程的缺点。而本发明正能符合这样的需求。
发明内容
本发明的一目的为提供一种具有高密度的复合多层内联线结构的基板，此复合基板由分别形成的低密度基板与高密度电路结构所构成，故具有高良率的优点。
本发明的另一目的为提供一种具有高密度的复合多层内联线结构的基板，此复合基板由现有的集成电路或薄膜晶体管液晶显示器(TFT-LCD)制程技术并利用大尺寸基板形成，故具有生产成本低的优点。
本发明的又一目的为提供一种具有高密度的复合多层内联线结构的基板，此复合基板并具有精准的阻抗控制的优点。
本发明的另一目的为提供一种具有高密度的复合多层内联线结构的基板，此复合基板具有可直接将被动组件植入的优点。
为了达成上述的目的，本发明提供一种具有多层内联线结构的基板的形成方法，该基板的形成方法包含以下步骤。首先提供一透光操作基板并形成一粘性光分解介电层于该操作基板上。接着形成一多层内联线结构于该粘性光分解介电层上。然后形成一粘性结合膜于该多层内联线结构上。图案化该粘性结合膜以暴露出该多层内联线结构的数个焊垫。接着由焊接结合该焊垫与一载台基板上的数个导体结合该多层内联线结构与该载台基板。分解该粘性光分解介电层并移除该操作基板。最后在移除该粘性光分解介电层。
上述有关发明的简单说明及以下的详细说明仅为范例并非限制。其它不脱离本发明的精神的等效改变或修饰均应包含在的本发明的权利要求书的范围之内。
附图说明
图1显示一覆晶封装结构；
图2A显示一具有一基底材料的操作基板；
图2B显示一多层内联线结构形成于基底材料上的结果；
图2C显示形成一结合膜于多层内联线结构上，接着被图案化以暴露出焊垫的结果；
图2D显示芯片载台基板与多层内联线结构焊接结合的结果；
图2E显示将操作基板与基底材料移除，形成一具有多层内联线结构的复合基板的结果；
图2F显示将图2E所示复合基板与一半导体芯片结合的结果。
图中符号说明
100    基底材料
102    高密度多层内联线结构
104    介电部份
106    电路部份
108    焊垫
110    焊接凸块
112    芯片
200    操作基板
202    基底材料
204    多层内联线结构
206    介电部份
208    焊垫
210    介层柱塞
212    焊垫
214    结合膜
216    芯片载台基板
218    印刷电路板
220    介层柱塞
222    焊垫
224    导体
228    介电材料
230    焊接凸块
232    半导体芯片
具体实施方式
在此必须说明的是以下描述的制程步骤及结构并不包含完整的制程。本发明可以由各种制程方法来实施，在此仅提及了解本发明所需的制程方法。
以下将根据本发明的附图做详细的说明，请注意图标均为简单的形式且未依照比例描绘，而尺寸均被夸大以利于了解本发明。
参考图2A所示，显示一具有一基底材料(Base Material)202的操作基板(Handle Substrate)200。操作基板200包含一透光平板，特别是一石英基板或一玻璃基板，此石英基板或玻璃基板尺寸可大于610毫米×610毫米。操作基板200的一较佳实例为用于薄膜晶体管液晶显示器(TFT-LCD)制程所用的玻璃基板。基底材料202具有粘性，且以一具粘性的高分子材料或离形膜(Release Film)较佳。离形膜为一般封装制程所用的介电膜，用于防止基板在运送至后续制程的过程中遭受外部环境所污染。此外，基底材料202能被例如紫外线与激光束照射分解，并在被分解后能被移除。
接着参考图2B所示，显示一多层内联线结构204形成于基底材料202上。多层内联线结构204包含一介电部份206与一导电部份。多层内联线结构204的导电部份包含焊垫208、212与介层柱塞210。图2B所示的多层内联线结构204为简化的图标。多层内联线结构204以薄膜晶体管液晶显示器制程所用的设备与制程形成，这些制程包含沉积、微影与蚀刻制程。此外，被动组件可直接植入于多层内联线结构204内。
参考图2C所示，显示形成一结合膜(Bonding Film)214于多层内联线结构204上，此结合膜214接着被图案化以暴露出焊垫212。结合膜214包含一具有粘性与附着力的介电膜，可具有半固化(Semi-Cured)的特性。图2C同时显示一芯片载台基板216。此芯片载台基板216包含一印刷电路板218，例如一低成本的类似球型数组基板(BallGrid Array Like Substrate)。此芯片载台基板216具有一包含焊垫222与介层柱塞220的电路。如图2C所示，导体224形成于焊垫222上。而导体224包含焊膏(Solder Paste)、表面镀着金属(Metal SurfaceCoating)或金属凸块(Metal Bump)。焊膏可用刮刀印刷(SqueegeePrinting)的方式形成，而表面镀着金属与金属凸块可以电镀的方式形成。结合膜214亦可形成于芯片载台基板216上并曝露出焊垫222而不形成于多层内联线结构204上。
接着参考图2D所示，由焊接结合导体224与焊垫212以及结合膜214的粘性与附着力，芯片载台基板216与多层内联线结构204焊接结合。接着基底材料202被紫外线或激光束照射并分解。紫外线或激光束穿透可透光的操作基板200到达基底材料202，并提供基底材料202分解所需的热(Heat Dose)。
参考图2E所示，显示将操作基板200与基底材料202依序移除，而形成一具有多层内联线结构的复合基板。分解的基底材料202以剥除(Stripping)或蚀刻的方式移除。图2F显示将图2E所示复合基板与一半导体芯片232结合的结果。复合基板与半导体芯片232由焊垫208与焊接凸块230的焊接结合以及介电材料228的填充固定而结合形成覆晶封装结构。介电材料228包含灌膠混合物(MoldingCompound)或覆晶填充(Underfill)物。
本发明提供了一种具有高密度的多层内联线结构的复合基板。利用微米/次微米集成电路制程与大尺寸石英/玻璃基板，高密度精细的电路先形成于石英/玻璃基板上，接着再被转移至一低成本的非增层基板上。由于使用成熟稳定的制程技术及大尺寸的操作基板，而非直接将精细电路图案增层形成于尺寸有限及低良率的核心基板(CoreSubstrate)上，此多层内联线结构的复合基板的生产成本低于传统的增层基板。本发明同时由分别形成低密度基板与高密度电路结构，而非直接形成高密度电路结构于核心基板上，可提高复合基板的良率，使其良率高于传统增层基板制程。利用高精准度与密度的多层内联线结构制程技术以形成具有精细、准确宽度与厚度的线路及介电层，本发明可提供良好的阻抗控制。此外，将被动组件直接植入多层内联线结构中可提升覆晶封装结构较良好的电性。另外，利用现有的集成电路或薄膜晶体管液晶显示器的制程设备、制程与导体、介电材料来形成多层内联线结构可提供较稳定良好的性质。
上述有关发明的详细说明仅为范例并非限制。其它不脱离本发明的精神的等效改变或修饰均应包含在的本发明的权利要求书范围之内。

Claims (10)

1.一种具有多层内联线结构的复合高密度构装基板的形成方法，其特征在于，该基板的形成方法包含：
提供一透光操作基板(Handle Substrate)；
形成一粘性光分解介电层于该操作基板上；
形成一多层内联线结构于该粘性光分解介电层上，该多层内联线结构的表面具有数个焊垫；
提供一载台基板(Carrier Substrate)，该载台基板设有突出表面的数个导体；
提供一图案化的粘性结合膜，其中若该粘性结合膜形成于该多层内联线结构上，则暴露出该多层内联线结构表面的该数个焊垫，若该粘性结合膜形成于该载台基板表面，则暴露出该载台基板表面的该数个导体；
由焊接分别结合该数个焊垫与该载台基板上的该数个导体，以结合该多层内联线结构与该载台基板；
分解该粘性光分解介电层；
移除该操作基板；及
移除该粘性光分解介电层。
2.如权利要求1所述的基板的形成方法，其特征在于，上述的该操作基板为石英基板及玻璃基板之一。
3.如权利要求1所述的基板的形成方法，其特征在于，上述的该粘性光分解介电层包含一离形膜。
4.如权利要求1所述的基板的形成方法，其特征在于，上述的该多层内联线结构以薄膜晶体管液晶显示器(TFT-LCD)技术的沉积、微影与蚀刻制程形成。
5.如权利要求1所述的基板的形成方法，其特征在于，上述的该粘性结合膜可为一半固化膜(Semi-Cured Film)。
6.如权利要求1所述的基板的形成方法，其特征在于，上述的该载台基板可为一印刷电路板。
7.如权利要求1所述的基板的形成方法，其特征在于，上述的该导体可为焊膏(Solder Paste)、金属凸块(Metal Bump)、表面镀着金属(Metal Surface Coating)其中之一。
8.如权利要求1所述的基板的形成方法，其特征在于，上述的该粘性光分解介电层以激光束及紫外线其中之一分解。
9.如权利要求1所述的基板的形成方法，其特征在于，上述的该粘性光分解介电层以蚀刻法移除。
10.如权利要求1所述的基板的形成方法，其特征在于，上述的该多层内联线结构中内嵌有至少一被动组件。
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WO2017072737A1 (en) * 2015-10-30 2017-05-04 At&S (China) Co. Ltd. Component carrier with alternatingly vertically stacked layer structures of different electric density

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CN103943600A (zh) * 2013-06-07 2014-07-23 珠海越亚封装基板技术股份有限公司 在芯片和基板之间的新型端接和连接
TWI637672B (zh) * 2013-06-07 2018-10-01 珠海越亞封裝基板技術股份有限公司 在芯片和基板之間的新型端接和連接
WO2017072737A1 (en) * 2015-10-30 2017-05-04 At&S (China) Co. Ltd. Component carrier with alternatingly vertically stacked layer structures of different electric density
US10834831B2 (en) 2015-10-30 2020-11-10 At&S (China) Co. Ltd. Component carrier with alternatingly vertically stacked layer structures of different electric density

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