CN1404114A - local forming process of self-aligning metal silicide - Google Patents
local forming process of self-aligning metal silicide Download PDFInfo
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- CN1404114A CN1404114A CN 01132658 CN01132658A CN1404114A CN 1404114 A CN1404114 A CN 1404114A CN 01132658 CN01132658 CN 01132658 CN 01132658 A CN01132658 A CN 01132658A CN 1404114 A CN1404114 A CN 1404114A
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Abstract
The present invention is one method of forming self-aligning metal silicide, especially is one method of forming self-aligning metal silicide in local area. One layer of silicon mask is used, so that self-aligning metal silicide can be formed locally on logic circuit. In the crystal cell array area, metal silicide is formed on the gate only, and there is no metal silicide in the diffusion area. In the peripheral circuit area, metal silicide may be formed in both gate pole and diffusion area. The method of the present invention makes it possible to obtain relatively low resistance in the semiconductor element while resulting in less defect of producing leakage current.
Description
Technical field
The present invention relates to a kind of method that forms self-aligned metal silicate, particularly relevant a kind of method that forms self-aligned metal silicate in the subregion.
Background technology
Integrated level (integrity) increase when element, make the resistance of the source/drain (source/drain) of metal-oxide-semiconductor transistor element, rise to resistance with metal-oxide-semiconductor transistor element passage (channel) gradually when suitable, for the sheet resistor (sheet resistance) that downgrades source/drain, and guarantee shallow joint the (shallow junction) complete between metal and MOS (metal-oxide-semiconductor) transistor, the application of a kind of being called " aimed at metal silicide (self-aligned silicide) " voluntarily processing procedure just enters 0.5 micron (micron gradually; μ m) Yi Xia ultra-large type integrated circuit (very large scale integration; VLSI) processing procedure.Therefore this processing procedure abbreviates self-aligned metal silicate (salicide) processing procedure again as.
General the most frequently used metal silicide is when first-elected Titanium silicide.Two stage Fast Heating processing procedure (rapid thermal process are generally all adopted in the formation of Titanium silicide; RTP) mode.At first,, provide a silicon base material 10, on ground 10, formed MOS (metal-oxide-semiconductor) transistor and shallow trench separator 30 with reference to shown in Figure 1.This MOS (metal-oxide-semiconductor) transistor has source/drain 12, gate and forms clearance wall (spacer) 18 at the sidewall of gate, and this gate comprises gate oxide layer 14 and polysilicon layer 16 at least, then with chemical vapour deposition technique (chemical vapor deposition; CMP) or magnetic control direct current sputtering method (direct currentmagnetron sputtering) deposition one deck titanium coating 20 on ground 10, the thickness of this titanium coating 20 is approximately 300 dusts.Next, carry out the first Fast Heating processing procedure, make the silicon layer reaction of titanium and contact position, to form Titanium silicide, its thickness is greatly between 600 to 700 dusts.The structure of the Titanium silicide of this moment mainly is the structure of the higher C-49 phase of resistance value.With reference to shown in Figure 2, the mode of utilizing RCA to clean remove have neither part nor lot in reaction or reaction back residual titanium, and titanium-silicon compound layer 22 is stayed on MOS (metal-oxide-semiconductor) transistor the most surperficial.This have neither part nor lot in reaction or reaction back residual titanium to may not be certain must be that form with titanium stays.Carry out the second Fast Heating processing procedure at last again, the Titanium silicide Structure Conversion of C-49 phase is become the structure of the lower C-54 phase of resistance value.
In the processing procedure of deep-sub-micrometer element, the transistor drive current decline that causes for fear of the source/drain parasitic series resistance, to source/drain in addition silicidation be to be an important and process technique that widely use.This can be by simple source/drain silicidation, or realizes by aiming at the metal silicide processing procedure voluntarily.Aim at the metal silicide processing procedure voluntarily and can finish the silicidation of source/drain and gate simultaneously.
On present logical circuit, also need to use metal silicide with resistance that reduces conducting shell and the quality that increases semiconductor element.But, on logical circuit, there is the zone of part can not form metal silicide, to prevent the defective of semiconductor element generation leakage current in order to be engaged in the running of logical circuit.And traditional self-aligned metal silicate processing procedure if will form metal silicide on the part material, then must could form metal silicide through quite complicated program on required zone.Utilize traditional method local metal silicide that forms on logical circuit apace, in the manufacture of semiconductor of stressing efficient at present, tradition step comparatively consuming time can't cooperate present manufacture of semiconductor, must utilization can quicken the method for processing procedure efficiency of operating.
Summary of the invention
The main purpose of the present invention provides a kind of local method that forms self-aligned metal silicate, to utilize the formed mask layer of a silicon layer, gate on peripheral circuit area and unit cell arrays zone and the diffusion zone on the peripheral circuit area form metal silicide smoothly, to reduce the resistance of unit cell arrays zone by the character line (word line) of peripheral circuit area.
Second purpose of the present invention provides a kind of local method that forms self-aligned metal silicate, to utilize the formed mask layer of a silicon layer, gate on peripheral circuit area and unit cell arrays zone and the diffusion zone on the peripheral circuit area form metal silicide smoothly, to avoid the defective of the diffusion zone generation leakage current on the unit cell arrays zone.
The 3rd purpose of the present invention provides a kind of local method that forms self-aligned metal silicate, to utilize the formed mask layer of a silicon layer, gate on peripheral circuit area and unit cell arrays zone and the diffusion zone on the peripheral circuit area form metal silicide smoothly, to reduce the resistance on the peripheral circuit area.
The 4th purpose of the present invention provides a kind of local method that forms self-aligned metal silicate, to utilize the formed mask layer of a silicon layer, gate on peripheral circuit area and unit cell arrays zone and the diffusion zone on the peripheral circuit area form metal silicide smoothly, to improve the quality of semiconductor element.
A further object of the present invention provides a kind of local method that forms self-aligned metal silicate, to utilize the formed mask layer of a silicon layer, gate on peripheral circuit area and unit cell arrays zone and the diffusion zone on the peripheral circuit area form metal silicide smoothly, to improve the processing procedure operational paradigm of semiconductor element.
According to above-described purpose, of the present inventionly form the method for a self-aligned metal silicate at a regional area, be characterized in may further comprise the steps at least: a wafer is provided, and described wafer comprises a ground at least; Form one first oxide skin(coating) on described ground; Form the mononitride layer on described first oxide skin(coating); Form one second oxide skin(coating) on described nitride layer; Described second oxide skin(coating), nitride layer and first oxide skin(coating) that remove part expose described ground with the first area at described wafer; Form a trioxide layer on the described ground of described first area; Form a silicon layer on described second oxide skin(coating) and described trioxide layer; The described silicon layer that removes part is to form several first gates and several first diffusion zones on described first area, described several first diffusion zones are positioned at a side of described several first gates; Form a clearance wall on a sidewall of described several first gates and described silicon layer; Implant an ion in described several first diffusion zones, to form one source pole/drain zone; Form a metal level on described several first gates, described several first diffusion zones and described silicon layer; Carry out a Fast Heating processing procedure on described several first gates, described several first diffusion zones and described silicon layer, to form a metal silicide layer; Remove described metal level; And the described metal silicide layer that removes the described silicon layer of part and part is to form several second gates and several second diffusion zones on a second area of described wafer.
Adopt such scheme of the present invention, owing to utilize the formed mask layer of a silicon layer, smoothly gate on peripheral circuit area and unit cell arrays zone and the diffusion zone on the peripheral circuit area form metal silicide, with the resistance of the character line of reduction unit cell arrays zone and peripheral circuit area and avoid the defective of the diffusion zone generation leakage current on the unit cell arrays zone.Method of the present invention also can reduce the resistance on the peripheral circuit area.Method of the present invention more can improve the quality of semiconductor element and improve the processing procedure operational paradigm of semiconductor element.
For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 deposits the schematic diagram of a titanium coating on MOS (metal-oxide-semiconductor) transistor for the utilization conventional art;
Fig. 2 forms the schematic diagram of Titanium silicide on gate zone and source/drain areas for the utilization conventional art;
Fig. 3 forms the schematic diagram of first oxide skin(coating), nitride layer and second oxide skin(coating) on the wafer ground for the present invention;
Fig. 4 removes the schematic diagram of first oxide skin(coating), nitride layer and second oxide skin(coating) of peripheral circuit area for the present invention;
Fig. 5 forms the schematic diagram of a trioxide layer on the ground of peripheral circuit area for the present invention;
Fig. 6 forms the schematic diagram of a silicon layer on second oxide skin(coating) and trioxide layer for the present invention;
Fig. 7 forms several first gates and several first diffusion regions for the present invention at peripheral circuit area, and forms the schematic diagram of light dope drain in several first diffusion regions;
Fig. 8 forms the schematic diagram of clearance wall on the sidewall of the silicon layer on the unit cell arrays zone and several first gates for the present invention;
Fig. 9 forms the schematic diagram of source/drain in several first diffusion regions for the present invention;
Figure 10 forms the schematic diagram of a metal level on the silicon layer on the unit cell arrays zone, several first gates and several first diffusion regions for the present invention;
Figure 11 forms the schematic diagram of metallic silicon compounds layer on the silicon layer on the unit cell arrays zone, several first gates and several first diffusion regions for the present invention; And
Figure 12 forms the schematic diagram of several second gates and several second diffusion zones on second oxide skin(coating) for the present invention.
Embodiment
Below preferred embodiment of the present invention is described in detail.Yet except describing in detail, the present invention can also be widely with other embodiment execution, and described embodiment limits scope of the present invention, and scope of the present invention is to be as the criterion with accompanying Claim.
Logical circuit mainly is to be connected the semiconductor element on the logical circuit by character line (word line) with bit line (bit line).The purpose of character line is for limiting the position of signal, and the purpose of bit line then is the type of decision signal, so character line is connected to the gate of semiconductor element, and the bit line is connected to the source/drain on the semiconductor element.For character line, it needs higher transmission speed transmission data, therefore must utilize method of the present invention to form a metal silicide on the gate of character line and semiconductor element, to reduce the resistance of character line, improves the transmission speed of character line.
Mainly divide into two big zones on the logical circuit, a zone wherein is the unit cell arrays zone, and another zone then is a peripheral circuit area.The function in unit cell arrays zone is a storage data, and the pattern of data with electric charge is stored in the storage unit of unit cell arrays.The function of peripheral circuit area for conduction and operational data, by the element in the peripheral circuit area, similarly is elements such as adder or subtracter then, and the data of required processing are handled, and handles the back and causes other zones by the peripheral circuit conduction.Therefore the element in unit cell arrays zone must be independent of individually to prevent the loss because of the data that defective is caused of short circuit.The element of peripheral circuit area then must link mutually, to accelerate processing speed of data.So must use mode of the present invention, on gate on the peripheral circuit area and diffusion zone, form metal silicide, gate on the unit cell arrays zone forms metal silicide simultaneously, and avoid metal silicide to be formed at diffusion zone on the unit cell arrays zone, accelerating data transmission capabilities and the data operation ability of peripheral circuit area, and prevent the phenomenon of unit cell arrays zone generation leakage current and cause the loss of data.
With reference to shown in Figure 3, at first provide one to comprise the wafer of ground 100 and on ground 100, form one first oxide skin(coating) 120, next on this first oxide skin(coating) 120, form mononitride layer 140, on this first nitride layer 140, form one second oxide skin(coating) 160 at last.Usually the thickness of this first oxide skin(coating) 120 is about 70 to 90 dusts, and the thickness of nitride layer 140 is about 60 to 80 dusts, and the thickness of second oxide skin(coating) 160 is approximately 60 to 80 dusts.Usually adopting the thickness of first oxide skin(coating) 120 in present processing procedure is 80 dusts, and the thickness of nitride layer 140 is 70 dusts, and the thickness of second oxide skin(coating) 160 then is 70 dusts.But along with the processing procedure width day by day dwindles, the thickness of first oxide skin(coating) 120, nitride layer 140 and second oxide skin(coating) 160 also must be along with dwindling, to meet the demand on the processing procedure.
With reference to shown in Figure 4, next after limiting unit cell arrays zone 104 and peripheral circuit area 102 on the wafer, mode by a little shadow (photolithography) and etching (etching) removes first oxide skin(coating) 120, first nitride layer 140 and second oxide skin(coating) 160 on the peripheral circuit area 102, makes peripheral circuit area 102 expose ground.With reference to shown in Figure 5, on the ground of peripheral circuit area 102, form a trioxide layer 200, the thickness of this trioxide layer 200 is about 40 to 60 dusts, and in present processing procedure, the thickness of trioxide layer 200 is generally 50 dusts.But along with the processing procedure width day by day dwindles, the thickness of trioxide layer 200 also must be along with dwindling, to meet the demand on the processing procedure.The material of common first oxide skin(coating) 120, second oxide skin(coating) 160 and trioxide layer 200 is silicon dioxide (silieon dioxide), and the material of nitride layer 140 is generally silicon nitride (silicon nitride).
In the present embodiment, multi-form dielectric layer is adopted with peripheral circuit area in the zone of the unit cell arrays on the wafer on ground.On the unit cell arrays zone, adopt the formed dielectric layer of sandwich form of oxide/nitride/oxide, then adopt the formed dielectric layer of single one deck oxide at peripheral circuit area.Along with the difference of process requirement, on ground, also can adopt the usefulness of the dielectric layer of same form with peripheral circuit area with the performance semiconductor element in the unit cell arrays zone.This dielectric layer can be the monoxide layer.
With reference to shown in Figure 6, form a silicon layer 300 on second oxide skin(coating) 160 and trioxide layer 200, this silicon layer 300 is a gate layer.With reference to shown in Figure 7, next on peripheral circuit area 102, limit the position of gate, and remove part silicon layer on the peripheral circuit area 102 by a little shadow and etched processing procedure, to form several first gates 400 and several first diffusion regions 450 on peripheral circuit area 102, these several first diffusion region 450 is positioned at the both sides of several first gates 400.Next carry out light dope drain (lightly doped drain; LDD) processing procedure is to form a slight drain zone 320 of mixing in several first diffusion regions 450.The purpose of this processing procedure is in order to reduce the defective that hot carrier effect (hot carrier effects) is caused.
With reference to shown in Figure 8, behind the processing procedure that carries out the light dope drain, on the silicon layer 300 on second oxide skin(coating) 160, the unit cell arrays zone 104, several first gates 400 and several first diffusion regions 450, form a gap parietal layer, and by a little shadow and etched processing procedure on the sidewall of the silicon layer on the unit cell arrays zone 104 300 and several first gates 400, to form clearance wall 500.
With reference to shown in Figure 9, limit the position of the gate/drain on the peripheral circuit area 102 after, required ion on the implantation process is with formation source/drain 550 several first diffusion regions 450 in.With reference to shown in Figure 10, form a metal level 600 on the silicon layer on the unit cell arrays zone 104 300, several first gates 400 and several first diffusion regions 450, before depositing metal layers 800, use the oxide on wet-cleaning method removing silicon layer 300 and the substrate at first earlier, make metal silicide more easily form.Major part uses chemical vapour deposition technique or magnetic control direct current sputtering method deposits this metal level 600.Next, wafer sent into carry out the first Fast Heating processing procedure in the reative cell, make the pasc reaction of metal level 600 and contact position, to form metal silicide (metal silicide) layer.The temperature of the first Fast Heating processing procedure is approximately 500 to 700 ℃.The structure of the metal silicide of this moment mainly is the structure of the higher C-49 phase of resistance value.With reference to shown in Figure 11, the mode of utilizing RCA to clean removes and has neither part nor lot in reaction or reaction back institute metal remained layer 600, and metallic silicon compounds layer 620 is stayed on silicon layer 300 on the unit cell arrays zone 104, several first gates 400 and several first diffusion regions 450.Carry out the second Fast Heating processing procedure at last again, the metal suicide structure of C-49 phase is converted to the structure of the lower C-54 phase of resistance value.The temperature of the second Fast Heating processing procedure is approximately 750 to 850 ℃.The material of this metal level 600 can be titanium, cobalt and platinum etc., uses the titanium material of metal level 600 for this reason usually.In order to cooperate the demand of processing procedure, before 600 layers of plated metals, can remove the trioxide layer 200 on several first diffusion regions sometimes, to improve the quality of semiconductor element.
Titanium is the metal material of normal use in the present self-aligned metal silicate processing procedure.Under suitable temperature, titanium very easily with MOS (metal-oxide-semiconductor) transistor on drain/source electrode and the silicon on the gate form the very low titanium-silicon compound of a resistivity (titanium silicide because of mutual diffusion; TiSi
2).
In the processing procedure of self-aligned metal silicate, the silicon layer on the brilliant bag array region is a mask layer, can avoid metal silicide to be formed on second oxide skin(coating) 160.With reference to shown in Figure 12, after finishing the processing procedure of self-aligned metal silicate, limit the gate position on the unit cell arrays zone 104, and remove silicon layer 300 on the part unit cell arrays via a little shadow and etched processing procedure, on second oxide skin(coating) 160, to form several second gates 700 and several second diffusion zones 750.These several second diffusion region 750 is positioned at the both sides of several first gates 700.During the etch process of the silicon layer on removing the part unit cell arrays, etch process can stop at second oxide skin(coating) 160, nitride layer 140 or first oxide skin(coating) 120.
According to above-described embodiment, the invention provides a method, utilize the formed mask layer of a silicon layer, successfully gate on peripheral circuit area and unit cell arrays zone and the diffusion region on the peripheral circuit area form metal silicide, with the resistance of the character line that reduces the unit cell arrays zone and avoid the defective of the diffusion zone generation leakage current on the unit cell arrays zone.The present invention also can reduce the resistance on the peripheral circuit area.The present invention also can improve the quality of semiconductor element and improve the processing procedure operational paradigm of semiconductor element.
The above only is preferred embodiment of the present invention, this embodiment only be used for the explanation but not in order to limit scope of the present invention.Still can be changed in the category that does not break away from flesh and blood of the present invention and implemented, these variations should still belong to scope of the present invention.Therefore, scope of the present invention is defined by following claims.
Claims (10)
1. one kind forms the method for a self-aligned metal silicate at a regional area, it is characterized in that comprising at least:
One wafer is provided, and described wafer comprises a ground at least;
Form one first oxide skin(coating) on described ground;
Form the mononitride layer on described first oxide skin(coating);
Form one second oxide skin(coating) on described nitride layer;
Described second oxide skin(coating), nitride layer and first oxide skin(coating) that remove part expose described ground with the first area at described wafer;
Form a trioxide layer on the described ground of described first area;
Form a silicon layer on described second oxide skin(coating) and described trioxide layer;
The described silicon layer that removes part is to form several first gates and several first diffusion zones on described first area, described several first diffusion zones are positioned at a side of described several first gates;
Form a clearance wall on a sidewall of described several first gates and described silicon layer;
Implant an ion in described several first diffusion zones, to form one source pole/drain zone;
Form a metal level on described several first gates, described several first diffusion zones and described silicon layer;
Carry out a Fast Heating processing procedure on described several first gates, described several first diffusion zones and described silicon layer, to form a metal silicide layer;
Remove described metal level; And
The described metal silicide layer that removes described silicon layer of part and part is to form several second gates and several second diffusion zones on a second area of described wafer.
2. the method for claim 1 is characterized in that, the material of described metal level is a titanium.
3. the method for claim 1 is characterized in that, the material of described metal level is a cobalt.
4. the method for claim 1 is characterized in that, the material of described metal level is a platinum.
5. the method for claim 1 is characterized in that, described first area is a peripheral circuit area.
6. the method for claim 1 is characterized in that, described second area is a unit cell arrays zone.
7. the method in regional area formation self-aligned metal silicate is characterized in that, comprises at least:
One wafer is provided, and described wafer comprises a ground at least;
Form one first oxide skin(coating) on described ground;
Form the mononitride layer on described first oxide skin(coating);
Form one second oxide skin(coating) on described nitride layer;
Described second oxide skin(coating), nitride layer and first oxide skin(coating) that remove part expose described ground with the first area at described wafer;
Form a trioxide layer on the described ground of described first area;
Form a silicon layer on described second oxide skin(coating) and described trioxide layer;
The described silicon layer that removes part is to form several first gates and several first diffusion zones on described first area, described several first diffusion zones are positioned at a side of described several first gates;
Form a light dope drain in described several first diffusion regions;
Form the sidewall of a clearance wall in described several first gates and described silicon layer;
Implant an ion in described several first diffusion zones, to form one source pole/drain zone;
Form a metal level on described several first gates, described several first diffusion zones and described silicon layer;
Carry out one first Fast Heating processing procedure on described several first gates, described several first diffusion zones and described silicon layer, to form a metal silicide layer;
Remove described metal level and carry out one second Fast Heating processing procedure; And
The described metal silicide layer that removes described silicon layer of part and part is to form several second gates and several second diffusion zones on a second area of described wafer.
8.. method as claimed in claim 7 is characterized in that, the material of described metal level is a titanium.
9. method as claimed in claim 7 is characterized in that, described first area is a peripheral circuit area.
10. method as claimed in claim 7 is characterized in that, described second area is a unit cell arrays zone.
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| CNB011326581A CN1159751C (en) | 2001-09-05 | 2001-09-05 | Local forming process of self-aligning metal silicide |
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| CNB011326581A CN1159751C (en) | 2001-09-05 | 2001-09-05 | Local forming process of self-aligning metal silicide |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7754545B2 (en) | 2007-12-03 | 2010-07-13 | Macronix International Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN101005094B (en) * | 2006-12-21 | 2011-05-25 | 上海集成电路研发中心有限公司 | Novel metal oxide silicon field effect transistor grid structure and its preparing process |
| CN106158656A (en) * | 2015-04-20 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101043007B (en) * | 2006-12-21 | 2012-06-06 | 上海集成电路研发中心有限公司 | Preparing technique for metallic oxide silicon field-effect transistor |
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2001
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101005094B (en) * | 2006-12-21 | 2011-05-25 | 上海集成电路研发中心有限公司 | Novel metal oxide silicon field effect transistor grid structure and its preparing process |
| US7754545B2 (en) | 2007-12-03 | 2010-07-13 | Macronix International Co., Ltd. | Semiconductor device and method of fabricating the same |
| TWI398932B (en) * | 2007-12-03 | 2013-06-11 | Macronix Int Co Ltd | Semiconductor device and method of fabricating the same |
| CN106158656A (en) * | 2015-04-20 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
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| CN1159751C (en) | 2004-07-28 |
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