CN101043007B

CN101043007B - Preparing technique for metallic oxide silicon field-effect transistor

Info

Publication number: CN101043007B
Application number: CN200610147716XA
Authority: CN
Inventors: 胡恒升
Original assignee: Shanghai Integrated Circuit Research and Development Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd
Priority date: 2006-12-21
Filing date: 2006-12-21
Publication date: 2012-06-06
Anticipated expiration: 2026-12-21
Also published as: CN101043007A

Abstract

The invention discloses a novel MOSFET preparation craftwork, it adjusts the forming of whole transistor greatly, the channel adjustment is injected to where it is needed, the generation of gate oxidation layer is only in specific area, not whole underlay source area, the working procedure of damp corrosion is decreased, the quality of craftwork is increased, but also the cost is decreased; polysillicon is corroded to form hollow structure, and the bridging phenomenon during the forming of silicide is resolved. Besides, the side wall protects the gate oxidation layer from corrosion and increases the reliability of the oxidation layer. By adjusting the side wall craftwork, the superposition area of LDD and HDD can be controlled to provide space for adjustment of transistor, the generation of silicide in source and drain area can be adjusted by side wall craftwaork, so the junction leakage is decreased. It also provides craftwork selection for optimizing property of apparatus.

Description

A kind of preparing technique for metallic oxide silicon field-effect transistor

Technical field

The invention belongs to the integrated circuit fabrication process field, be specifically related to form the transistorized preparation technology of MOSFET (metal-oxide semiconductor fieldeffect transistor).

Background technology

The fast development of integrated circuit makes electronic technology obtain to popularize rapidly, forms huge industry size.The main body of integrated circuit technique is the MOSFET integrated circuit at present, and the work of MOSFET be unable to do without the formation of grid, source electrode, drain electrode.These electrodes will be worked, and not only need inject through ion and obtain highly doped and activate these impurity with annealing, and need define corresponding zone and non-electrode zone is made effective isolation.The size of electrode effective coverage belongs to the row of minimum feature in the design rule.Outstanding feature that integrated circuit is fast-developing or major obstacle are exactly size constantly the dwindling of grid size especially of transistor design rule definition; This proposes very high requirement to etching, deposit especially photoetching process, and the traditional optical exposure technique has approached physics limit at present.In order to satisfy the requirement that transistor size constantly dwindles; People are doing a lot of trials aspect technology and the device architecture; Photoetching technique and many three-dimension device structures that exploitation makes new advances different MOS technological processes occurred, but total trend all are the complexity that has increased technology greatly.

Summary of the invention

The object of the present invention is to provide a kind of novel MOSFET preparation,, make that characteristics of transistor obtains to promote to improve the formation quality of silicide.

Technical scheme one of the present invention comprises the steps:

1) on the basis of original silicon chip, form the STI shallow groove isolation structure through photoetching, etching and filling, the active region area of definition transistor in silicon chip, as shown in Figure 1;

2) CVD deposit one deck medium one (oxide layer) is on the silicon chip of plane, and this oxidated layer thickness is 70-500nm, can determine the height of MOSFET grid, and is as shown in Figure 2;

3) pass through the effective coverage that photoetching process defines the polysilicon gate of deposit in the future;

4) through etching technics, medium one (oxide layer) is etched into the silicon wafer-based surface, remove photoresist, silicon chip is cleaned, the width of bottom has determined transistorized physics channel length, and is as shown in Figure 3;

5) no mask carries out the channel doping injection, and is as shown in Figure 4;

6) growth gate oxide 1-10nm is as shown in Figure 5;

7) deposit polysilicon, polysilicon thickness fills up groove greater than gash depth, and is as shown in Figure 6;

8) through etch-back technics or CMP technology, the polysilicon that groove is outer is removed, and is parked on medium one (oxide layer) surface, and is as shown in Figure 7;

9) through photoetching the polysilicon exposed is come out, plasma etching or directly surperficial polysilicon is eroded a part again with etch-back technics, corrosion thickness is 5-30nm, removes photoresist then, and is as shown in Figure 8;

10) carry out photoetching, the side wall zone that definition need stay, as shown in Figure 9;

11) choose the solution that medium one (oxide layer) is had corrosiveness, perhaps use plasma etching to carry out selective etch, remove the above oxide layer of silicon chip surface, stay polysilicon and sidewall structure, carry out low-doped drain LDD then and inject, shown in figure 10;

12) carry out heavy dose of injection of source and drain areas and mix, if polysilicon does not mix, simultaneously polysilicon is mixed, remove photoresist, activated at mixes then, and is shown in figure 11;

13) the LOCSAL oxide layer of deposit 15-30nm, as the mask of part formation silicide, shown in figure 12;

14) definition LOCSAL forms the zone, and is shown in figure 13;

15) plasma etching LOCSAL oxide layer is removed photoresist behind silicon chip surface;

16) clean after, depositing metal like Ti, Co, Ni, is convenient to form silicide, and is shown in figure 15;

17) carry out the RTP rapid thermal treatment, selective etch forms silicide, is Ni to depositing metal, and then RTP once more is shown in figure 16;

18) accomplish custom integrated circuit operation subsequently, form contact hole, metal level and inter-level dielectric.Technical scheme two may further comprise the steps:

6) growth gate oxide 1-10nm is as shown in Figure 5;

12) deposit one deck medium two silicon nitrides (SiN) again, thickness is 30-50nm, shown in Figure 11 (I);

13) through etch-back technics, medium two is etched into silicon chip substrate, shown in Figure 12 (I);

14) carry out heavy dose of injection of source and drain areas and mix, if polysilicon does not mix, simultaneously polysilicon is mixed, remove photoresist, activated at mixes then, shown in Figure 13 (I);

15) the LOCSAL oxide layer of deposit 15-30nm is as the mask of part formation silicide;

16) definition LOCSAL forms the zone, shown in Figure 15 (I);

17) plasma etching LOCSAL oxide layer is removed photoresist behind silicon chip surface, shown in Figure 16 (I);

18) clean after, depositing metal is convenient to form silicide, like Ti, Co, Ni, shown in Figure 17 (I);

19) carry out the RTP rapid thermal treatment, selective etch forms silicide, shown in Figure 18 (I), is Ni to depositing metal, then RTP once more;

20) accomplish custom integrated circuit operation subsequently, form contact hole, metal level and inter-level dielectric.

In the technical scheme one, two the 9th) step can omit as required.Technical scheme two needs to consider the etching selection property between medium (14) and the LOCSAL oxide (11).

Technical scheme three comprises the steps:

6) growth gate oxide 1-10nm is as shown in Figure 5;

9) through wet method or dry method selective etch medium one (oxide layer) is removed, up to stopping at silicon chip (1) surface, and carried out low-doped drain LDD and inject, shown in Fig. 8 (II);

10) medium three silicon dioxide (SiO2) that deposit one deck 15-20nm is thick, (silicon nitride (SiN) is shown in Fig. 9 (II) for the medium four that deposit one deck 25-50nm is thick again;

11) eat-back, form grid curb wall, shown in Figure 10 (II);

12) carry out heavy dose of injection of source and drain areas and mix, if polysilicon does not mix, simultaneously polysilicon is mixed, remove photoresist, activated at mixes then;

13) the LOCSAL oxide layer of deposit 15-30nm is as the mask of part formation silicide;

14) definition LOCSAL forms the zone;

16) clean after, depositing metal is convenient to form silicide;

17) carry out the RTP rapid thermal treatment, selective etch forms silicide, shown in Figure 18 (II), if depositing metal is Ni, and RTP once more then;

18) accomplish custom integrated circuit operation subsequently, form contact hole, metal level and inter-level dielectric.

Medium one described in above-mentioned three kinds of schemes can be in following five kinds of media selection-silicon nitride, carborundum, silicon oxynitride, silica, silicon oxide carbide; Used silicon chip contains CZ sheet, FZ sheet, epitaxial wafer and soi wafer; It can be Ti, Co or Ni that the formation silicide needs metals deposited.

Medium two described in above-mentioned second kind of technical scheme can select-one of silicon nitride, carborundum, silicon oxynitride, silica and silicon oxide carbide, and medium one, medium two can be the same or different;

The described medium of above-mentioned the third scheme three, medium four can select-one of silicon nitride, carborundum, silicon oxynitride, silica and silicon oxide carbide, and medium three is different with medium four.

The invention has the beneficial effects as follows: propose a kind of new MOSFET preparation technology; Bigger corresponding improvement has been made in traditional technological process; Polysilicon gate is through filling and CMP or eat-back and be formed in the groove that etching is good in advance; Forming groove only needs a kind of medium, is removed or become the part of side wall subsequently, and the height of grid is by this dielectric thickness decision; Raceway groove is regulated to inject and can only be injected into the place that needs injection, and the technogenic influence of prior art is to the entire substrate active area; Growth of gate oxide layer also only occurs in the specific region, rather than the entire substrate active area, makes the wet etching operation be able to reduce, and not only improves processing quality but also reduce the technology cost; The side wall protection gate oxide is not influenced by etching to have improved the oxide layer reliability; Because the bridging phenomenon (bridging) when the grid groove has been avoided silicidation reaction; Through adjusting to side wall technology, can control the coincidence district between LDD and the HDD, regulating for transistor provides the space; Silicide also can pass through the side wall process adjustments in the growth of source-drain area, has reduced junction leakage; The LOCSAL oxide layer can become the part of side wall, has reduced the deposit number of times of medium after grid forms.Therefore the present invention has promoted some processing performances effectively, for regulating transistor performance very big state space is provided simultaneously.Improved the formation quality of silicide through process modification, made that characteristics of transistor has obtained greatly promoting.

Description of drawings

Fig. 1 is the sketch map after silicon chip forms STI (shallow-trench isolation);

Fig. 2 is the sketch map behind silicon chip surface deposit one deck medium monoxide;

Fig. 3 applies photoresist, etches into the sketch map of substrate surface after the exposure;

Fig. 4 carries out raceway groove to regulate the sketch map that injects;

Fig. 5 is the sketch map behind the growth gate oxide;

Fig. 6 is the sketch map of CVD deposit polysilicon;

Fig. 7 be polysilicon CMP or eat-back after sketch map;

Fig. 8 is the sketch map that further eat-backs or be with the glue plasma etching to form to be lower than the polysilicon surface of side wall;

Fig. 9 is the sketch map of definition LDD injection region figure after the photoetching;

Figure 10 carries out the sketch map that wide-angle LDD injects after etching into substrate;

Figure 11 is for carry out the sketch map that low-angle HDD injects subsequently;

Figure 12 is the sketch map after the deposit LOCSAL oxide layer;

Figure 13 prepares to carry out the sketch map of LOCSAL etching for photoetching, notices that area of grid is for eat-backing the zone;

Figure 14 is the transistor area sketch map that forms after removing photoresist;

Figure 15 forms the sketch map of the required metal of silicide for deposit;

Figure 16 is through the sketch map behind the formation silicide behind the RTP;

Figure 11 (I) is the sketch map of deposit one deck medium two (SiN) again after scheme two LDD inject;

Figure 12 (I) is after scheme two is eat-back (etchback), etches into the sketch map of substrate surface;

Figure 13 (I) carries out the sketch map that low-angle HDD injects for scheme two;

Figure 14 (I) is the sketch map after the scheme two deposit LOCSAL oxide layers;

Figure 15 (I) is the sketch map that scheme two photoetching prepare to carry out the LOCSAL etching, notices that area of grid is for eat-backing the zone;

Figure 16 (I) is the transistor area sketch map that forms after scheme two is removed photoresist;

Figure 17 (I) is scheme two forms the required metal of silicide for deposit a sketch map;

Figure 18 (I) is the sketch map after scheme two process RTP form silicide;

Fig. 8 (II) forms the sketch map that carries out wide-angle LDD injection behind the polysilicon gate for scheme three;

Fig. 9 (II) is that scheme three deposits form the required SiO2 of side wall, the sketch map after the SiN two layer medium;

Figure 10 (II) is the sketch map after scheme three etchings form side wall;

Figure 18 (II) adopts the sketch map of traditional M OS technological process formation behind the silicide for scheme three in Fig. 9 (II) back;

Scheme three is from the 11st) to be scheme one corresponding steps identical for flow process after the step, and sketch map is consistent with conventional process flow, so do not draw specially.

Label among the figure: 1 is silicon chip, and 2 is the STI isolation structure, and 3 is the medium one (oxide layer) on the silicon chip, and 4 is photoresist; 5 for ion injects, and 6 are raceway groove modulation injection zone, and 7 is gate oxide (SiO2), and 8 is (doping) polysilicon; 9 is the LDD injection region, and 10 is the HDD injection zone, and 11 is the LOCSAL oxide layer, and 12 for forming the required metal of silicide; 13 is silicide, and 14 is medium two (SiN), and 15 is medium three (SiO2), and 16 is medium four (SiN).

Present embodiment has only been illustrated a transistorized forming process, and like NMOS, another kind of transistorized forming process like PMOS, only need be added several roads mask and can realize, need only change a little sketch map to get final product.When the injection mask is medium, can regrows and also can adopt the remaining medium of etching.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the present invention is elaborated.

Present embodiment is an example to form NMOS:

The 1st) step on the basis of p type silicon chip 1, forms STI (shallow-trench isolation) structure 2 through photoetching, etching and filling like Fig. 1, and active region is the silicon chip part in the middle of the shallow slot structure.

The 2nd) go on foot like Fig. 2, medium one oxide layer 3 (oxide) of PECVD deposit 200nm thickness, thickness of oxide layer can determine the height of grid.

The 3rd) the 4th) step defines the polysilicon gate effective coverage that width is 0.18um (just illustrated groove width is 0.18um) like Fig. 3 through photoetching process.Through etching technics, etch into apart from silicon chip surface 10nm, remove photoresist 4, silicon chip 1 is cleaned, the width of silicon chip bottom has determined transistorized physics channel length, the mask of the oxide layer oxide of this 10nm for injecting.

The 5th) go on foot like Fig. 4, no mask carries out channel doping and injects, and forms channel doping injection zone 6, and it is boron (B) that injection is doped to ion, and energy is 35keV, and dosage is 1E13/cm2, and 6 is raceway groove modulation injection zone.

The 6th) go on foot like Fig. 5, growth gate oxide 7, thickness is 4nm.

The 7th) go on foot like Fig. 6, deposit 350nm polysilicon 8, and fill up groove.

The 8th) step, removes the polysilicon outside the groove, and is parked on the oxide layer 3 through CMP technology like Fig. 7.

The 9th) step directly erodes 20nm with etch-back technics with surperficial polysilicon like Fig. 8, makes it to lower recess, removes photoresist then.

The 10th) step is carried out photoetching (photoresist is 4 among the figure), the side wall part that definition will stay like Fig. 9.

The 11st) step uses plasma etching to carry out selective etch like Figure 10, removes the above oxide layer of silicon chip surface, stopping apart from silicon chip 1 surperficial 10nm place, stays the part of the oxide layer 3 of 40nm, forms sidewall.Carry out LDD (low-doped drain 9) then and inject, arsenic (As), energy are 30keV, and dosage is 3E14/cm2, and implant angle is 27 degree or bigger.The 12nd) step is carried out the heavy dose of HDD (highly doped drain electrode 10) of injection of source and drain areas (S/D) like Figure 11,

The energy of arsenic (As) is 70keV, and dosage is 4E15/cm2, and angle is 7 degree.

The 13rd) go on foot like Figure 12, the oxide layer 11 of CVD deposit 45nm is as the mask (LOCSAL) of part formation silicide.

The 14th) step defines LOCSAL and forms the zone like Figure 13.4 block the oxide layer zone that does not need etching, i.e. masks area with photoresist.

The 15th) go on foot like Figure 14, the zone that plasma etching is not blocked by photoresist, and remove photoresist after etching into substrate.

The 16th) step is like Figure 15, after silicon chip cleans, and deposited metal 12, depositing metal is Ti and Co, thickness is distinguished and can be 8 and 15nm.Under the metal Ti metal Co is arranged, Co preferential reaction, and Ti does not react, so the Ti does not here participate in forming silicide, such as common practise knowledge, the Ti here does top cover layer usefulness shown in Fig. 9 (II),

The 17th) step is carried out 540C/60s rapid thermal treatment (RTP) like Figure 16, and selective etch carries out the 850C/30s rapid thermal annealing again and forms CoSi2 silicide 13.

Custom integrated circuit operation is subsequently accomplished in final step, forms contact hole, metal level and inter-level dielectric.

From scheme one the 12nd) step beginning, also can take following steps:

The 12nd) step, deposit one deck medium 2 14 silicon nitride SiN again, thickness is 30-50nm, shown in Figure 11 (I);

The 13rd) step etches into base substrate with medium two, shown in Figure 12 (I) through etch-back technics;

The 14th) step is carried out heavy dose of inject (HDD) of source and drain areas (S/D), simultaneously polysilicon is mixed, and the energy of arsenic (As) is 70keV, and dosage is 4E15/cm2, and angle is 7 degree.Remove photoresist, activated at then is shown in Figure 13 (I);

The 15th) step deposit oxide15-30nm is as the mask (LOCSAL) of part formation silicide, shown in Figure 14 (I);

The 16th) step definition LOCSAL forms the zone, shown in Figure 15 (I);

The 17th) go on foot plasma etching and behind substrate, remove photoresist, shown in Figure 16 (I)

The 18th) after the step cleans, deposited metal 12, depositing metal is Ti and Co, thickness respectively can be 8 and 15nm.Shown in Figure 17 (I);

The 19th) step is carried out 540C/60s rapid thermal treatment (RTP), and selective etch carries out the 850C/30s rapid thermal annealing again and forms CoSi2 silicide 13.Shown in Figure 18 (I).

Final step is then identical with scheme one, accomplishes custom integrated circuit operation subsequently, forms contact hole, metal level and inter-level dielectric.

In addition, the 9th of scheme one the) to 11) step replaceable be following steps:

The 9th) step, through wet method or dry method selective etch oxide layer 3 is removed, up to stopping at silicon chip surface, and carry out low-doped drain LDD and inject, shown in Fig. 8 (II)

The 10th) step, the medium 3 15 (SiO2) behind deposit one deck 15-20nm, the medium 4 16 (SiN) that deposit one deck 25-50nm is thick again is shown in Fig. 9 (II);

The 11st) in the step, eat-back, form grid curb wall, shown in Figure 10 (II).

And scheme one is all identical in other steps of this scheme and the present embodiment, but the because the 9th) to 11) difference in step, the silicide sketch map that generates at last is Figure 18 (II).

Claims

1. MOSFET preparation technology is characterized in that may further comprise the steps:

1) on the basis of original silicon chip (1), forms STI shallow-trench isolation (2) structure through photoetching, etching and filling, the active region area of definition transistor in silicon chip;

2) CVD deposit one deck medium one (3) oxide layer is on plane silicon chip (1), and this oxidated layer thickness is 70-500nm, the height of decision MOSFET grid;

4) through etching technics, medium one (3) oxide layer is etched into the silicon wafer-based surface, remove photoresist, silicon chip is cleaned, the width of bottom has determined transistorized physics channel length;

5) no mask carries out the channel doping injection, forms channel doping injection zone (6);

6) growth gate oxide (7) 1-10nm;

7) deposit polysilicon (8), polysilicon thickness fills up groove greater than gash depth;

8) through etch-back technics or CMP technology, the polysilicon that groove is outer is removed, and is parked on medium one (3) the oxide layer surface;

9) through photoetching the polysilicon exposed is come out, plasma etching or directly surperficial polysilicon is eroded a part again with etch-back technics, corrosion thickness is 5-30nm, removes photoresist then;

10) carry out photoetching, the side wall zone that definition need stay;

11) choose the solution that medium one (3) oxide layer is had corrosiveness, perhaps use plasma etching to carry out selective etch, remove the above oxide layer in silicon chip (1) surface, stay polysilicon and sidewall structure, carry out low-doped drain (9) then and inject;

12) carry out heavy dose of injection of source and drain areas and mix (10), if polysilicon does not mix, simultaneously polysilicon (8) is mixed, remove photoresist, activated at mixes then;

13) the LOCSAL oxide layer (11) of deposit 15-30nm is as the mask of part formation silicide;

14) definition LOCSAL forms the zone;

15) plasma etching LOCSAL oxide layer (11) is removed photoresist behind silicon chip surface;

16) clean after, depositing metal (12) is convenient to form silicide;

17) carry out the RTP rapid thermal treatment, selective etch forms silicide (13), is Ni to depositing metal, then RTP once more;

2. MOSFET preparation technology is characterized in that may further comprise the steps:

6) growth gate oxide (7) 1-10nm;

10) carry out photoetching, the side wall zone that definition need stay;

12) deposit one deck medium two (14) silicon nitrides (SiN) again, thickness is 30-50nm;

13) through etch-back technics, medium two (14) is etched into silicon chip (1) substrate;

14) carry out heavy dose of injection of source and drain areas and mix (10), if polysilicon does not mix, simultaneously polysilicon (8) is mixed, remove photoresist, activated at mixes then;

15) the LOCSAL oxide layer (11) of deposit 15-30nm is as the mask of part formation silicide;

16) definition LOCSAL forms the zone;

17) plasma etching LOCSAL oxide layer (11) is removed photoresist behind silicon chip surface;

18) clean after, depositing metal (12) is convenient to form silicide;

19) carry out the RTP rapid thermal treatment, selective etch forms silicide (13), is Ni to depositing metal, then RTP once more;

3. MOSFET preparation technology is characterized in that may further comprise the steps:

6) growth gate oxide (7) 1-10nm;

9) through wet method or dry method selective etch medium one (3) oxide layer is removed,, carried out low-doped drain then and inject up to stopping at silicon chip (1) surface;

10) medium three (15) silicon dioxide (SiO2) that deposit one deck 15-20nm is thick, medium four (16) silicon nitrides (SiN) that deposit one deck 25-50nm is thick again;

11) eat-back, form grid curb wall;

14) definition LOCSAL forms the zone;

16) clean after, depositing metal (12) is convenient to form silicide;

17) carry out the RTP rapid thermal treatment, selective etch forms silicide (13), if depositing metal is Ni, and RTP once more then;

4. like claim 2 or 3 described MOSFET preparation technologies, it is characterized in that the polysilicon surface that finally forms silicide is lower than side wall.

5. like claim 1,2 or 3 described MOSFET preparation technologies, it is characterized in that medium one (3) selection-silicon oxynitride, silica, silicon oxide carbide in following three kinds of media.

6. like claim 1,2 or 3 described MOSFET preparation technologies, it is characterized in that medium one (3) adopts silicon nitride or carborundum replacement oxide layer.

7. the MOSFET preparation technology who states like claim 2 it is characterized in that one of medium two (14) selection-carborundum, silicon oxynitride, silica or silicon oxide carbide replacement silicon nitride, and medium one (3), medium two (14) is identical.

8. the MOSFET preparation technology who states like claim 2 is characterized in that one of medium two (14) selection-carborundum, silicon oxynitride, silica or silicon oxide carbide replacement silicon nitride, and medium one (3), medium two (14) differences.

9. MOSFET preparation technology as claimed in claim 3; It is characterized in that one of medium three (15) selection-silicon nitrides, carborundum, silicon oxynitride or silicon oxide carbide replacement silicon dioxide; One of medium four (16) selection-carborundum, silicon oxynitride, silica or silicon oxide carbide replacement silicon nitride, and medium three (15) is different with medium four (16).

10. like claim 1,2 or 3 described MOSFET preparation technologies, it is characterized in that used silicon chip (1) contains CZ sheet, FZ sheet, epitaxial wafer and soi wafer.

11. like claim 1,2 or 3 described MOSFET preparation technologies, it is characterized in that forming silicide, to need metals deposited be Ti, Co or Ni.