CN1402436A - Link code A/D converter - Google Patents
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- CN1402436A CN1402436A CN 02128314 CN02128314A CN1402436A CN 1402436 A CN1402436 A CN 1402436A CN 02128314 CN02128314 CN 02128314 CN 02128314 A CN02128314 A CN 02128314A CN 1402436 A CN1402436 A CN 1402436A
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Abstract
The formation of the Link-Chain A/D converter is simplar to the Flash A/D converter. But, under the condition of the same resolution N, the amount of the voltage comparator in the structure of Link-Chain A/D converter is no more than half of the amount of the voltage comparator in the Flash A/D converter. The Link-Chain A/D converter possesses the features of not need of complex encoders, simple structure, regualr arrangement, a great variety of combination with the peripheral circuits as well as easy of transferring the output signal. The Link-Chain A/D converter can be made of the discrete components or IC chips. The invented converter supports a variety of sensors, providing and advantages of the high speed, and good anti-interference ability of the directive digitized sensor.
Description
Technical field the invention belongs to electronic technology field, and a kind of analog to digital converter that is output as serial loop chain code digital signal based on Link-Chain Code coding principle design, the work of similar parallel relatively pattern number converter (Flash ADC) is provided.
In the technical background digital application of electronic technology, analog-digital converter is very crucial device.At present in the various high speed analog-digital converters that provided by manufacturer, parallel relatively pattern number converter Flash ADC is fastest transducer.The principle of this device is fairly simple: resistor voltage divider network forms 2 in the structure
N-1 Voltage Reference amount, analog input amount (voltage) compare with all reference quantity simultaneously, (contain overflow position totally 2 by comparator array
NIndividual comparator) obtains corresponding comparative result logical value, via coder processes output binary digital signal.In the structure of Flash ADC transducer, used voltage comparator quantity and its resolution, N are exponential relationship, be operated in high-speed transitions, the higher state of power consumption again, because of lead-in wire complicated in input end capacitor and the encoder etc., make under present fabrication process condition, the integrated level of device and resolution (are generally 6～8, be up to 10) be difficult to improve, also limit Flash ADC converter performance such as dynamic error, signal to noise ratio (S/N) and number of significant digit parameters such as (ENOB) and realized its ideal value.
The present invention is intended to reduce effectively number of comparators in the comparator array, overcome the above-mentioned drawback that causes thus, a kind of new-type parallel relatively pattern number converter is provided, have under the same resolution, N condition, number of comparators at most only for the FlashADC converter half, need not numerous and jumbled encoder, the simple in structure and rule of arranging, be convenient to integrated on a large scale, as to be convenient to export teletransmission serial loop chain code digital signal ADC converter.Summary of the invention the invention provides link code A/D converter (accompanying drawing 4) for achieving the above object, and it comprises when resolution is N: divider resistance array 14, and by being no more than 2
N-1+ 1 resistance that resistance is specific, serial connection forms linear array mutually, inserts canonical reference voltage unipolarity V
REFOr bipolarity ± V
REFThe time, the serial connection point is drawn and is no more than 2
N-1Individual voltage reference points; Voltage comparator array 15 comprises maximum 2
N-1Individual comparator is docile and obedient preface one input end (negative or positive) is connected the correspondent voltage reference point, and its another input is interconnected with one another, and constitutes the input end of analog signal Input of link code A/D converter; Logic is selected data output circuit 16, is that order is a pair of with adjacent two comparators, with one two input " with " gate is connected this output to comparator, maximum 2
N-2 Individual diode 19 grades connect AND gate with DOL Data Output Line 18, make 2
N-2Individual " with " gate to data output line 18 form each other " or " relation, DOL Data Output Line 18 constitutes link code A/D converter data output end Out via shaping circuit 20 output.Be furnished with the supply voltage that guarantees operate as normal, form whole link code A/D converter (Link-Chain ADC) thus.
The present invention by the requirement of conversion resolution N, selects a corresponding suitable collection code vector of surveying of analog signal full scale range (FRS) according to the Link-Chain Code coding principle
, rank Δ X is a transverse axis unit with amount, with
Middle code element c
iPut in order, draw code element c
iCorresponding " 1 ", level "0" obtain surveying the collection code vector
Pulse sequence diagram (accompanying drawing 1).
Determine the quantification datum mark 1 of corresponding zero level in the pulse sequence diagram, for making quantization error within [0.5LSB, 0.5LSB], datum mark should be at the mid point (0.5 Δ X place) of the amount rank Δ X that a certain code element occupies.When FRS was the bipolarity conversion, datum mark 1 was defined in
" 0 " code element place of the transverse axis of pulse sequence diagram (range) mid point; When FRS was unipolarity, datum mark 1 was defined in null value pairing " 0 " the code element place that sequence chart begins.Follow FRS on the occasion of being the positive polarity direction from datum mark 1; Otherwise follow the FRS negative value is the negative polarity direction.
The divider resistance array 14 of link code A/D converter of the present invention is according to surveying the collection code vector
Pulse sequence diagram is by being no more than 2
N-1+ 1 resistance constitutes divider resistance array (accompanying drawing 2) by following rule:
1. just (bear) polar orientation from datum mark 1 edge, run into porch 2 and to array first resistor 5 is set, its resistance is (m
i+ 0.5) R (R is a unit resistance), m
iFor running into before porch or the FRS border 4, walk the number on excessive rank or walked the number of code element.First resistor 5 one ends connect the zero-potential point GND of reference voltage, the other end be follow-up resistor be connected in series a little 6.
For the explanation circuit connects, the point that is connected in series (with the point of extraction voltage reference) is distinguished: all rising edge of a pulses 2 etc. that runs into, insert tie point 6 grades that form after the resistor and be called " going up point ", its tie point ordinal number is an odd number: run into pulse trailing edge 3 etc., insert tie point 7 grades that form behind the resistor and be called " following point ", its tie point ordinal number is an even number.
2. continue to follow polar orientation, arrive porch whenever, at the tie point 6 or 7,8 of last series resistor device ... Deng resistor of continued access, its resistance is m
i *R (m
iMeaning the same), the other end of the new resistor that inserts be again follow-up resistor be connected in series a little 7,8 ...
3. arrive FRS boundary value 4 points at last, the tail resistors 9 of serial connection array, its resistance is (m
i+ 0.5) R, (m
iMeaning the same), tail resistors 9 other ends are the incoming end ± V that connect the link code A/D converter reference voltage in the array
REFThe feature of divider resistance array 14 is: based on the selected survey collection code vector of range
The pulse sequence diagram of being drawn (accompanying drawing 1) is complied with 3 rules of divider resistance array 14 explanations of above-mentioned link code A/D converter, the divider resistance array of formation (accompanying drawing 2); After array inserts canonical reference voltage, disregard-V
REFOr zero reaching+V
REFPotential point is no more than 2 from being connected in series a little can draw
N-1Individual voltage reference points; First resistor 5 and tail resistors 9 resistance values are (m in the array
i+ 0.5) R (R is a unit resistance), the resistance of the resistor of other serial connection is m
i *R, m
iFor running into before porch and the FRS border 4, walk the number on excessive rank or walked the number of code element.
The voltage comparator of the voltage comparator array 15 of link code A/D converter of the present invention will be connected, arrange by following rule with divider resistance array 14:
1. be connected in series a little 6 from first resistor 5, select single output voltage comparator (accompanying drawing 3) for use: when positive polarity, with the tie point ordinal number is that the comparator 11 (B1) that is connected of " go up point " of odd number etc. is its negative input end, is that the comparator 12 (B2) that is connected of " the following point " of even number etc. is its positive input terminal with the tie point ordinal number; During negative polarity, being that the comparator 11 (B1 ') that is connected of " go up point " of odd number etc. is its positive input terminal with the tie point ordinal number, is that the comparator (B2 ') that is connected of " the following point " of even number etc. is its negative input end with the tie point ordinal number; If voltage comparator selects the complementary output type for use, and be connected different (accompanying drawing 4) that is connected in series a little: when positive polarity, all with voltage comparator 11 (B1), negative input end and the tie point 6,7 of 12 (B2) etc. ... be connected; During negative polarity, all with positive input terminal and the tie point 6,7 of voltage comparator 11 (B1 ') and (B2 ') etc. ... be connected.
For the explanation circuit connects, title connection tie point 6 ordinal numbers such as grade are that the comparator of odd number is called strange ordinal number comparator 11 etc., and connection tie point 7 ordinal numbers such as grade are that the comparator of even number is called even ordinal number comparator 12 etc.
2. another input that does not insert tie point of all voltage comparators all couples together with lead, draws the input 17 of analog signal to be converted.
Voltage comparator array 15 is characterised in that: no matter select single output voltage comparator for use or select the voltage comparator of complementary output for use, the array that is constituted comprises 2 at most
N-1Individual voltage comparator; Two of each comparator inputs and " going up point " of divider resistance array or being connected of " following point " and input end of analog signal in the array are by 2 rule decisions of voltage comparator array 15 explanations of above-mentioned link code A/D converter.
The logic of link code A/D converter of the present invention is selected the composition of data output circuit 16, be to follow polar orientation, begun to connect by the output than device 11, it is a pair of 10 that adjacent in twos strange, even comparator is formed, as adjacent two comparators 11 (B1) and 12 (B2) as a pair of.When selecting single output voltage comparator for use, their outputs of 10 connect one two input " with " gate 13; When selecting complementary output voltage comparator (accompanying drawing 4) for use, the negative logic output terminal of the positive logic output terminal of strange ordinal number comparator 11 (B1) etc., even ordinal number comparator 12 (B2) etc., respectively with " with " two inputs of gate 13 are connected.AND gate 13 outputs insert diode 19 and are connected to DOL Data Output Line 18.DOL Data Output Line 18 is divided into two, and one is connected with reference voltage zero-potential point GND with diode 22 parallel connections by resistor 23; Another causes the input of shaping circuit 20 DOL Data Output Line 18, and shaping circuit output constitutes the data output end Out of link code A/D converter; The earth terminal of link code A/D converter power supply is connected with reference voltage zero-potential point GND, is thus connected and a little draws the earth terminal GND that connects outside link code A/D converter.
Logic selects data output circuit 16 to be characterised in that: in the voltage comparator array, adjacent strange ordinal number comparator and even ordinal number comparator form a pair of 10.If the comparator of single output, two outputs that this is a pair of, with " with " two inputs of gate are connected; If the comparator of complementary output, the positive logic output terminal of strange ordinal number comparator, the negative logic output terminal of even ordinal number comparator, connect respectively " with " two inputs of gate; Have 2 at most
N-2Individual AND gate by diode 19 grades be connected to DOL Data Output Line 18 form " or " logical relation; DOL Data Output Line 18 will connect the input of shaping circuit 20 as Schmidt trigger, and the shaping circuit output constitutes link code A/D converter data output end Out.
Link code A/D converter of the present invention is made up of 14,15,16 described parts, related resistor, comparator, trigger, gate etc., and its notion had both comprised the function of its definition, also comprised all components and parts of extension that can finish specific function.Therefore, link code A/D converter of the present invention both can have been connected by discrete single components and parts and realize, also can be realized by the semiconductor integrated circuit chip technology.Link code A/D converter of the present invention is characterised in that: when realizing with discrete component, need design and produce according to the link code A/D converter integrated circuit figure (as accompanying drawing 5) that embodies 14,15,16 each several part features and print version; When realizing with the ic core chip technology, the materialization boundary of components and parts can disappear in the described whole composition, finish the composition of specific function and can simplify, integrate, but its logic function still exists; For the resolution, N link code A/D converter, insert normal working voltage and canonical reference voltage after, when input end of analog signal Input adds by-V
REFOr 0 to+V
REFLINEAR CONTINUOUS evenly increase progressively (slope) voltage the time, data output end Out obtains the digital signal level figure, the N position Link-Chain Code that resolution, N is down corresponding is surveyed the collection code vector just
Pulse sequence diagram.
Description of drawings accompanying drawing of the present invention and being described as follows:
The Link-Chain Code of Fig. 1 full scale range correspondence is surveyed the collection code vector
Pulse sequence diagram
Fig. 2 link code A/D converter divider resistance array connection layout
Fig. 3 link code A/D converter list output voltage comparator array connection layout
Fig. 4 link code A/D converter complementary output voltage comparator array connection layout
Four link code A/D converter embodiment of Fig. 5 circuit diagram
Embodiment embodiment of the invention accompanying drawings is as follows: present embodiment is four link code A/D converters, is welded on to print on the version by discrete electronic devices and components to form.Tested voltage range FRS is positive polarity [0,3V], and selected Link-Chain Code is surveyed the collection code vector
Be by primitive polynomial P (x)=X
4+ X+1 generates (the generation method is referring to document " application of Link-Chain Code in location detecting technology ", and sensor technology was rolled up the phase in 1999 the 18th), surveys the collection code vector
The pulse sequence diagram of drawing is seen Fig. 1 (N=4 positive polarity).
Resistor 5,9 in the embodiment divider resistance array 14 ..., select that temperature coefficient is little, high stability metal membranous type RJ25 composes in series, unit resistance resistance R=1k Ω for use.Insert canonical reference voltage V
REFAfter, require each tie point 6,7 ..., the error of reference voltage less than ± 1%, so select for use the resistance accuracy of resistor should ± 0.5%, resembling first resistor 5 grades, to be in the electric resistance array tie point ordinal number forward, more should accurately measure, screen.Electric resistance array is 0.5,4,1,1,1,2,2,1 from first resistor 5 to tail resistors 9 resistances successively, 3.5k Ω.
In the voltage comparator array 15 of embodiment, voltage comparator 11,12 ..., that select for use is high speed complementation output voltage comparator J760, its response time＜25n8 and highly sensitive, input imbalance deviation voltage＜1mV.Because the output circuit of single output voltage comparator is fairly simple on internal structure, for verifying the validity of using single output voltage comparator to arrange in the integrated comparator array, here complementary output voltage comparator J760 is used as single output voltage comparator and uses, only use its positive logic output terminal.
The logical device that the logic of embodiment selects data output circuit 16 to select for use: two input AND gates, Schmidt trigger belong to 74HCT cmos digital circuit, and the conduction delay time is not more than 20nS.Diode 19 grades that are connected to DOL Data Output Line 18 are selected 1N4009 for use.Shaping circuit 20 be two independently the schmidt trigger unit be in series from beginning to end.The resistor 22 that inserts between DOL Data Output Line 18 and GND is selected 1N4009 for use for RJ25 resistance 10k, diode 21.
Four link code A/D converters of embodiment are through breadboardin, steady operation when cooperating sampling-retainer (S/H) of sampling rate 30MHz, the sampled analog signal voltage that inserts input is changed accurate, the good in anti-interference performance of output serial loop chain code digital signal.If implement with semiconductor integrated chip technology,, the technical parameter of this link code A/D converter (Link-Chain ADC) is further improved by optimal design.With parallel relatively pattern number conversion (Flash ADC) device relatively, Link-Chain ADC is cooperating various transducers to form the Direct Digital sensings, comes more simple and directly, cost is low, realizes that the data acquisition remote installed meter reveals remarkable advantages.
Claims (6)
1. link code A/D converter based on Link-Chain Code coding principle design.It comprises when resolution is N: 1. divider resistance array, and by being no more than 2
N-1+ 1 resistance that resistance is specific is connected in series the linear array that forms mutually.Inserting reference voltage unipolarity V
REFOr bipolarity ± V
REFThe time, the serial connection point is drawn and is no more than 2 between resistance
N-1Individual voltage reference points; 2. the voltage comparator array comprises 2 at most
N-1Individual comparator is docile and obedient preface one input end (negative or positive) is connected the correspondent voltage reference point, and its another input is interconnected with one another, and constitutes the input end of analog signal Input of link code A/D converter; 3. logic is selected data output circuit, is that order is will adjacent two comparators composition a pair of, with one two input " with,, gate connects this output to comparator, uses 2 at most
N-2Individual diode connects the AND gate output with DOL Data Output Line, make 2
N-2Individual " with " the gate output form each other " or " relation, DOL Data Output Line is exported by shaping circuit, constitutes link code A/D converter data output end Out.Be furnished with the supply voltage that guarantees operate as normal, form link code A/D converter (Link-Chain ADC) thus.
2. link code A/D converter according to claim 1 is the requirement by conversion resolution N, selects corresponding one of analog signal full scale range (FRS) suitably to survey the collection code vector
, by surveying the collection code vector
Pulse sequence diagram launches design.It is characterized in that: to the link code A/D converter of resolution, N, insert normal working voltage and canonical reference voltage after, when input end of analog signal Input adds from-V
REFOr 0 to+V
REFLINEAR CONTINUOUS evenly increase progressively (slope) voltage the time, data output end Out obtains the digital signal level figure, the N position Link-Chain Code that resolution, N is down corresponding is surveyed the collection code vector just
Pulse sequence diagram.
3. link code A/D converter according to claim 1, its resistor related in forming, comparator, trigger, gate etc., its notion had both comprised defined function, also comprised all components and parts of extension that can finish specific function.It is characterized in that: when realizing with known discrete component, the printing version that need design and produce by the link code A/D converter circuit diagram; When realizing with the ic core chip technology, the materialization boundary of components and parts can disappear in the described whole composition, finish the composition of specific function and can simplify, integrate, but its logic function still exists.
4. the divider resistance array of link code A/D converter according to claim 1 is by being no more than 2
N-1+ 1 resistance that resistance is specific, serial connection forms array mutually.It is characterized in that: after array inserts canonical reference voltage, disregard ± V
REFAnd zero-potential point, be no more than 2 from being connected in series a little can draw
N-1Individual voltage reference points; First resistor and tail resistors resistance value are (m in the array
i+ 0.5)
*R (R is a unit resistance), the resistance of the resistor of other serial connection is m
i *R, m
iFor running into before porch and the positive and negative FRS border, walk the number on excessive rank or walked the number of code element.
5. the voltage comparator array of link code A/D converter according to claim 1 is by comprising 2 at most
N-1Individual voltage comparator is formed.It is characterized in that: if select single output type voltage comparator for use, when positive polarity, being that comparator is its negative input end in the array that is connected of the voltage reference points of odd number with ordinal number, is that the comparator that the voltage reference points of even number is connected is its positive input terminal with ordinal number; During negative polarity, being that the comparator that the voltage reference points of odd number is connected is its positive input terminal with ordinal number, is that the comparator that the voltage reference points of even number is connected is its negative input end with ordinal number.If voltage comparator selects the complementary output type for use, be connected in series a little be connected different: when the positive polarity, the negative input end of voltage comparator is connected with voltage reference points; During negative polarity, the positive input terminal of voltage comparator is connected with voltage reference points.Another input that does not insert voltage reference points of all voltage comparators all couples together with lead, draws the input Input of link code A/D converter analog signal.
6. the logic of link code A/D converter is selected data output circuit according to claim 1, be characterised in that: in the voltage comparator array, adjacent strange ordinal number comparator and even ordinal number comparator are formed a pair of, if the comparator of single output, two outputs that this is a pair of, should with " with " two inputs of gate are connected; If the comparator of complementary output, the positive logic output terminal of strange ordinal number comparator, the negative logic output terminal of even ordinal number comparator, connect respectively " with " two inputs of gate; Have 2 at most
N-2Individual AND gate is connected to DOL Data Output Line by diode, make the AND gate output form each other " or " logical relation; DOL Data Output Line will connect the input of shaping circuit such as Schmidt trigger, and the shaping circuit output constitutes the data output end Out of link code A/D converter.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02128314 CN1203615C (en) | 2002-07-30 | 2002-07-30 | Link code A/D converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02128314 CN1203615C (en) | 2002-07-30 | 2002-07-30 | Link code A/D converter |
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|---|---|
| CN1402436A true CN1402436A (en) | 2003-03-12 |
| CN1203615C CN1203615C (en) | 2005-05-25 |
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|---|---|---|---|
| CN 02128314 Expired - Fee Related CN1203615C (en) | 2002-07-30 | 2002-07-30 | Link code A/D converter |
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| CN1567726B (en) * | 2003-06-13 | 2010-04-14 | 陈启星 | Displacing type A/D and D/A converter with optimized signal to noise ratio |
| CN101051841B (en) * | 2007-02-06 | 2010-08-25 | 复旦大学 | Window type parallel modulus converter suitable for digital power controller |
| CN101286742B (en) * | 2007-04-11 | 2011-09-07 | 联发科技股份有限公司 | Analog-digital converter,analog-digital conversion system, data reading system and its related method |
| CN102427367A (en) * | 2010-11-09 | 2012-04-25 | 微软公司 | Resolution enhancing analog-to-digital conversion |
| US8223881B2 (en) | 2004-10-27 | 2012-07-17 | Sennheiser Electronic Gmbh & Co. Kg | Transmitter and receiver for a wireless audio transmission system |
| CN103532557A (en) * | 2013-11-05 | 2014-01-22 | 吴小刚 | All-parallel analog-digital converter of VCO (voltage-controlled oscillator)-based comparators |
| CN101594148B (en) * | 2008-05-30 | 2014-04-23 | 深圳艾科创新微电子有限公司 | Flash ADC with current inserted structure |
| CN103023500B (en) * | 2011-09-22 | 2016-01-20 | 株式会社东芝 | Analog to digital converter |
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| CN106685421A (en) * | 2016-12-15 | 2017-05-17 | 北京万集科技股份有限公司 | Method and device for acquiring analog signals |
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| CN1567726B (en) * | 2003-06-13 | 2010-04-14 | 陈启星 | Displacing type A/D and D/A converter with optimized signal to noise ratio |
| US8223881B2 (en) | 2004-10-27 | 2012-07-17 | Sennheiser Electronic Gmbh & Co. Kg | Transmitter and receiver for a wireless audio transmission system |
| CN101051841B (en) * | 2007-02-06 | 2010-08-25 | 复旦大学 | Window type parallel modulus converter suitable for digital power controller |
| CN101286742B (en) * | 2007-04-11 | 2011-09-07 | 联发科技股份有限公司 | Analog-digital converter,analog-digital conversion system, data reading system and its related method |
| CN102324938A (en) * | 2007-04-11 | 2012-01-18 | 联发科技股份有限公司 | Analog digital converter, analog-to-digital conversion system, data reading system and correlated method |
| CN102324938B (en) * | 2007-04-11 | 2014-06-04 | 联发科技股份有限公司 | Analog digital converter, analog-to-digital conversion system, data reading system and correlated method |
| CN101594148B (en) * | 2008-05-30 | 2014-04-23 | 深圳艾科创新微电子有限公司 | Flash ADC with current inserted structure |
| CN102427367A (en) * | 2010-11-09 | 2012-04-25 | 微软公司 | Resolution enhancing analog-to-digital conversion |
| CN102427367B (en) * | 2010-11-09 | 2013-06-19 | 微软公司 | Resolution enhancing analog-to-digital conversion |
| CN103023500B (en) * | 2011-09-22 | 2016-01-20 | 株式会社东芝 | Analog to digital converter |
| CN103532557A (en) * | 2013-11-05 | 2014-01-22 | 吴小刚 | All-parallel analog-digital converter of VCO (voltage-controlled oscillator)-based comparators |
| CN103532557B (en) * | 2013-11-05 | 2016-09-07 | 吴小刚 | A kind of all-parallel A/D converter of comparator based on voltage controlled oscillator |
| CN106052593A (en) * | 2015-04-03 | 2016-10-26 | 株式会社三丰 | Phase adjuster and encoder |
| CN106052593B (en) * | 2015-04-03 | 2020-05-01 | 株式会社三丰 | Phase adjuster and encoder |
| CN106685421A (en) * | 2016-12-15 | 2017-05-17 | 北京万集科技股份有限公司 | Method and device for acquiring analog signals |
| CN106685421B (en) * | 2016-12-15 | 2019-12-10 | 北京万集科技股份有限公司 | Analog signal acquisition method and device |
| CN109547025A (en) * | 2018-11-20 | 2019-03-29 | 恒通旺达(深圳)科技有限公司 | A kind of quick D conversion method and analog-digital converter |
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