CN1400737A - Phase compensation circuit for data phase-locked loop - Google Patents
Phase compensation circuit for data phase-locked loop Download PDFInfo
- Publication number
- CN1400737A CN1400737A CN 01123551 CN01123551A CN1400737A CN 1400737 A CN1400737 A CN 1400737A CN 01123551 CN01123551 CN 01123551 CN 01123551 A CN01123551 A CN 01123551A CN 1400737 A CN1400737 A CN 1400737A
- Authority
- CN
- China
- Prior art keywords
- circuit
- phase
- absolute value
- abs
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Thin invention provides a phase compensation circuit used in digital phase lock loop (DPLL) especially used in the DPLL with quadrature amplitude modulation (QAM) as the demodulatory way with the character of high efficiency and low hardware cost used in solving the problem of phase deviation of the received signal resulted by timing drift in demodulation including a first absolute circuit, a second absolute value circuit, an addition circuit, a subs-traction circuit, a weight circuit and a multiplication circuit.
Description
Technical field
The invention relates to a kind of phase compensating circuit that is applied to the data phase-locked loop.
Background technology
Known application in the data phase-locked loop with demodulation techniques in, because the deviation of far-end oscillator frequency and local oscillator frequencies, make the sampling generation timing off-set phenomenon (timing shift) of received signal, the rotation that causes signal to produce phase place on frequency domain causes the locking phase demodulation to become quite difficult.
With asymmetric data user loop (Asymmetric Digital Subscriber Line, ADSL) technology is an example, time sequence information is taken time sequence information with 4-QAM mode modulation one guiding musical note (pilot.tone) deliver to terminating machine (ATU-R) end by central control room (ATU-C) end.Fig. 1 is data phase-locked loop (the Digital Phase lock loop of known difference form, DOLL) 10, in order to reply this time sequence information, when the sequential of ATU-R end is not held fully synchronously with ATU-C as yet, differential phase discriminator (Differential Phase Discriminator) 100 input will have the phenomenon of phase place deflection, shown in Fig. 2 A, B.When near synchronously the time, this digital baseband input signal can level off to zero, but because the quantization error that fixed-point calculation (fixed-point numerical operations) causes also can cause the phase place deflection of trace, this micro-phase place deflection can't be detected by differential discriminator, therefore it is output as zero, and no longer adjusts the frequency of local oscillator, after after a while, this trace phase place deflection builds up, and then causes synchronization failure.
In traditional solution, time-domain signal sampling skew computing is used to compensate timing drift, the method is proposed (to see IEEEInternational Conference on Communications SUPERCOMM/ICC ' 94 for details in one piece of paper " Timing Recovery forEcho-Cancelled Discrete Multitone Systems " by Minnie Ho and John M.Cioffi, Vol.1, pp.307～310,1994.) identical notion also is used in people's such as L.Kiss the paper " SACHEM; a Versatile DMT-Based Modem Transceiver for ADSL " and (sees IEEE Journal of Solid-State Circuits for details, Vol.34, NO.7, July1999.).This sample skew in time domain can cause in frequency domain the phase jitter of musical note (Tone) (phase jump) in each channel, and this phase jitter is proportional to the frequency of musical note in each channel.Therefore, a phase compensation circuit various phase jitter situation in all channels of suitably to handle of still needing.
In another solution, the synchronous demodulation of a complexity (Coherent Demodulation) mode is used to directly capture phase information from the guiding musical note.After the guiding musical note that this mode will receive gave normalization (Normalize) earlier, the 4-QAM signal coordinate figure with expection made comparisons again; And another kind of mode is to utilize arc tangent (arch-tangent, tan
-1) computing, the phase angle of the guiding musical note that obtains receiving.Because normalization and arctangent cp cp operation are complicated numerical operation, do not have an efficiency, need a complicated circuit to realize simultaneously, cause the considerable cost of cost on hardware designs.
Summary of the invention
Purpose of the present invention, provide a kind of phase compensating circuit that is applied to the data phase-locked loop, especially for being the data phase-locked loop of demodulation code mode with orthogonal amplitude modulating and changing technology (QAM), the characteristic of this phase compensating circuit tool efficiency and low hardware cost, separate timing in order to solve, causing the problem of the phase place deflection of received signal because of timing drift.
To achieve the object of the present invention, the invention provides a kind of phase compensating circuit that is applied to the data phase-locked loop, it comprises: one first absolute value circuit, one second absolute value circuit, an add circuit, a subtraction circuit, a weighting circuit, a mlultiplying circuit.
Description of drawings
Fig. 1 is the data phase-locked loop of known difference form;
Fig. 2 A, B are the phase place deflection schematic diagrames that shows received signal;
Fig. 3 is a circuit block diagram of the present invention;
Fig. 4 implements specific embodiments of the invention.
Among the figure
Data phase-locked loop 32 add circuits of 10 difference form
100 differential phase discriminators, 33 subtraction circuits
20 2D signal planes, 34 weighting circuits
200 received signals, 35 mlultiplying circuits
201 4-QAM signals, 41 phase compensating circuits
30 first absolute value circuits, 42 phase compensation values
31 second absolute value circuits, 43 voltage-controlled oscillators
Embodiment
In the known demodulation techniques, because the deviation of fortune end oscillator frequency and local oscillator frequencies, make the timing sequence generating drift phenomenon (timing drift) of received signal, cause the locking phase demodulation quite difficulty that becomes.Therefore circuit of the present invention is by producing the deficiency that a phase compensation value remedies known differential phase discriminator, in order to adjust local oscillator frequencies, makes itself and fortune end oscillator synchronization, finally reaches the purpose of locking phase demodulation.This phase compensation value is to be defined as phase place correction term V
kWith weighted factor W
kProduct, phase place correction term V wherein
kDefinition as back:
If the guiding musical note is taken the signal that send and is positioned at 2D signal plane first or third quadrant,
V
k＝abs(Y
k)-abs(X
k)；
If the guiding musical note is taken the signal that send and is positioned at 2D signal plane second or four-quadrant,
V
k＝abs(X
k)-abs(Y
k)。
X wherein
kBe the real part of signal in time k, Y
kThen be the imaginary part of signal in time k, abs is an ABS function.And weighted factor W
kThen define as the back:
W
k＝[abs(X
k)+abs(Y
k)]*S 0≤S≤1
Wherein ratio adjustment factor S is the arbitrary numerical value in interval [0,1], and in actual applications, the best formula that ratio is adjusted factor S is 2
-n, the wherein decision of n value is to get one greater than 0 and less than [abs (X
k)+abs (Y
k)] the numerical value of bit length.In addition, can get abs (X respectively
k) and abs (Y
k) general numerical value (probable value), replace former abs (X
k) value and former abs (Y
k) value, this way not but still have the effect that reaches the object of the invention and does not have the more simple advantage of the circuit design of making.
Fig. 2 A, B are the phase place deflection schematic diagrames that shows received signal.Wherein received signal 200 has departed from the 4-QAM signal 201 of (+1 ,+1) coordinate that is positioned at 2D signal plane 20, makes that the signal that receives is the result of a phase deviation.
The received signal 200 of Fig. 2 A is at the counterclockwise (anti-clockmise) of 4-QAM signal 201, this moment V
kBy definition be calculated as on the occasion of, in order to accelerate local oscillator frequencies, make received signal 200 toward 4-QAM signal 201 convergences; The received signal 200 of Fig. 2 B is at (clockwise) clockwise of 4-QAM signal 201, this moment V
kBe calculated as negative value by definition,, make received signal 200 toward 4-QAM signal 201 convergences, because V in order to slow down local oscillator frequencies
kBe a bigger numerical, therefore must multiply by weighted factor W
kWith the convergence rate of control phase offset correction, V
kWith W
kThe value that multiplies each other i.e. this phase compensation value, uses so that progressively past 4-QAM signal 201 convergences of received signal 200.
Fig. 3 is a circuit block diagram of the present invention.First absolute value circuit 30 is in order to calculate X
kAbsolute value; Second absolute value circuit 31 is in order to calculate Y
kAbsolute value; Add circuit 32 connects the output of first absolute value circuit 30, second absolute value circuit 31, in order to calculate X
kAbsolute value and Y
kBoth sums of absolute value; Subtraction circuit 33 connects the output of first absolute value circuit 30, second absolute value circuit 31, in order to calculate X
kAbsolute value and Y
kBoth poor of absolute value, that is phase place correction term V
kWeighting circuit 34 connects the output of add circuit 32, in order to produce weighted factor W
k, weighted factor W wherein
kBe the output valve of add circuit 32 and the product that ratio is adjusted factor S; Mlultiplying circuit 35 connects weighting circuit 34, and the output of subtraction circuit 33 is in order to calculate weighted factor W
kWith phase place correction term V
kBoth products, that is phase compensation value.
Fig. 4 implements specific embodiments of the invention.Known application is in the differential phase discriminator 100 of DPLL, be in one piece of paper " AFC Tracking Algorithms ", to propose (to see IEEE Transaction on Communications for details by Francis D.Natali, Vol.COM-32, No.8,1984).In the ADSL technology that with 4-QAM is guiding musical note modulation mode, differential phase discriminator 100 is in order to the guiding musical note (pilottone) of detecting after paying upright leaf conversion (FFT) fast, the phase difference variation amount Z of its continuous two symbols (symbol) during week
kDefinition as back:
Z
k＝Im[(X
k+jY
k)(X
k-1-jY
k-1)]
Wherein Im is the computing that obtains the imaginary part of a parameter.DPLL will be according to differential phase difference Z
k, do clock pulse reduction (timing recovery) action.Yet use under real the work in fixed point, differential phase discriminator 100 also can't detect quite small timing drift and to its compensation (compensation), cause DPLL can't reach the purpose of synchronous demodulation.The guiding musical note that receive this moment is subjected to the influence of timing drift, its phase place departs from its tram at the 4-QAM coordinate gradually, shown in Fig. 2 A, B, by implementing phase compensating circuit 41 of the present invention, the phase compensation value 42 that is produced by phase compensating circuit 41 will add to Z
k, in order to should test progressively convergence of the past correct phase position of tone.
When the circuit of Fig. 4 came into operation, phase place deflection phenomenon was obvious, and this moment is mainly by differential phase difference Z
kControl voltage-controlled oscillator 43 is synchronous with the sequential of ATU-C end to reach ATU-R end, when far away, nearly two ends near synchronously the time, differential phase difference Z
kVery little, voltage-controlled oscillator 43 has not been had influence power, but the phase place deflection problem that the timing drift of the small quantity that fixed-point calculation and other factor cause is caused in long period accumulation then remains phase compensation value 42 to be solved, just dominate the output of voltage-controlled oscillators 43 this moment by phase compensation value 42, make the received signal 200 and the phase angle difference of 4-QAM signal 201 level off to 0 gradually, reach the purpose of ATU-C end and ATU-R end true synchronization at last.
Though the present invention with a specific embodiment openly as above; yet it is not in order to limit the present invention; anyly be familiar with the technology personage; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention should be looked the protection range that the accompanying Claim book defined and is as the criterion.
Claims (7)
1. phase compensating circuit that is applied to the data phase-locked loop, especially for being the data phase-locked loop of demodulation code mode with orthogonal amplitude modulating and changing technology (QAM), it comprises:
One first absolute value circuit is in order to calculate the real part X of a frequency-region signal
kAbsolute value abs (X
k);
One second absolute value circuit is in order to calculate the imaginary part Y of this frequency-region signal
kAbsolute value abs (Y
k);
One add circuit connects the output of this first absolute value circuit and this second absolute value circuit, in order to the output valve of calculating this first absolute value circuit and the output valve sum of this second absolute value circuit;
One subtraction circuit connects the output of this first absolute value circuit and this second absolute value circuit, in order to produce a phase place correction term V
k, this phase place correction term V wherein
kBe output valve poor of the output valve of this first absolute value circuit and this second absolute value circuit;
One weighting circuit connects the output of this add circuit, in order to produce a weighted factor W
k, this weighted factor W wherein
kBe the output valve of this add circuit and the product that a ratio is adjusted the factor;
One mlultiplying circuit connects the output of this weighting circuit and this subtraction circuit, and in order to produce a phase compensation value, wherein this phase compensation value is this phase place correction term V
kWith this weighted factor W
kBoth products.
2. phase compensating circuit as claimed in claim 1, wherein the value that calculated of this first absolute value circuit is abs (X
k) general numerical value (probable value), and the value that this second absolute value circuit is calculated is abs (Y
k) general numerical value.
3. phase compensating circuit as claimed in claim 1, wherein this phase place correction term V
kBe defined as follows:
If this frequency-region signal is positioned at first or the third quadrant on 2D signal plane, then:
V
k＝abs(Y
k)-abs(X
k)；
If this frequency-region signal is positioned at second or the four-quadrant on 2D signal plane, then:
V
k＝abs(X
k)-abs(Y
k)；
Wherein abs is an ABS function.
4. phase compensating circuit as claimed in claim 1, wherein this ratio is adjusted arbitrary numerical value that the factor is interval interior [0,1].
5. phase compensating circuit as claimed in claim 4, wherein this ratio adjustment factor is 2
-n, and the decision of n value is to get one greater than 0 and less than [abs (X
k)+abs (Y
k)] the numerical value of bit length.
6. a differential phase discriminator (Differential Phase Discriminator), it has phase compensating circuit as claimed in claim 1 at least.
7. a data phase-locked loop (DPLL), it has phase compensating circuit as claimed in claim 1 at least.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011235519A CN1156981C (en) | 2001-08-01 | 2001-08-01 | Phase compensation circuit for data phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011235519A CN1156981C (en) | 2001-08-01 | 2001-08-01 | Phase compensation circuit for data phase-locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1400737A true CN1400737A (en) | 2003-03-05 |
| CN1156981C CN1156981C (en) | 2004-07-07 |
Family
ID=4665147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011235519A Expired - Fee Related CN1156981C (en) | 2001-08-01 | 2001-08-01 | Phase compensation circuit for data phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1156981C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101208921B (en) * | 2005-06-24 | 2011-01-12 | 松下电器产业株式会社 | Radio receiving apparatus |
| CN103141030A (en) * | 2010-09-30 | 2013-06-05 | 意法爱立信有限公司 | Reference clock sampling digital pll |
| CN103401829A (en) * | 2013-06-26 | 2013-11-20 | 吉林大学 | IQ imbalance compensation method for coherent-light orthogonal frequency division multiplexing (OFDM) communication system |
-
2001
- 2001-08-01 CN CNB011235519A patent/CN1156981C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101208921B (en) * | 2005-06-24 | 2011-01-12 | 松下电器产业株式会社 | Radio receiving apparatus |
| CN103141030A (en) * | 2010-09-30 | 2013-06-05 | 意法爱立信有限公司 | Reference clock sampling digital pll |
| CN103141030B (en) * | 2010-09-30 | 2016-01-20 | 意法爱立信有限公司 | Reference clock sampling digital phase-locked loop/FLL |
| CN103401829A (en) * | 2013-06-26 | 2013-11-20 | 吉林大学 | IQ imbalance compensation method for coherent-light orthogonal frequency division multiplexing (OFDM) communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1156981C (en) | 2004-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7248662B2 (en) | System and method for deriving symbol timing | |
| CN109831402B (en) | 16APSK signal carrier phase synchronization and judging and locking method thereof | |
| CN1582557B (en) | DAT-aided frequency offset detection using phase unwrapping | |
| US20090028252A1 (en) | Combined Frame Alignment and Timing Recovery in OFDM Communications Systems | |
| JPH04227348A (en) | Method and apparatus for correcting offset of clock and carrier frequency and phase jitters in multicarrier modem | |
| CN103181137B (en) | Pll circuit | |
| US6021157A (en) | Fast phase estimation in digital communication systems | |
| TW533720B (en) | Method and apparatus for eliminating the effects of frequency offsets in a digital communication system | |
| CN1156981C (en) | Phase compensation circuit for data phase-locked loop | |
| JP2000049882A (en) | Clock synchronization circuit | |
| JP3885909B2 (en) | Power detection device | |
| Gudovskiy et al. | A novel nondata-aided synchronization algorithm for MSK-type-modulated signals | |
| US7233635B2 (en) | Apparatus and method for digital symbol synchronization | |
| AU4756999A (en) | Time error compensation arrangement and multi-carrier modem comprising the arrangement | |
| US6937684B2 (en) | Phase discriminator with a phase compensation circuit | |
| US20010019593A1 (en) | xDSL sample rate compensation using phase balancing | |
| TW508900B (en) | Phase compensation circuit applicable to digital phase lock loop | |
| CN105072070A (en) | Digital broadband wireless signal synchronization algorithm | |
| JP3413359B2 (en) | QPSK demodulator | |
| US6757336B1 (en) | Device and method for performing a carrier recovery | |
| KR100319914B1 (en) | Phase Control Loop Circuits for Multicarrier Communication Systems | |
| Wu et al. | A low-complexity frequency offset correction scheme for synchronization in OFDM systems | |
| Chinchu et al. | A Comparative Study of Costas Loop and DPLL for Carrier Synchronization | |
| Wickert | A Simulation Framework to Introduce Modern DSP Based Synchronization Techniques in a PLL Course | |
| Tay | FEEDFORWARD CARRIER AND SYMBOL TIMING RECOVERY AND PHASE-INVARIANT SIGNALING FOR SOFTWARE-DEFINED RADIO |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040707 Termination date: 20090901 |