CN1395463A - Production method of laminated base material with high integrated level - Google Patents
Production method of laminated base material with high integrated level Download PDFInfo
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- CN1395463A CN1395463A CN 02140388 CN02140388A CN1395463A CN 1395463 A CN1395463 A CN 1395463A CN 02140388 CN02140388 CN 02140388 CN 02140388 A CN02140388 A CN 02140388A CN 1395463 A CN1395463 A CN 1395463A
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Abstract
The lamination basis plate consists of stacked the multiple dielectric layers and the multiple circuit layers in turn. The dielectric layer possesses the multiple through holes. The circuit layers via the through hole are connected each other electrically. The characters of the basis plate are that the embedded type structure designof the ring pads with no through hole possessing better adhesive force and high reliability on the circuit layer is utilized instead of the traditional design of the ring pads with through hole. The invention also discloses the method for manufacturing the basis plate. After the dielectric layer with the pattern and the dielectric layer withthe through hles being prepared, the two kinds of the layers are aligned and prssed together so as to complete the procedure of manufacturing the basis plate.
Description
Technical field
The present invention relates to a kind of laminated base material (laminated substrate) structure and manufacture method thereof, particularly a kind of encapsulation base material or printed circuit board arrangement and manufacture method thereof.
Background technology
Because the progress and the demand of electronics technology, various electronic correlation products are researched and developed to the direction of miniaturization, densification invariably.With the field of encapsulation, and ball lattice array encapsulation (Ball GridArray, BGA), (Chip Scale Package, CSP) etc. the research and development of technology all are orientated the demand of market to miniaturization and densification product to chip size packages.And aspect printed circuit board (PCB),, also used the technology of sandwich construction in order to dwindle the circuit area of whole printed circuit board (PCB).Yet, no matter be to be used for the base material of encapsulation of the encapsulation of ball lattice array, chip size packages or the making of printed circuit board (PCB) (PCB), all can't avoid using the via of conductive material as the connection between each layer line road.Therefore, fine rule road on the laminated base material and undersized via can make the density of encapsulation and the integrated level of printed circuit board (PCB) more improve.
The manufacture method of existing laminated base material mainly can be divided into laminating technology (LaminationProcess) and increase layer process (Build Up Process) two classes.Laminating technology is that a plurality of insulating barriers are provided earlier, then on the surface of insulating barrier, make line layer, and on each insulating barrier, hole, plating, jack process to be to produce (the Plating Through Hole that has the plating via, PTH), so that can reaching by the formed plating via of via technology, the two lip-deep line layers that insulate are electrically connected.After each insulating barrier making via is finished, in addition then on the surperficial copper layer after the pressing, make the conducting wire, thereafter by repeating the insulating barrier and the contraposition of surperficial copper layer of both determined number and being pressed into laminated base material and making numerous and diverse technology such as conducting wire and finish substrate or circuit board.
When making laminated base material with existing laminating technology, must carry out the consent action that via and insulation material were made, electroplated to via on insulating barrier, its technology is comparatively loaded down with trivial details and consuming time.In addition, the clear size of opening of insulating barrier near 100 microns situation under, its technology difficulty and unit cost will significantly increase, and clear size of opening less than 100 microns situation under, industry still can't be released the volume production product.Therefore, electroplate the problem that via will face the volume production technical bottleneck under less than 100 microns situation.
Except laminating technology, increase layer process also widely industry use.As its name suggests, increasing layer process mainly is that interlayer conduction hole in dielectric layer, the dielectric layer and the lip-deep line layer of dielectric layer are made from lower to upper in regular turn, to constitute laminated base material.Wherein, dielectric layer in the laminated base material mainly forms in modes such as pressing, coatings, after dielectric layer forms, use modes such as image formation/etch process or laser/electric paste etching in dielectric layer, to form opening (opening), and insert conductive material in the opening or with via between method cambium layer such as plating, and after the interlayer conduction hole completes, on the dielectric layer surface, carry out the chemical surface treatment of difficulty and the making of line layer again.The making step that repeats above-mentioned numerous and diverse, difficult dielectric layer, interlayer conduction hole and chemical surface treatment and line layer can produce laminated base material.
In the laminated base material that increases the layer process making, each dielectric layer and line layer must be made from lower to upper in regular turn, make whole technology too tediously long, and the good corrupt yield that all can directly influence whole laminated base material of the making of each layer dielectric layer and line layer, so the control of technology yield is difficult for.When making laminated base material, except having the problem that technology is too tediously long and the technology yield is low, also have technology cost height and equipment investment cost to be difficult for producing problems such as reliability reduction greatly or sometimes because of technology controlling and process with Layer increasing method.
Fig. 1 illustrates to line layer and via contact position in the existing laminated base material has the schematic diagram of ring pad with through hole (via land).Please refer to Fig. 1, circuit 100a and ring pad with through hole 102a utilize a dielectric layer (not illustrating) and circuit 100b and ring pad with through hole 102b interval.Wherein, the size of ring pad with through hole 102a, 102b (dimension) is big with the live width than circuit 100a, 100b (line width) of regular meeting's design, electrically connects to guarantee can utilize between the two-layer line layer (circuit layer) via 104 in the dielectric layer.Yet ring pad with through hole 102a and ring pad with through hole 102b can make layout (layout) space of line layer reduce usually, cause the circuit integrated level in the laminated base material effectively to improve.
Summary of the invention
Therefore, purpose of the present invention is proposing a kind of laminated base material, and its line layer and via contact position adopt no conduction through hole ring pad design (landless design), to promote the circuit integrated level in the laminated base material.
Purpose of the present invention is proposing a kind of laminated base material, and it has good electric performance (electrical performance) and heat radiation performance (thermal performance).
Purpose of the present invention is proposing a kind of laminated base material manufacture method, and it has, and advantages of high process yield, high production capacity, manufacture method are simple and easy, the characteristics of high integration and low cost of manufacture.
For realizing above-mentioned purpose of the present invention, a kind of laminated base material is proposed, constitute by a plurality of dielectric layers and the mutual storehouse of a plurality of line layer.Wherein, have a plurality of vias in the dielectric layer, and line layer improves the via in the dielectric layer and is electrically connected to each other, the laminated base material of present embodiment is characterised in that the line layer pattern between the dielectric layer is the design of no conduction through hole ring pad.The line layer pattern of no conduction through hole ring pad design can be promoted the circuit integrated level in the laminated base material effectively.
In the laminated base material of the present invention, comprise that also at least one welding pad opening layer is disposed on outermost two dielectric layers.Wherein, the welding pad opening layer has a plurality of openings corresponding to the via in the two outermost dielectric layers, and the demand of looking to impose the welding pad opening layer for example be a dielectric layer or an anti-welding cover layer (solder mask) or need not apply this layer.
For realizing above-mentioned purpose of the present invention, a kind of laminated base material manufacture method is proposed, the making that has the dielectric layer of patterned circuit earlier and have the dielectric layer of via, after the dielectric layer with patterned circuit and dielectric layer with via complete, again with its contraposition and pressing to finish the making of laminated base material.Wherein, has the dielectric layer of patterned circuit and to have between the dielectric layer of via for example be to carry out pressing in the mode that vacuum hotpressing is closed.In addition, at dielectric layer and after having the dielectric layer contraposition and pressing of via with patterned circuit, for example can carry out a curing schedule (curing), solidify with the dielectric material in the dielectric layer that will have patterned circuit and the dielectric layer with via.
For realizing above-mentioned purpose of the present invention, a kind of laminated base material manufacture method is proposed, have the dielectric layer of patterned circuit, dielectric layer and selectivity earlier and apply the making of welding pad opening layer with via, after the dielectric layer with patterned circuit, the dielectric layer with via and welding pad opening layer complete, again with its contraposition and pressing to finish the making of laminated base material.Wherein, has the dielectric layer of patterned circuit and to have between the dielectric layer of via for example be to carry out pressing in the mode that vacuum hotpressing is closed.In addition, at dielectric layer and after having the dielectric layer contraposition and pressing of via with patterned circuit, for example can carry out a curing schedule (curing), solidify and on suitable conducting place on line, finish electrically conducting with the dielectric material in the dielectric layer that will have patterned circuit and the dielectric layer with via.
The present invention provides one first supporter earlier, then on first supporter, form a patterned circuit, on first supporter, form one first dielectric layer at last to cover patterned circuit, so can on first supporter, form dielectric layer with patterned circuit.
The present invention provides one second supporter earlier, then on second supporter, form a plurality of via posts, form one second dielectric layer at last on second supporter, wherein the via post protrudes in the surface of second dielectric layer, so can finish the dielectric layer with via post on second supporter.
Patterned circuit of the present invention for example is to electroplate (pattern plating), semi-additive process (semi-additive) with metal etch (metal etching), patterning, or fully-additive process modes such as (full-additive) forms.In addition, first dielectric layer and second dielectric layer are for example with coating, and spraying or bonding mode form.
Opening in the welding pad opening layer of the present invention for example is that the mode with machine drilling, laser drill, punching (punch) forms.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, elaborated.
Description of drawings
Fig. 1 illustrates to line layer and via contact position in the existing laminated base material has the schematic diagram of ring pad with through hole;
Fig. 2 A to Fig. 2 D illustrates and is the making flow process generalized section according to the dielectric layer that has patterned circuit in the first embodiment of the invention laminated base material;
Fig. 3 A to Fig. 3 D illustrates and is the making flow process generalized section according to the dielectric layer that has via in the first embodiment of the invention laminated base material;
Fig. 4 A and Fig. 4 B illustrate and are the making flow process generalized section according to welding pad opening layer in the first embodiment of the invention laminated base material (pad opening layer);
Fig. 5 A and Fig. 5 B illustrate to carry out the flow process generalized section of pressing according to the first embodiment of the invention laminated base material;
Fig. 6 A to Fig. 6 D illustrates and is the making flow process generalized section according to the dielectric layer that has patterned circuit in the second embodiment of the invention laminated base material; And
Fig. 7 illustrates to have the schematic diagram of no conduction through hole ring pad design (landless design) according to line layer and via post contact position in the first embodiment of the invention and the second embodiment matrix structure.[figure number explanation] 100a, 100b, 700a, 700b: circuit 102a, 102b: ring pad with through hole 104,702: via 200: the dielectric layer 202,302,602 with patterned circuit: supporter 204,304,604,608: conductor layer 204a, 608a: patterned circuit 206,306,606: patterning photoresistance 208,308,610: dielectric layer 300: the dielectric layer 304a with via post: via post 400: dielectric layer 400a: welding pad opening layer 402,607: opening
Embodiment
First embodiment
Fig. 2 A to Fig. 2 D illustrates and is the making flow process generalized section according to the dielectric layer that has patterned circuit in the first embodiment of the invention laminated base material.In the present embodiment laminated base material patterned circuit for example with metal etch, patterning electroplate, semi-additive process, or fully-additive process forms.Present embodiment describes in the metal etch mode.At first please refer to Fig. 2 A, a supporter (supporter) 202 is provided, then on supporter 202, form a conductor layer 204 again.Wherein, the material of conductor layer 204 for example is a copper (Copper), and conductor layer 204 for example with sputter (sputtering), pressing is adhered to or the mode that deposits (deposition) is formed on the supporter 202.
Then please then form a patterning photoresistance 206 on conductor layer 204 simultaneously with reference to Fig. 2 B and Fig. 2 C, patterning photoresistance 206 is in order to define the pattern of its lower conductor layer 204.Wherein, patterning photoresistance 206 for example is to be formed on the conductor layer 204 through step such as photoresistance coating, exposure, development.After patterning photoresistance 206 forms, be the conductor layer 204 of screenings (mask) etching under it with patterning photoresistance 206, not removed by the conductor layer 204 of patterning photoresistance 206 coverings, with formation patterned circuit 204a.Afterwards, again patterning photoresistance 206 is divested.
Then please refer to Fig. 2 D, after forming patterned circuit 204a, then form a dielectric layer 208 on supporter 202, and cover patterned circuit 204a.Wherein, patterned circuit 204a and dielectric layer 208 promptly constitute a dielectric layer 200 with Embedded patterned circuit.
Fig. 3 A to Fig. 3 D illustrates and is the making flow process generalized section according to the dielectric layer that has the via post in the first embodiment of the invention laminated base material.At first please refer to Fig. 3 A, a supporter 302 is provided, then on supporter 302, form a conductor layer 304 again.Wherein, the material of conductor layer 304 for example is a copper, and conductor layer 304 for example is to adhere to or the mode that deposits is formed on the supporter 302 with sputter, pressing.
Then please then form a patterning photoresistance 306 on conductor layer 304 simultaneously with reference to Fig. 3 B and Fig. 3 C, patterning photoresistance 306 is for example in order to define the pattern of its lower conductor layer 304.Wherein, patterning photoresistance 306 for example is to be formed on the conductor layer 304 through step such as photoresistance coating, exposure, development.After patterning photoresistance 306 forms, serve as its conductor layer 304 down of shielding etching with patterning photoresistance 306, not removed by the conductor layer 304 of patterning photoresistance 306 coverings, with formation via post 304a.Afterwards, again patterning photoresistance 306 is divested.
Then please refer to Fig. 3 D, after forming via post 304a, then form a dielectric layer 308 on supporter 302, and cover via post 304a.Wherein, via post 304a and dielectric layer 308 promptly constitute a dielectric layer 300 with via post.Learn the visual process requirements of size of via post 304a and changing by knowing among Fig. 3 D.
Fig. 4 A and Fig. 4 B illustrate and are the making flow process generalized section according to welding pad opening layer in the first embodiment of the invention laminated base material.Please at first provide a dielectric layer 400 simultaneously with reference to Fig. 4 A and Fig. 4 B, then in dielectric layer 400, form opening 402, to form welding pad opening layer 400a.Wherein, the opening 402 among the welding pad opening layer 400a for example forms in the mode of machine drilling, laser drill or punching.
Fig. 5 A and Fig. 5 B illustrate to carry out the flow process generalized section of pressing according to the first embodiment of the invention laminated base material.At first please a plurality of dielectric layers with patterned circuit 200 that completed, the dielectric layer 300 with via post and welding pad opening layer 400a be carried out contraposition, illustrate as Fig. 5 A simultaneously with reference to Fig. 5 A and Fig. 5 B.After the contraposition, have the dielectric layer 200 of patterned circuit, dielectric layer 300 and a welding pad opening layer 400a pressing, promptly finish the making of laminated base material with via post with above-mentioned.Wherein, have and for example improve the mode that vacuum hotpressing closes between the dielectric layer 200 of patterned circuit, dielectric layer 300 and the welding pad opening layer 400a and carry out pressing with via post.
Please refer to Fig. 5 A and Fig. 5 B equally, in the manufacturing process of laminated base material, welding pad opening layer 400a is the member of selectivity (optional).In other words, present embodiment also can only carry out contraposition and pressing with a plurality of dielectric layer 200 and a plurality of dielectric layers 300 with via post with patterned circuit.Thus, the manufacturing process of laminated base material can be saved welding pad opening layer 400a, make integrated artistic more simplify.
Second embodiment
Present embodiment is identical with first embodiment in the making of dielectric layer with via post and welding pad opening layer, but the difference part of the present embodiment and first embodiment is to have the production method of the dielectric layer of patterned circuit.
Fig. 6 A to Fig. 6 D illustrates and is the making flow process generalized section according to the dielectric layer that has patterned circuit in the second embodiment of the invention laminated base material.At first please refer to Fig. 6 A, a supporter 602 is provided, then on supporter 602, form a conductor layer 604 again.Wherein, the material of conductor layer 604 is a copper for example, and conductor layer 604 for example adheres to sputter, pressing or the mode that deposits is formed on the supporter 602.
Then please then form a patterning photoresistance 606 on conductor layer 604 simultaneously with reference to Fig. 6 B and Fig. 6 C, patterning photoresistance 606 has a plurality of openings 607.Wherein, patterning photoresistance 606 for example is to be formed on the conductor layer 604 through step such as photoresistance coating, exposure, development.After patterning photoresistance 606 forms, conductor layer 608 is inserted in the opening 607 of patterning photoresistance 606, because opening 607 is a set pattern, so the conductor layer of inserting in the opening 607 608 can be consistent with above-mentioned set pattern.Afterwards, again patterning photoresistance 606 is divested, so that the conductor layer under it 604 is exposed.
Then please refer to Fig. 6 C and Fig. 6 D, after patterning photoresistance 606 divests, then for example carry out the step of a non-selectivity microetch, so that conductor layer 604 is removed.In the process that conductor layer 604 removes, it is etched and form patterned circuit 608a that conductor layer 608 also has partly thickness.After patterned circuit 608a forms, then form a dielectric layer 610 on supporter 602, and cover patterned circuit 608a.Wherein, patterned circuit 608a and dielectric layer 610 promptly constitute a dielectric layer 600 with patterned circuit.
The technology of above-mentioned Fig. 6 A to Fig. 6 D can carry out the making on fine rule road in laminated base material, and this fine line technology (Fig. 6 A to Fig. 6 D) can effectively improve the line density in the laminated base material, also the layout elasticity of line layer in the laminated base material be benefited to some extent simultaneously.
Fig. 7 illustrates to have the schematic diagram of no conduction through hole ring pad design (landless design) according to line layer and via post contact position in the first embodiment of the invention and the second embodiment matrix structure.Please refer to Fig. 7, circuit 700a and electrically connects by via post 702 between circuit 700a and the circuit 700b by a dielectric layer (not illustrating) and circuit 700b separately.
Then simultaneously with reference to Fig. 1 and Fig. 7, in the present embodiment, direct and via post 702 electric connections of circuit 700a and circuit 700b do not need existing ring pad with through hole 102a, 102b design (being illustrated in Fig. 1).Therefore, the arrangement space of line layer can't be subjected to the restriction of ring pad with through hole 102a, 102b and reduces in the present embodiment.
In sum, laminated base material of the present invention and manufacture method thereof have following advantage at least:
1. in the laminated base material of the present invention, line layer and via contact position adopt the design of no conduction through hole ring pad, can significantly promote the circuit integrated level in the laminated base material.
2. in the laminated base material of the present invention, the via post adopts solid design (solid via), so have good electric performance and heat radiation performance.
3. in the laminated base material manufacture method of the present invention, only need can produce laminated base material by the mode of Patternized technique (patternprocess) and synchronous lamination, thus manufacturing time can be shortened effectively, and then improve production capacity.
4. in the laminated base material manufacture method of the present invention, only need can produce laminated base material, so can save the investment that has now at miscellaneous equipment by the mode of Patternized technique (patternprocess) and synchronous lamination.
5. in the laminated base material manufacture method of the present invention, before each layer (having the dielectric layer of patterned circuit, the dielectric layer with via post and welding pad opening layer) carries out lamination, can confirm each layer respectively, so the yield of laminated base material is easier to control and effectively reduces production costs.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, thus protection scope of the present invention should with claim the person of being defined be as the criterion.
Claims (10)
1. a laminated base material manufacture method is characterized in that, comprising:
One first supporter is provided;
On this first supporter, form a patterned circuit;
Form one first dielectric layer on this first supporter, this first dielectric layer covers this patterned circuit, to form a dielectric layer with patterned circuit on this first supporter;
One second supporter is provided;
On this second supporter, form a plurality of via posts;
Form one second dielectric layer on this second supporter, these via posts protrude in this second dielectric layer, have the dielectric layer of via post with formation one on this second supporter; And
With a plurality of dielectric layer and a plurality of dielectric layer contraposition and pressings, so that a little via post pierces through this first dielectric layer and electrically connects with this patterned circuit with via post with patterned circuit.
2. laminated base material manufacture method as claimed in claim 1, it is characterized in that: these have after the dielectric layer of patterned circuit and the dielectric layer contraposition and pressing that these have the via post, also comprise and carry out a curing schedule, be connected so that this first dielectric layer and this second dielectric layer are solidified the electrically conducting of also finishing conductive site simultaneously.
3. laminated base material manufacture method as claimed in claim 1 is characterized in that, the formation method of this patterned circuit comprises:
Form a conductor layer on this first supporter;
Form a patterning photoresistance on this conductor layer; And
With this patterning photoresistance is shielding, removes this conductor layer that is not covered by this patterning photoresistance, to form this patterned circuit.
4. laminated base material manufacture method as claimed in claim 1 is characterized in that, the formation method of this patterned circuit comprises:
Form one first conductor layer on this first supporter;
Form a patterning photoresistance on this conductor layer, this patterning photoresistance has a plurality of openings;
Form one second conductor layer in these second openings;
Remove this patterning photoresistance; And
Remove this first conductor layer that is not covered, to form this patterned circuit by this second conductor layer.
5. laminated base material manufacture method as claimed in claim 1 is characterized in that: these have the dielectric layer of patterned circuit and the pressing of these dielectric layers with via post is that vacuum hotpressing is closed.
6. a laminated base material manufacture method is characterized in that, comprising:
One first supporter is provided;
On this first supporter, form a patterned circuit;
Form one first dielectric layer on this first supporter, this first dielectric layer covers this patterned circuit, to form a dielectric layer with patterned circuit on this first supporter;
One second supporter is provided;
On this second supporter, form a plurality of via posts;
Form one second dielectric layer on this second supporter, these via posts protrude in this second dielectric layer, have the dielectric layer of via post with formation one on this second supporter;
At least one welding pad opening layer is provided, and this welding pad opening layer has a plurality of openings; And
Have the dielectric layer of patterned circuit, a plurality of dielectric layer and this contraposition of welding pad opening layer and pressing with a plurality of, so that a little via post pierces through this first dielectric layer and electrically connects with this patterned circuit with via post.
7. laminated base material manufacture method as claimed in claim 6, it is characterized in that: these have after dielectric layer, these dielectric layers with via post and this welding pad opening layer contraposition and the pressing of patterned circuit, also comprise and carry out a curing schedule, be connected so that this first dielectric layer and this second dielectric layer are solidified the electrically conducting of also finishing conductive site simultaneously.
8. laminated base material manufacture method as claimed in claim 6 is characterized in that, the formation method of this patterned circuit comprises:
Form a conductor layer on this first supporter;
Form a patterning photoresistance on this conductor layer; And
With this patterning photoresistance is shielding, removes this conductor layer that is not covered by this patterning photoresistance, to form this patterned circuit.
9. laminated base material manufacture method as claimed in claim 6 is characterized in that, the formation method of this patterned circuit comprises:
Form one first conductor layer on this first supporter;
Form a patterning photoresistance on this conductor layer, this patterning photoresistance has a plurality of openings;
Form one second conductor layer in these second openings;
Remove this patterning photoresistance; And
Remove not by this first conductor layer of this second conductor layer covering, to form this patterned circuit.
10. as the laminated base material manufacture method as described in the claim 6, it is characterized in that the formation method of these via posts comprises:
Form a conductor layer on this second supporter;
Form a patterning photoresistance on this conductor layer; And
With this patterning photoresistance is shielding, removes this conductor layer that is not covered by this patterning photoresistance, to form these via posts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02140388 CN1201645C (en) | 2002-07-02 | 2002-07-02 | Production method of laminated base material with high integrated level |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02140388 CN1201645C (en) | 2002-07-02 | 2002-07-02 | Production method of laminated base material with high integrated level |
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| Publication Number | Publication Date |
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| CN1395463A true CN1395463A (en) | 2003-02-05 |
| CN1201645C CN1201645C (en) | 2005-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02140388 Expired - Lifetime CN1201645C (en) | 2002-07-02 | 2002-07-02 | Production method of laminated base material with high integrated level |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463584C (en) * | 2004-11-05 | 2009-02-18 | 财团法人工业技术研究院 | Pore column dividing type intercommunicating pore structure and its manufacturing method |
| CN101277591B (en) * | 2007-03-29 | 2010-09-22 | 欣兴电子股份有限公司 | Inner embedded type circuit board and method for manufacturing the same |
| US7926172B2 (en) | 2007-03-16 | 2011-04-19 | Unimicron Technology Corp. | Embedded circuit board and process thereof |
| CN113129760A (en) * | 2021-05-18 | 2021-07-16 | 吕文伟 | Flexible display screen and installation method |
-
2002
- 2002-07-02 CN CN 02140388 patent/CN1201645C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463584C (en) * | 2004-11-05 | 2009-02-18 | 财团法人工业技术研究院 | Pore column dividing type intercommunicating pore structure and its manufacturing method |
| US7926172B2 (en) | 2007-03-16 | 2011-04-19 | Unimicron Technology Corp. | Embedded circuit board and process thereof |
| CN101277591B (en) * | 2007-03-29 | 2010-09-22 | 欣兴电子股份有限公司 | Inner embedded type circuit board and method for manufacturing the same |
| CN113129760A (en) * | 2021-05-18 | 2021-07-16 | 吕文伟 | Flexible display screen and installation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1201645C (en) | 2005-05-11 |
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