CN1395155A

CN1395155A - Conversion device of DDR and QDR and adapter card, main board and internal memory module interface using it

Info

Publication number: CN1395155A
Application number: CN 01120119
Authority: CN
Inventors: 吴坤河; 庄海峰
Original assignee: Leadtek Technology Co Ltd
Current assignee: Leadtek Technology Co Ltd
Priority date: 2001-07-05
Filing date: 2001-07-05
Publication date: 2003-02-05

Abstract

The invention relates to the conversion device of DDR and QDR as well as the relevant adaptation cards, main boards and memory module interfaces. The conversion device of DDR and QDR possesses QDR interface element, DDR interface element and the conversion core element. The QDR interface element is utilized to exchange the signal for the QDR element. The DDR interface element is utilized to exchange the signal for the DDR element. The conversion core element converts the commands and data in the QDR format to the commands and data in the DDR format, as well as converts the commands and data in the DDR format to the commands and data in the QDR format.

Description

The conversion equipment of DDR and QDR and adapter, mainboard and the memory module interfaces of using it

The invention relates to a kind of internal memory conversion equipment and use its device, and particularly relevant for the conversion equipment and the adapter, mainboard, memory modules and the portable computer mainboard that use it of a kind of DDR and QDR.

Because the improvement of computer technology and technology, encapsulation technology not only has the growth of advancing by leaps and bounds on the processing speed of central processing unit (CPU, Central Processing Unit), many changes are also arranged on internal memory.Along with the raising that the internal memory access speed is required, internal memory commonly used is also from incipient DRAM (Dynamic Random Access Memory) (DRAM), extension data output random access memory (EDO RAM) etc., until most common synchronization DRAM (Dynamic Random Access Memory) (Synchronous Data Rate RAM now, hereinafter referred to as the SDR random access memory) and double data rate (DDR) random access memory (Double Data Rate RAM is hereinafter referred to as the DDR random access memory).And along with the raising of memory access speed, the cost of making various random access memorys is higher.

Therefore, the access speed that the present invention proposes the present internal memory of a kind of ratio is method and structure faster, can improve the efficient of DDR random access memory significantly, and can not expend too many cost of manufacture.The structure that this kind is brand-new is called quadruple according to rate random access memory (Quadruple DataRate RAM is hereinafter referred to as the QDR random access memory).And present invention includes conversion method between formulation, DDR and the QDR signal system of QDR signal system.DDR proposed by the invention and the transformational structure of QDR and method can be used in various need the use in all electronic installations of random access memory, for example adapter, mainboard and portable computer mainboard etc.

The present invention proposes the conversion equipment of a kind of DDR and QDR, and this conversion equipment has QDR interface element, ddr interface element, clock controller, instruction control unit, status register group and DTU (Data Transfer unit).Wherein, the QDR interface element is used for carrying out signal exchange with the QDR element, and the ddr interface element then is used for carrying out signal exchange with the DDR element.Clock controller will be converted to conversion equipment and the employed clock of DDR element by the clock signal that the QDR element is delivered to.Instruction control unit is processed into corresponding DDR command signal with the QDR command signal after obtaining the QDR command signal of QDR element, and outputs to the DDR element.The status register group is used for storing the employed module buffer of QDR interface group (Mode Register Set, MRS) with extension of module buffer group (Extended Mode Register Set, EMRS) data in, and provide transitional information to make suitable instruction and data-switching to instruction control unit.DTU (Data Transfer unit) then is used for the data kenel of QDR is converted to the data kenel that is applicable to DDR, and the data kenel of DDR is converted to the data kenel that is applicable to QDR.

And in one embodiment of the invention, DTU (Data Transfer unit) has comprised a data shielding and has surveyed controller, QDR to a DDR data converter, and DDR to a QDR data converter.Wherein, data mask and detection controller are used for obtaining the QM signal and the DQS signal of QDR element, the QM signal is changed into DDR QM signal and DDR QM signal is outputed to the DDR element, and transfer the DQS signal to the QDR element extracts data to the DDR element data extract signal.QDR to DDR data converter converts the serial signal of QDR element to parallel signal, and according to the order of instruction control unit, and the parallel signal of conversion gained separately is transferred to two DDR elements.DDR to QDR data converter then changes into the employed serial signal of QDR element with the data-signal of two DDR elements, and transfers to the QDR element according to the serial signal that the order of instruction control unit will be changed gained.

In sum, the present invention sets up ALT-CH alternate channel between QDR and DDR, make DDR in system that supports QDR or device, normally to move, and do not need and will support the system of QDR or install whole system or the device of supporting DDR that convert to, therefore can be so that the normal simultaneously operation of DDR and QDR.

The user can not need to purchase new QDR memory modules, uses device of the present invention in conjunction with existing DDR memory modules, can make the only DDR efficient of script bring up to the memory module that possesses QDR efficient.

Concerning the producer, when printed circuit board (PCB)s such as making adapter, mainboard, can the lower DDR chip of alternative costs, cooperate device of the present invention, can make product have the data-handling efficiency of QDR equally, make the existing product of the products and marketing of being produced have same quality and effect, but its cost of manufacture can significantly reduce.

For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below:

The accompanying drawing simple declaration:

Figure 1A is the block scheme according to the conversion equipment of the first embodiment of the present invention;

Figure 1B is the embodiment according to the utilization circuit of Figure 1A conversion equipment;

Fig. 2 A is the block scheme of conversion equipment according to a second embodiment of the present invention;

Fig. 2 B is the embodiment according to the utilization circuit of Fig. 2 A conversion equipment;

Fig. 3 A is the block scheme according to the conversion equipment of third embodiment of the invention;

Fig. 3 B is first embodiment according to the utilization circuit of Fig. 2 A conversion equipment;

Fig. 3 C is second embodiment according to the utilization circuit of Fig. 3 A conversion equipment;

Fig. 3 D is the 3rd embodiment according to the utilization circuit of the conversion equipment of Fig. 2 A;

Fig. 4 is the block scheme of the conversion equipment of a fourth embodiment in accordance with the invention;

Fig. 5 is a block scheme according to a fifth embodiment of the invention;

Fig. 6 is a block scheme according to a sixth embodiment of the invention;

Fig. 7 is a block scheme according to a seventh embodiment of the invention;

Fig. 8 is the block scheme according to the eighth embodiment of the present invention; And

Fig. 9 is the block scheme according to the ninth embodiment of the present invention.Description of reference numerals: 10,20,30,52,62,70,80,92,1002,1102,1202,1302, the conversion equipment 12 of 1402:DDR and QDR, 22,32,42: conversion core parts 14,24,34,40:

QDR interface element

18,28,38,44,46,48,410:DDR interface element 512: adapter 54,56:DDR modular matrix 612: mainboard 64,66:DDR DIMM712:

memory modules

72,74,76:DDR memory chip group matrix 812: memory module interfaces 82,84:DDR DIMM912: the mainboard 94 of portable computer, 96:SO-DIMM

slot

1000,1100,1200,1300,1400:

QDR element

1004,1104,1204,1304,1404:SQDR1006,1106,1306: phase-locked loop (being called for short PLL) 120,220,320: clock controller 122,222,322: instruction control unit 124,224,324: status register group 126,226,326: DTU (Data Transfer unit) 50,60,90: chipset 1260,2260,3260: data mask and detection controller 1262,2262,3262:DDR to QDR data converter 1264,2264,3264:QDR to DDR data converter

Embodiment

Please refer to Figure 1A, is the block scheme according to first embodiment of the present invention conversion equipment.In the conversion equipment 10 of DDR and QDR, comprised a QDR interface element 14, a ddr interface element 18 and conversion core parts 12, and conversion equipment 10 is named with " DQDR " at this.

QDR interface element 14 is between QDR memory modules and conversion core parts 12, is used for carrying out the exchange of signal.Ddr interface element 18 then between DDR memory modules and conversion core parts 12, is used for carrying out the exchange of signal.In Figure 1A, also drawn conversion core parts 12 block scheme according to an embodiment of the invention in more detail.In this embodiment, conversion core parts 12 have comprised a clock controller 120, instruction control unit 122, a status register group 124, and a data conversion equipment 126.Wherein, (CKn CKn#) converts conversion equipment 10 inner uses and the employed clocks of DDR memory modules (MCKn) to the clock signal that clock controller 120 will be delivered to by the QDR memory modules.

After instruction control unit 122 is used for receiving the QDR instruction (for example comprising CSn, RAS, CAS, Ban, Can, WE etc.) that the QDR memory modules sends, the QDR command signal is processed into corresponding DDR instruction (for example corresponding MCSn, MRAS, MCAS, MBAn, Man, MWE etc.), outputs to then in the DDR memory modules.And the instruction of working as QDR is as if the access that has for data, when for example the QDR instruction needs to use the read or write command of data, DTU (Data Transfer unit) 126 will the mobilizing function control system, these systems comprise data mask and detection system, QDR to DDR data conversion system and DDR to the QDR data conversion system.The data kenel that these systems have with QDR DTU (Data Transfer unit) 126 is converted to the data kenel that is applicable to DDR, and the function that the data kenel of DDR is converted to the data kenel that is applicable to QDR.Status register group 124 then is used for storing the employed module buffer of QDR interface group, and (Mode Register Set is MRS) with extension of module buffer group (ExtendedMode Register Set, EMRS) data in.

For being described in more detail the present invention, in Figure 1A, the DTU (Data Transfer unit) 126 internal circuit block schemes of one embodiment of the invention have also been drawn in more detail.In this embodiment, DTU (Data Transfer unit) 126 has comprised the shielding of data and has surveyed controller 1260, DDR to a QDR data converter 1262 and QDR to a DDR data converter 1264.

When the mobilizing function control system, when the order of reading or writing of data is just arranged, data mask with survey controller 1260 just can reach the QM signal and the DQS signal of QDR memory modules, the QM signal is changed into DDR QM signal be input to the DDR memory modules again, and used data extract signal when the DQS signal changed into QDR the DDR element is extracted data.When the QDR command signal was data read command, QDR to DDR data converter 1264 can convert the serial signal of QDR element to parallel signal, and according to the order of instruction control unit 122, and the parallel signal of conversion gained separately is transferred to two DDR elements.When the QDR command signal is the data write command, DDR to QDR data converter 1262 can change into the employed serial signal of QDR element to the data-signal of two DDR elements, and transfers to the QDR element according to the serial signal that the order of instruction control unit 122 will be changed gained.

Because QDR sends four bits (bit) in one-period (cycle), and DDR only can send two bits in one-period, so QDR all is better than DDR on processing speed and efficient, in the above-described embodiments, be the conversion equipment that designs DDR and QDR in the mode of corresponding two the DDR elements of a QDR element.But the person skilled in the art should know, in fact also can one the mode of the corresponding DDR element of QDR element design this conversion equipment, but obviously its efficient will reduce, if will keep identical efficient, then the frequency of DDR must be increased to two times that are about QDR, just can make the DDR output bit identical, but the technology of frequency that improves DDR is also difficult with QDR, therefore required cost also can improve relatively, uses two groups of DDR modules to produce the efficient of QDR so the present invention still is applied in.

Please refer to Figure 1B, is the circuit diagram according to conversion equipment 10 practice of the embodiment of the invention shown in Figure 1A.Conversion equipment 10 among Figure 1A can be used among Figure 1B, wherein ought write fashionable, then by the conversion equipment 1402 of QDR element 1400 input DQS signals to DDR and QDR.When reading, QDR element 1400 will be imported the conversion equipment 1402 of DQS signal to DDR and QDR, then after the DQDR 1404 via the conversion equipment 1402 of DDR and QDR handles, input to QDR element 1400 at last, wherein the person skilled in the art as can be known this conversion equipment 10 need not use the clock signal of outside phase-locked loop and two times, and the DQS signal is directly to transmit.

For example: when QDR element 1400 wants access data to DDR, at first QDR element 1400 can be sent an access command, then via the instruction control unit 122 of the QDR interface element shown in Figure 1A 14 to conversion equipment 10, after this moment, instruction control unit 122 received the access command of QDR element 1400, be processed into corresponding DDR instruction, coomand mode data buffer 124 is stored the data in QDR interface 14 employed module buffer groups and the extension of module buffer group then, and the mobilizing function control system.After the mobilizing function control system, data mask and detection controller 1260 can remove to read the DM signal and the DQS signal of QDR element 1400, data mask with survey controller 1260 and the DM conversion of signals of QDR element 1400 can be become DDR DM signal, and used data extract signal when becoming QDR that the DDR element is extracted data the DQS conversion of signals of QDR element 1400.

When the access command of QDR element 1400 is the data write command, then can convert the serial signal of QDR element 1400 to parallel signal via the data converter of the QDR to DDR shown in Figure 1A 1264, and, separately send the parallel signal of conversion gained to two DDR elements according to the order of instruction control unit 122.When the access command of QDR element 1400 is data read command, DDR to QDR data converter 1262 can convert the data-signal of two DDR elements to QDR element employed serial signal, and transfers to QDR element 1400 according to the serial signal that the order of instruction control unit 122 will be changed gained.

Please refer to Fig. 2 A, is the block scheme of conversion equipment according to a second embodiment of the present invention.The function of all devices all device with Figure 1A is identical, unique difference be when data mask when surveying controller 2260 and obtain the QM of QDR element and DQS signal, the QM signal is changed into DDR QM signal and outputs to the DDR element, used data extract signal when the DQS signal is changed into the QDR element DDR element is extracted data, and in the time must returning the DQS signal, produce the DQS signal of passback according to two times clock signals to the QDR element.

Please refer to Fig. 2 B, be a embodiment according to the utilization circuit of Fig. 2 A conversion equipment, conversion equipment 20 of the present invention can be used among Fig. 2 B, among this figure from the direction of the conversion equipment 1202 of QDR element 1200 to DDR and QDR for writing, and from the direction of conversion equipment 1202 to the QDR elements 1200 of DDR and QDR for reading.If produce the DQS signal of passback by two times clock signals, writing fashionablely, just import the conversion equipment 1204 of DQS signals to DDR and QDR by QDR element 1200.When reading, just the DQDR 1204 by the conversion equipment 1202 of DDR and QDR changes into the DQS signal with two times of clock signals that QDR element 1200 is provided, and then outputs to QDR element 1200.

Please refer to Fig. 3 A, is the block scheme of the conversion equipment of the third embodiment of the present invention.The function of all devices all conversion equipment with Figure 1A is identical, and unique difference is phase-locked loop (PhaseLock Loop, beneath abbreviation PLL) 321 and data mask and detection controller 3260.Behind the 321 receive clock signals of phase-locked loop, can produce frequency is the clock signal output doubly of input clock signal frequency plural number, for example two of present embodiment times clock signal.And data mask and detection controller 3260 are when obtaining the QM of QDR element and DQS signal, the QM signal is changed into DDR QM signal and outputs to the DDR element, used data extract signal when the DQS signal is changed into the QDR element DDR element is extracted data, and in the time must returning the DQS signal to the QDR element, then the clock signal of being exported according to phase-locked loop 321 produces the DQS signal of passback.

Please refer to Fig. 3 B and Fig. 3 D, is the practice circuit embodiments according to Fig. 2 A conversion equipment 20 of the embodiment of the invention.Conversion equipment 20 of the present invention can be used among Fig. 3 B.Among this figure from the direction of the conversion equipment 1202 of QDR element 1000 to DDR and QDR for writing, and from the direction of conversion equipment 1202 to the QDR elements 1000 of DDR and QDR for reading.Fig. 3 B and Fig. 3 D mainly illustrate in Fig. 2 A conversion equipment 20 phase-locked loop 321 can in be built in DDR and the QDR conversion equipment 1002, or in be built in the DQDR 1004, or provide by the outside.

In one embodiment, if phase-locked loop 1006 is the insides at the conversion equipment 1002 of DDR and QDR, and the clock signal that produces the clock signal with two times is during to DTU (Data Transfer unit), write fashionable, just by the conversion equipment 1002 of QDR element 1000 output DQS signals to DDR and QDR.When reading, then the DQDR 1004 by the conversion equipment 1002 of DDR and QDR changes into the DQS signal with the passback clock signal that phase-locked loop 1006 is provided, and outputs to QDR element 1000 then.

In another embodiment, if phase-locked loop 1106 is in DQDR 1104 inside, please refer to Fig. 3 C, is the practice circuit embodiments according to Fig. 3 A conversion equipment 30 of the embodiment of the invention.And the clock signal that phase-locked loop 1106 is produced outputs to DTU (Data Transfer unit).Write fashionable, just by the conversion equipment 1102 of QDR element 1100 input DQS signals to DDR and QDR.When reading, then the DQDR 1104 by the conversion equipment 1102 of DDR and QDR changes into the DQS signal with the passback clock signal that phase-locked loop 1106 is provided, and outputs to the QDR element then.

In another embodiment, if phase-locked loop 1306 is provided by external circuit, please refer to Fig. 3 D, is the practice circuit embodiments according to Fig. 2 A conversion equipment 20 of the embodiment of the invention.And the clock signal that phase-locked loop 1306 is produced is input in the conversion equipment 1302 of DDR and QDR.Write fashionable, just by the conversion equipment 1302 of QDR element 1300 input DQS signals to DDR and QDR.When reading, then the DQDR 1304 by the conversion equipment 1302 of DDR and QDR changes into the DQS signal with the passback clock signal that phase-locked loop 1306 is provided, and outputs to the QDR element then.

Please refer to Fig. 4, is the block scheme of the embodiment of the invention.Wherein change core parts and be used for instruction and the data mode that instruction and data mode with QDR convert DDR to, be input to the DDR element by

ddr interface element

44,46, and instruction and data mode with instruction and the data mode of DDR converts QDR to are sent to the QDR element by QDR interface element 40.

Next please refer to Fig. 5, is the embodiment that internal memory conversion equipment of the present invention is applied to adapter, the just fifth embodiment of the present invention.In adapter 512, a chipset of supporting to use the QDR module 50, conversion equipment 52 and two DDR

modular matrixs

54,56 have been comprised.Wherein, in order to make block scheme become apparent, the QDR interface element of conversion equipment 52 and ddr interface element are only respectively to represent with the connecting line that DDR

modular matrix

54,56 is connected with chipset 50.With the connected mode of this kind device, just can on the adapter 512 of supporting the QDR module, use the DDR modular matrix.

Next please refer to Fig. 6, is the embodiment that internal memory conversion equipment of the present invention is applied to mainboard, the just sixth embodiment of the present invention.In mainboard 612, a chipset of supporting the QDR module 60, conversion equipment 62 and two DDR

DIMM

64,66 have been comprised.Wherein, in order to make that block scheme can be clearer, the QDR interface element of conversion equipment 62 is only represented with the connecting line that DDR

DIMM

64,66 is connected with chipset 60 respectively with the ddr interface element.With the connected mode of this kind device, just can on the mainboard 612 of supporting QDR DIMM, use DDR DIMM.

Next please refer to Fig. 7, is the embodiment that internal memory conversion equipment of the present invention is applied to memory modules (Memory Module), the just seventh embodiment of the present invention.In memory modules 712, a conversion equipment 70 and a plurality of DDR memory chip group matrix 72～76 have been comprised.Wherein, in order to make that block scheme can be clearer, the QDR interface element of conversion equipment 70 is represented with the connecting line that a plurality of DDR memory chip group matrixes 72～76 are connected with the outside device respectively with the ddr interface element.With the connected mode of this kind device, just can on the memory modules 712 of supporting QDR memory chip group matrix, use DDR memory chip group matrix.

Next please refer to Fig. 8, is the block scheme according to eighth embodiment of the invention.In memory module interfaces 812, a conversion equipment 80 and two DDR DIMM 82,84 have been comprised.Wherein, in order to make that block scheme can be clearer, the QDR interface element of conversion equipment 80 is represented with the connecting line that two DDR DIMM 82,84 are connected with the outside device respectively with the ddr interface element.With the connected mode of this kind device, just can on the memory module interfaces 812 of supporting QDR DIMM, use DDR DIMM.

Please refer to Fig. 9, is the block scheme of ninth embodiment of the invention.In the mainboard 912 of portable computer, a chipset of supporting the QDR module 90, conversion equipment 92 and two

DDR dimm sockets

94,96 have been comprised.Wherein, in order to make that block scheme can be clearer, the QDR interface element of conversion equipment 92 is only represented with the connecting line that DDR

dimm socket

94,96 is connected with chipset 90 respectively with the ddr interface element.With the connected mode of this kind device, just can on the mainboard 912 of the portable computer of supporting the QDR dimm socket, use the DDR dimm socket.

In sum, the present invention not only can also still have the data-handling efficiency of QDR so that DDR and QDR are normal simultaneously to be moved by set up ALT-CH alternate channel between QDR and DDR under the situation of only using the DDR internal memory.

The user can not need to purchase new QDR memory modules, use device of the present invention in conjunction with existing DDR memory modules, can make the only DDR efficient of script bring up to the memory module of efficient with QDR, also can use existing DDR memory modules, add that device of the present invention and QDR memory modules use simultaneously, further improve the efficient of system.

Concerning the producer, when making memory modules and adapter, can the lower DDR chip of alternative costs, cooperate device of the present invention, can make product have the data-handling efficiency of QDR equally, make the existing QDR product of the products and marketing of being produced have same quality and effect, but its cost of manufacture can significantly reduce.And when making mainboard, use device of the present invention still under the situation of only using the DDR module, can reach the efficient of QDR for the user no matter use under the situation of DDR and QDR module at the same time, therefore can improve competitiveness of product.

Though the present invention with the embodiment explanation as above; so it is not to be used for limiting the present invention, any person skilled in the art, without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is when being as the criterion with claims.

Claims

1. the conversion equipment of DDR and QDR is characterized by: comprising:

One QDR interface element is used for carrying out signal exchange with the QDR element;

One ddr interface element is used for carrying out signal exchange with the DDR element;

One clock controller is used for the clock conversion of signals that the QDR element is delivered to is become this conversion equipment and the employed operation clock signal of DDR element;

One status register group is used for storing the QDR element state;

One DTU (Data Transfer unit) is used for the data kenel of QDR is converted to the data kenel that is applicable to DDR, and the data kenel of DDR is converted to the data kenel that is applicable to QDR; And

One instruction control unit after obtaining a QDR command signal of QDR element, is processed into a corresponding DDR command signal with this QDR command signal, and exports the DDR element to.

2. the conversion equipment of DDR as claimed in claim 1 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, be used for obtaining the QM signal and the DQS signal of QDR element, the QM signal is changed into DDR QM signal and DDR QM signal is inputed to the DDR element, and transfer the DQS signal to the QDR element extracts data to the DDR element a data extract signal;

One QDR to DDR data converter converts the serial signal of QDR element to parallel signal, and according to the order of this instruction control unit, and the parallel signal of conversion gained separately is transferred to two DDR elements; And

One DDR to QDR data converter changes into the employed serial signal of QDR element with the data-signal of two DDR elements, and transfers to the QDR element according to the serial signal that the order of this instruction control unit will be changed gained.

3. the conversion equipment of DDR as claimed in claim 1 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, obtain QM signal and DQS signal that the QDR element is transmitted, the QM signal is changed into DDR QM signal and exports the DDR element to, transfer the DQS signal to the QDR element extracts data to the DDR element a data extract signal, and in the time must returning the DQS signal, produce the DQS signal of passback according to these clock signals of two times to the QDR element;

4. the conversion equipment of DDR as claimed in claim 1 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One phase-locked loop is used for receiving this clock signal, and the generation frequency is a built-in function clock signal of this clock signal frequency twice;

One data mask and detection controller, be used for obtaining a QM signal and the DQS signal of this QDR, this QM signal is changed into a DDR QM signal and inputs to this DDR element, transfer this DQS signal to this QDR element extracts data to this DDR element a data extract signal, and in the time must returning this DQS signal, produce the DQS signal of passback according to this built-in function clock signal to this QDR element;

One QDR to DDR data converter becomes a parallel signal with a serial conversion of signals of this QDR element, and according to the order of this instruction control unit, and this parallel signal of conversion gained separately is transferred to two these DDR elements; And

One DDR to QDR data converter changes into employed this serial signal of this QDR element with the data-signal of two these DDR elements, and transfers to this QDR element according to this serial signal that the order of this instruction control unit will be changed gained.

5. the conversion equipment of DDR and QDR, be applicable between a QDR interface element and the ddr interface element, it is characterized by: this QDR interface element is used for carrying out signal exchange with a QDR element, and this ddr interface element is used for carrying out signal exchange with a DDR element, and this conversion equipment comprises:

One clock controller is used for receiving the clock signal that this QDR element is exported, and converts the employed clock signal of this conversion equipment to;

One instruction control unit after being used for obtaining a QDR command signal of this QDR element, is processed into a corresponding DDR command signal with this QDR command signal, and exports this DDR element to; And

One DTU (Data Transfer unit), be couple to this QDR interface element, this ddr interface element and this instruction control unit, a control signal of exporting according to this instruction control unit, the data kenel that is applicable to this QDR element is converted to the data kenel that is applicable to this DDR element, and will be applicable to that the data kenel of this DDR element is converted to the data kenel that is applicable to this QDR.

6. the conversion equipment of DDR as claimed in claim 5 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, be used for obtaining a QM signal and a DQS signal of this QDR element, this QM signal is changed into a DDR QM signal that is applicable to this DDR element and exports this DDR element to, and transfer the DQS signal to this QDR element extracts data to this DDR element a data extract signal;

One QDR to DDR data converter will be become a parallel signal by the serial conversion of signals that this QDR element is exported, and according to the order of this instruction control unit, and this parallel signal of conversion gained is transferred to those DDR elements; And

One DDR to QDR data converter changes into employed this serial signal of this QDR element with the data-signal of those DDR elements, and transfers to this QDR element according to this serial signal that the order of this instruction control unit will be changed gained.

7. the conversion equipment of DDR as claimed in claim 5 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One data mask and detection controller, be used for obtaining a QM signal and the DQS signal that this QDR element is transmitted, this QM signal is changed into a DDRQM signal that is applicable to this DDR element and exports this DDR element to, transfer this DQS signal to this QDR element extracts data to this DDR element a data extract signal, and in the time must returning this DQS signal, produce this DQS signal of passback according to these clock signals of two times to the QDR element;

One QDR to DDR data converter, the serial conversion of signals that this QDR element is exported become a parallel signal, and according to the order of this instruction control unit, and the parallel signal of conversion gained separately is transferred to those DDR elements; And

8. the conversion equipment of DDR as claimed in claim 5 and QDR is characterized by: this DTU (Data Transfer unit) comprises:

One phase-locked loop receives this clock signal, and produces the passback clock signal that frequency is this clock signal frequency twice;

One data mask and detection controller, be used for obtaining QM signal and the DQS signal of this QDR, the QM signal is changed into DDR QM signal and inputs to the DDR element, transfer the DQS signal to the QDR element extracts data to the DDR element a data extract signal, and in the time must returning the DQS signal, produce the DQS signal of passback according to this passback clock signal to the QDR element;

9. the conversion equipment of DDR and QDR is characterized by: comprising:

One ddr interface element is used for carrying out signal exchange with the DDR element; And

One conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, reach the DDR element by this ddr interface element, and, reach the QDR element by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

10. an adapter that uses the conversion equipment of DDR and QDR is applicable on the circuit board of supporting the QDR module, it is characterized by: have a chipset of supporting QDR on this circuit board at least, this adapter comprises at least:

At least one DDR modular matrix; And

The conversion equipment of one DDR and QDR comprises:

One QDR interface element is used for carrying out signal exchange with this chipset;

One ddr interface element is used for carrying out signal exchange with this DDR modular matrix;

One conversion core parts, instruction and data mode with instruction and the data mode of QDR converts DDR to are sent to this DDR modular matrix by this ddr interface element,

And the instruction and the data mode that convert instruction and the data mode of DDR to QDR,

Be sent to this chipset of supporting QDR by this QDR interface element.

11. a mainboard that uses the conversion equipment of DDR and QDR is characterized by: comprising:

Chipset supports to use the QDR module; And

The conversion equipment of one DDR and QDR comprises:

At least one DDR DIMM;

The conversion equipment of one DDR and QDR comprises a QDR interface element, is used for carrying out signal exchange with this chipset; One ddr interface element is used for carrying out signal exchange with this DDR DIMM; Reach conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this DDR DIMM by this ddr interface element, and, be sent to this chipset by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

12. a memory modules that uses the conversion equipment of DDR and QDR is applicable to that it is characterized by: this memory modules comprises on the internal memory of supporting the QDR memory modules:

At least one DDR memory chip group matrix; And

The conversion equipment of one DDR and QDR comprises a QDR interface element, carries out signal exchange with this internal memory; One ddr interface element carries out signal exchange with this DDR memory chip group matrix; Reach conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this DDR memory chip group matrix by this ddr interface element, and, be sent to this internal memory by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

13. a memory module interface that uses the conversion equipment of DDR and QDR is characterized by: comprising:

At least one DDR DIMM; And

The conversion equipment of one DDR and QDR comprises a QDR interface element, carries out signal exchange with this memory module interfaces; One ddr interface element carries out signal exchange with this DDR DIMM; Reach conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this DDR DIMM by this ddr interface element, and, be sent to this memory module interfaces by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.

14. a portable computer mainboard that uses the conversion equipment of DDR and QDR is characterized by: comprising:

One chipset supports to use the QDR module; And

The conversion equipment of one DDR and QDR comprises a QDR interface element, is used for carrying out signal exchange with this chipset; One ddr interface element provides at least one SO-DIMM slot; One conversion core parts, the instruction and the data mode that convert instruction and the data mode of QDR to DDR, be sent to this SO-DIMM slot by this ddr interface element, and, be sent to this chipset by this QDR interface element with instruction and data mode that instruction and the data mode of DDR converts QDR to.