CN1393923A - Process for preparing double metal inlaid structure - Google Patents
Process for preparing double metal inlaid structure Download PDFInfo
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- CN1393923A CN1393923A CN 01129593 CN01129593A CN1393923A CN 1393923 A CN1393923 A CN 1393923A CN 01129593 CN01129593 CN 01129593 CN 01129593 A CN01129593 A CN 01129593A CN 1393923 A CN1393923 A CN 1393923A
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Abstract
The invention relates to the method for manufacturing the structure of the doubling metal mosaic. The barrier layer and the crystal seed layer are formed on the doubling metal mosaic openig of the semiconductor structure so as to cover the opening. Then, the protection layer is formed on the crystal seed layer to fill in the opening. With the crystal seed layer being as the terminated layer of the etching process, the eatback is carried out on the protection layer. Next, the exposed copper crystal seed layer is removed, and the protection layer is totally removed. Finally, the metal layer is formed on the doubling metal mosaic opening, and fills in the opening.
Description
The invention relates to the method for a kind of manufacturing metal interconnecting (Interconnects), and particularly relevant for the manufacture method of a kind of dual-metal inserting (Dual Damascene) structure.
In the development of semi-conductor industry, the raising of element arithmetic speed is the main points of development always, simultaneously also is the important indicator of consumer when selecting.Along with the fast development of integrated circuit technology, influencing at present in the factor of speed with the resistance value of lead itself and the parasitic capacitance size of interlayer dielectric layer is conclusive key.Wherein, reduce the influence of lead resistance, can select the metal material of low resistance for use; And improve the parasitic capacitance of interlayer dielectric layer, then can adopt the material of low-k, as the insulating barrier between the multiple layer metal line.
Typical metal interconnecting technology is to form metal plug in dielectric layer, forms the aluminum metal lead that is connected with metal plug again in substrate.And the technology of dual-metal inserting is a kind of have high-reliability and metal wire manufacturing technology cheaply, and the material of its employed metal interconnecting is not subjected to the restriction of metal etch.Therefore this technology has been widely used in the making of copper conductor, reduces the resistance value of lead itself with this, and then improves the speed and the quality of integrated circuit component.And along with element heights integrated after, make double-metal inlaid structure with the dielectric layer of low-k, become a kind of mode that the metal interconnecting technology of semi-conductor industry is adopted gradually.
Known dual-metal inserting technology is to form dielectric layer in substrate mostly, forms a pair of heavy metal then and inlay opening in dielectric layer, metallic copper is inserted this dual-metal inserting opening again, carries out planarization with cmp at last.Said method is in the back segment step, can use chemical mechanical milling tech, but well-known chemical mechanical milling tech can produce comprise surperficial indentation (scratch), peel off (rip off), residual particles (particleresidue), copper district depression (dishing), corrode (erosion) removal, prevent the oxide layer on copper surface and to the problems such as control of copper diffusion in the cleaning process behind the cmp, and the defective that chemical mechanical milling tech caused, also can cause qualification rate loss and reliability problems.
Therefore, the invention provides a kind of manufacture method of double-metal inlaid structure, can avoid the use of Semiconductor Chemistry mechanical lapping.
The present invention proposes a kind of manufacture method of double-metal inlaid structure.The method is to have a pair of heavy metal one to inlay formation one deck barrier layer (BarrierLayer) on the semiconductor structure of opening, and covers this dual-metal inserting opening; On barrier layer, form one deck crystal seed layer (Seed-layer) again, and cover this barrier layer surface; On this crystal seed layer, form layer protective layer (Sacrificial Layer) again, and fill up this dual-metal inserting opening; And be that etch stop layer eat-backs (etch-back) to protective layer with the crystal seed layer; Then remove the crystal seed layer that exposes, remove protective layer more fully, in the dual-metal inserting opening, form a metal level at last and fill up this dual-metal inserting opening, to form double-metal inlaid structure.Because use the mode of etching and filling to make double-metal inlaid structure, thus need not use chemical mechanical milling method, and the defective of avoiding it to cause.
The present invention be utilize protective layer with the dual-metal inserting of making the semiconductor rear section step to avoid the use of Semiconductor Chemistry mechanical lapping, the method also can be used for back segment step (BackEnd of Line, BEOL) making of intraconnections.Because it is general with the method for copper as the intraconnections material, all need to utilize chemical mechanical milling tech to do the processing of planarization, therefore can't can run into the problem that cmp produces with avoiding, for example surperficial indentation, peel off, residual particles, copper district depression, erosion, copper surface generation oxide layer and to the problems such as diffusion of copper ion in the cleaning process behind the cmp.So the present invention avoids the use of cmp, can prevent the generation of above-mentioned variety of issue, therefore can guarantee that dual-metal inserting can not run into every problem of coming from cmp because of using chemical mechanical milling tech, and then increase qualification rate, reach desired reliability.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. elaborate:
The drawing explanation:
Figure 1A to Fig. 1 G is a kind of manufacturing process generalized section of making double-metal inlaid structure of preferred embodiment of the present invention.Description of reference numerals:
100: substrate
102a, 102b: dielectric layer with low dielectric constant
104: etch stop layer
106: cover curtain layer
108: the dual-metal inserting opening
110: barrier layer
112: crystal seed layer
114,114a: protective layer
116: metal level
Embodiment:
Figure 1A to Fig. 1 G is the manufacturing process generalized section of a kind of dual-metal inserting (DualDamascene) structure of preferred embodiment of the present invention, and the method can be used for back segment step (Back End of Line, the BEOL) making of intraconnections.
Please refer to Figure 1A, one substrate 100 is provided, and in substrate 100, form one deck dielectric layer with low dielectric constant 102a, one deck etch stop layer 104, one deck dielectric layer with low dielectric constant 102b and one deck cover curtain layer 106 successively, with as semiconductor structure, wherein the material of cover curtain layer 106 can be silicon nitride, carborundum, boron nitride.Then, in substrate 100, form a dual-metal inserting opening 108.The manufacture method of typical dual-metal inserting opening 108 can be to form one deck photoresist layer (not painting on the figure) earlier on cover curtain layer 106 earlier, defines this photoresist layer then and carries out etching, to form an interlayer hole in dielectric layer with low dielectric constant 102a, 102b.After removing above-mentioned photoresist layer, then on cover curtain layer 106, form another layer photoresist layer (not painting on the figure) again, define this photoresist layer then and be etched to etch stop layer 104 to form a raceway groove, this raceway groove is positioned at the interlayer hole top, can form dual-metal inserting opening 108.
Then, please refer to Figure 1B.Deposition one deck barrier layer (Barrier Layer) 110 deposits one deck crystal seed layer (Seed-layer) 112 again on the surface of dual-metal inserting opening 108 and cover curtain layer 106, to cover the surface of barrier layer 110.The formation method of crystal seed layer 112 can be chemical vapour deposition technique (Physical Vapor Deposition, PVD) or physical vaporous deposition (Chemical Vapor Deposition, CVD), its material can be a copper.
Then, please refer to Fig. 1 C, form layer protective layer (Sacrificial Layer) 114 with covering crystal seed layer 112 surfaces, and fill up dual-metal inserting opening 108.The material of protective layer 114 need have preferable ditch and fill out ability (Gapfill), for example be boron-phosphorosilicate glass (BoronPhosphorus Silica Glass, BPSG).
Subsequently, please refer to Fig. 1 D, as etch stop layer, utilize the method for eat-backing (etch-back) to remove dual-metal inserting opening 108 unnecessary protective layer 114 in addition with crystal seed layer 112.After eat-backing, crystal seed layer 112 can come out, and in dual-metal inserting opening 108 matcoveredn 114a.
Then, please refer to Fig. 1 E, remove dual-metal inserting opening 108 part crystal seed layer 112 in addition, the method for wherein removing crystal seed layer 112 can be a Wet-type etching, and employed etching solution is a for example sulfuric acid solution of acid solution.Because after the crystal seed layer 112 beyond the dual-metal inserting opening 108 is removed, the step that can make later use electroplate (Plating) formation metal level becomes and has selectivity, therefore can reach the purpose that does not need chemical mechanical milling tech.
Then, please refer to Fig. 1 F, remove the protective layer 114a in the dual-metal inserting opening 108, to expose the copper crystal seed layer 112 on dual-metal inserting opening 108 surfaces.Wherein removing the method for protective layer 114a, can be to wait tropism's dry-etching, utilizes hydrogen fluoride gas (Vapor HF) as etching gas.Have the fast and high advantage of etching selectivity of etch-rate because tropism's dry-etchings such as utilization are removed protective layer 114a, so the process time is shorter, and copper crystal seed layer 112 is difficult for being etched.
At last, please refer to Fig. 1 G, form a metal level 116 and fill up this dual-metal inserting opening 108 in dual-metal inserting opening 108, the method that forms metal level 116 can be to electroplate, and its material can be a copper.
The present invention is because utilize the protective layer that is filled in the dual-metal inserting opening; and use the mode of etching and filling to make double-metal inlaid structure; using chemical mechanical milling method in the dual-metal inserting step of avoiding semiconductor rear section, and the method also can be used for the making of back segment in-process line.This is because general with the method for copper as the intraconnections material, need utilize chemical mechanical milling tech to do the processing of planarization, therefore can't can meet with that cmp produced with avoiding, for example surperficial indentation, peel off, residual particles, copper district depression, erosion, copper surface generation oxide layer and to the problems such as diffusion of copper ion in the cleaning process behind the cmp.So the present invention avoids the use of cmp, can prevent the generation of above-mentioned variety of issue, therefore can guarantee that dual-metal inserting can not meet with every problem of coming from cmp because of using chemical mechanical milling tech, and then improve qualification rate, reach desired reliability.
Though the present invention with a preferred embodiment openly as above; but it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; a little that done changed and retouching; all do not break away from protection scope of the present invention, and protection scope of the present invention should be with being as the criterion that claims were limited.
Claims (13)
1. the manufacture method of a double-metal inlaid structure, it is characterized in that: this method comprises:
Semiconductor structure is provided;
On this semiconductor structure, form a cover curtain layer;
On this semiconductor structure, form a pair of heavy metal and inlay opening;
On this semiconductor structure, form a barrier layer and cover this dual-metal inserting opening;
Forming a crystal seed layer on this semiconductor structure and covering on this barrier layer;
On this semiconductor structure, form a protective layer, fill up this dual-metal inserting opening, and cover on the surface of this crystal seed layer above this cover curtain layer with covering;
Utilization eat-back and with this crystal seed layer as etch stop layer, remove this protective layer of part, to expose this crystal seed layer of this cover curtain layer top;
Remove this dual-metal inserting opening this crystal seed layer of part in addition;
Remove this protective layer fully;
Utilize galvanoplastic on this crystal seed layer, to form a metal level,, form this double-metal inlaid structure to fill up this dual-metal inserting opening.
2. the manufacture method of double-metal inlaid structure according to claim 1, it is characterized in that: the material of this protective layer comprises boron-phosphorosilicate glass.
3. the manufacture method of double-metal inlaid structure according to claim 1 is characterized in that: the method for removing this protective layer fully such as comprises at tropism's dry-etching method.
4. the manufacture method of double-metal inlaid structure according to claim 3, it is characterized in that: the method for removing this protective layer fully comprises utilizes hydrogen fluoride gas as reacting gas.
5. the manufacture method of double-metal inlaid structure according to claim 1 is characterized in that: the method that forms this crystal seed layer comprise physical vaporous deposition and chemical vapour deposition technique one of them.
6. the manufacture method of double-metal inlaid structure according to claim 1 is characterized in that: the method for removing this crystal seed layer of part beyond this dual-metal inserting opening comprises a wet etching.
The manufacture method of 7 double-metal inlaid structures according to claim 6 is characterized in that: the employed solution of this wet etching comprises acid solution.
8. the manufacture method of a double-metal inlaid structure, it is characterized in that: this method comprises:
In a substrate, form a dielectric layer with low dielectric constant, and on this dielectric layer with low dielectric constant surface, form a cover curtain layer;
Among this dielectric layer with low dielectric constant and this cover curtain layer, form a pair of heavy metal and inlay opening;
In this substrate, form a barrier layer and cover this dual-metal inserting opening;
Forming a bronze medal crystal seed layer in this substrate and covering on this barrier layer;
In this substrate, form a protective layer and fill up this dual-metal inserting opening;
Utilization eat-back and with this copper crystal seed layer as etch stop layer, remove this protective layer of part;
Remove this dual-metal inserting opening this copper crystal seed layer of part in addition;
Utilize first-class tropism's dry-etching method to remove this protective layer fully;
Utilize galvanoplastic on this copper crystal seed layer, to form metallic copper and fill up this dual-metal inserting opening, to form this double-metal inlaid structure.
9. the manufacture method of double-metal inlaid structure according to claim 8, it is characterized in that: the material of this protective layer comprises boron-phosphorosilicate glass.
10. the manufacture method of double-metal inlaid structure according to claim 8, it is characterized in that: the employed reacting gas of these tropism's dry-etching methods comprises hydrogen fluoride gas.
11. the manufacture method of double-metal inlaid structure according to claim 8 is characterized in that: the method that forms this copper crystal seed layer comprise physical vaporous deposition and chemical vapour deposition technique one of them.
12. the manufacture method of double-metal inlaid structure according to claim 8 is characterized in that: the method for removing this dual-metal inserting opening this copper crystal seed layer of part in addition comprises a wet etching.
13. the manufacture method of double-metal inlaid structure according to claim 12 is characterized in that: the employed solution of this wet etching comprises acid solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01129593 CN1208819C (en) | 2001-06-28 | 2001-06-28 | Process for preparing double metal inlaid structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01129593 CN1208819C (en) | 2001-06-28 | 2001-06-28 | Process for preparing double metal inlaid structure |
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| Publication Number | Publication Date |
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| CN1393923A true CN1393923A (en) | 2003-01-29 |
| CN1208819C CN1208819C (en) | 2005-06-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01129593 Expired - Lifetime CN1208819C (en) | 2001-06-28 | 2001-06-28 | Process for preparing double metal inlaid structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101651117B (en) * | 2008-08-14 | 2011-06-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Metal copper filling method used in Damascus interconnecting process |
| CN103943599A (en) * | 2013-01-17 | 2014-07-23 | 中国科学院微电子研究所 | Interconnection structure and manufacture method thereof |
-
2001
- 2001-06-28 CN CN 01129593 patent/CN1208819C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101651117B (en) * | 2008-08-14 | 2011-06-15 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Metal copper filling method used in Damascus interconnecting process |
| CN103943599A (en) * | 2013-01-17 | 2014-07-23 | 中国科学院微电子研究所 | Interconnection structure and manufacture method thereof |
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| Publication number | Publication date |
|---|---|
| CN1208819C (en) | 2005-06-29 |
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