CN1392741A - Turbine code decoder for logarithmic compression-expansion code and its realizing method - Google Patents
Turbine code decoder for logarithmic compression-expansion code and its realizing method Download PDFInfo
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Abstract
A logarithm componding coded Turbo code decoder and its realizing method feature that the decoder comprises two channel decoders, two interleavers, two deinterleaves, demultiplex circuit, judgement devices and three memories. Imput/output ends of the said three memories are set up with circuit units of logarithm compressed and expanded coding to the input and outupt sequential signals of the corresponded memory respectively. The said three memories are used to store the received sequence by loyarithm compressed code during the said decoders processing the sequential signals, the outer information sequence after logarithm compressed coding and interleaving, output by the first decoder and outer information sequence via logarithm compressed coding and interleaving output by the second one.
Description
Affiliated field
The present invention relates to turbine (Turbo) code decoder of a kind of logarithmic companding coding, and the implementation method of this decoder, belong to the technical field of channel decoding system.
Background technology
The channel decoding technology is widely used in communication system, and for example in numerous technical fields such as mobile communication, satellite communication, interstellar communication and disk, optical disc storage Data Detection, the channel decoding device all is one of most important parts.Turbine (Turbo) sign indicating number is a kind of channel decoding with super error correction ability that eighties of last century occurred since the nineties, since turbine (Turbo) sign indicating number is suggested, has been used widely rapidly.Current various standards (W-CDMA (Wideband Code Division Multiple Access (WCDMA) for example at 3G (Third Generation) Moblie, the standard that Europe and Japan use), CDMA-2000 (standard that use the North America) and TD-SCDMA (TD SDMA, the standard that China uses)) in, for the transmission of high-speed data service, all adopted Turbo code.In addition, US National Aeronautics and Space Administration with Turbo code as the standard channel coding techniques of communicating by letter between space shuttle, spaceship and space station from now on and the earth receiving station.
Traditional turbine (Turbo) code decoder structure as shown in Figure 1.This decoder is made up of 1,2, two interleavers of two channel decoders, two deinterleavers and the basic elements of character such as memory, decision device.Traditional turbine (Turbo) code decoder adopts uniform quantization for receiving sequence and external information sequence, and turbine (Turbo) code decoder needs huge memory space, and therefore, its hardware resource that takies is extremely huge.Suppose that r (k) quantizes receiving sequence, discrete time mark k=1 wherein, 2 ....;
Be channel reliability tolerance, wherein E
sThe coded representation symbol energy, N
0Be one-sided power spectrum density.λ
U(k) receiving sequence of expression uniform quantization, Ax (k), Ay
1(k), Ay
2(k) and Ax
p(k) represent Turbo (turbine) yard system coding sequence, first via check code sequence, the second road check code sequence that obtains behind the demultiplexing and the sequence of passing through the arrangement that interweaves respectively.
(k),
(k) represent the external information uniform quantization sequence that decoder 1,2 is exported respectively; Then the decode procedure of conventional decoder mainly may further comprise the steps:
(1) receiving sequence r (k) and channel reliability tolerance
Multiply each other, obtain the receiving sequence λ of uniform quantization
U(k);
(2) to receiving sequence λ
U(k) carry out the serial to parallel conversion demultiplexing, obtain three parallel subsequence Ax (k), Ay
1(k) and Ay
2(k), wherein Ax (k), Ay
1(k) and Ay
2(k) represent system coding sequence, first via check code sequence and the second road check code sequence of Turbo (turbine) sign indicating number respectively;
(3) with system coding sequence A x (k) and first via verification sequence Ay
1(k) send into decoder 1, the sequence A x after system coding sequence process is interweaved
p(k) and the second tunnel verification sequence Ay
2(k) send into decoder 2;
(4) decoder 1 obtains system coding sequence A x (k), first via verification sequence Ay
1(k) and the external information sequence sent here of decoder 2
(k), begin to carry out channel decoding and handle through the sequence after the deinterleaving;
(5) the likelihood ratio sequence of decoder 1 output deducts respectively
(k) and behind the Ax (k), obtain the external information sequence of the uniform quantization of decoder 1
(k);
(6) decoder 2 obtains the external information sequence of above-mentioned steps (5)
(k), the system coding sequence A x after interweaving
p(k) and the second road check code sequence A y
2(k) after, begin to carry out channel decoding and handle;
(7) the likelihood ratio sequence of decoder 2 outputs deducts the external information sequence of decoder 1 respectively
(k) and the system coding sequence A x after interweaving
p(k) after, obtain the external information sequence of the uniform quantization of decoder 2
(k), through sending into decoder 1 after deinterleaving and the storage;
(8) order execution in step (3)-(7) respectively once are called iteration one time; Repeated execution of steps (3)-(7) promptly stop through deciphering after the iterative cycles repeatedly; For the first time the initialization condition during iteration is the external information sequence of decoder 1,2
(k),
(k) be 0;
(9) after decoding stopped, the likelihood ratio sequence of decoder 2 outputs was sent into deinterleaver, and the sequence after handling through deinterleaving is sent into decision device again, finally obtains deciphering output sequence.
Owing to could begin decoding after turbine (Turbo) code decoder need be stored receiving sequence fully, and the reconciliation interlace operation that interweaves that will carry out external information between two decoders, also need the external information sequence is stored fully just and can be carried out, therefore traditional Turbo code decoder needs huge memory space.For example, establish Turbo code data frame length N=5000, code rate R=1/3 adopts 6 bit quantizations to receiving sequence, and externally information sequence adopts 10 bit quantizations, and then the required memory space of decoder is at least 3N * 6+2N * 10=1.9 * 10
5A bit! So huge memory space has seriously limited applying of Turbo (turbine) code decoder, so how the insider addresses this problem seeking.
Summary of the invention
The purpose of this invention is to provide a kind of turbine (Turbo) code decoder of logarithmic companding coding, this decoder has added the circuit unit of log-compressed and expansion on the structure of conventional decoder, thereby can reduce memory space, reduces the consumption of hardware resource.
Another object of the present invention provides a kind of implementation method of turbine (Turbo) code decoder of logarithmic companding coding.
Turbine (Turbo) code decoder of logarithmic companding coding of the present invention is achieved in that a kind of turbine (Turbo) code decoder of logarithmic companding coding, include: by two channel decoders, two interleavers, two deinterleavers, demultiplexing circuit, decision device and three turbine (Turbo) code decoders that memory is formed, these three memories are respectively applied at this decoder and handle storage uniform quantization receiving sequence λ in the sequence signal process
UThe external information sequence of the uniform quantization after (k), the process of first decoder output interweaves
(k) and the external information sequence of the uniform quantization of second decoder output
(k); It is characterized in that: the input and output side at described three memories is provided with the circuit unit that the sequence signal of this corresponding stored device of input and output is carried out log-compressed coding and logarithm extended coding respectively; Wherein to the external information sequence of the uniform quantization of first decoder output
(k) circuit unit that carries out log-compressed coding is arranged on the input of its interleaver, and to the external information sequence of the uniform quantization of second decoder output
(k) circuit unit that carries out the logarithm extended coding is arranged on the output of the deinterleaver that is connected with this memory output, and described three memories are respectively applied at this decoder and handle in the sequence signal process storage through the receiving sequence λ of log-compressed coding
C(k), process the log-compressed of first decoder output encode and interweave after the external information sequence
(k) and process the log-compressed of second decoder output external information sequence of encoding
(k).
The logarithmic companding function that the log-compressed coding in the described decoder and the circuit unit of extended coding are used is Log-Map (logarithm maximum posteriori decoding) computational methods, or SOVA (soft output Viterbi decoding) computational methods.
Turbine (Turbo) code decoder of described logarithmic companding coding is realized with field programmable gate array FpGA (Field programmable Gate Array) integrated circuit (IC) chip, or is made with application-specific integrated circuit ASIC (Application Specific Integrated Circuit) chip.
Described decoder is applied to WCDMA or CDMA2000 or TD-SCDMA system, and in satellite communication and the aerospace communication system.
Another object of the present invention is achieved in that a kind of implementation method of turbine (Turbo) code decoder of logarithmic companding coding, it is characterized in that: comprise the steps: at least
(1) will quantize receiving sequence r (k) (discrete time mark k=1 wherein, 2 ... .) with channel reliability tolerance
(E wherein
sThe coded representation symbol energy, N
0Be one-sided power spectrum density) processing of multiplying each other, obtain the receiving sequence λ of uniform quantization
U(k);
(2) with λ
U(k) send into log compression circuit unit f
ICarry out log-compressed and handle, obtain the sequence λ after the uniform quantization receiving sequence log-compressed
C(k), the log compression function that adopted of log compression circuit unit is f
ISequence λ after will compressing then
C(k) write memory is to save the space of memory; (3) from memory, read sequence λ after the compression
C(k), send into logarithm expanded circuit unit
Carry out the logarithm expansion, obtain the sequence λ after logarithm is expanded
E(k), the logarithm spread function that adopted of logarithm expanded circuit unit is the inverse transform function of log-compressed
(4) with logarithm sequence spreading λ
E(k) carry out the serial to parallel conversion demultiplexing, obtain three parallel subsequence Ax (k), Ay
1(k) and Ay
2(k); This three sub-sequence A x (k), Ay
1(k) and Ay
2(k) represent system coding sequence, first via check code sequence and the second road check code sequence of turbine (Turbo) sign indicating number respectively;
(5) respectively with system coding sequence A x (k) and first via verification sequence Ay
1(k) send into first decoder, and with the system coding sequence through the sequence A x after interweaving
p(k) and the second tunnel verification sequence Ay
2(k) send into second decoder;
(6) first decoder is obtaining system coding sequence A x (k), first via verification sequence Ay
1(k) and the external information sequence of second decoder output
(k) after, begin to carry out channel decoding and handle;
(7) the likelihood ratio sequence of first decoder output is deducted after the log-compressed of external information sequence of second decoder sequence of expansion more respectively
(k) and after the processing of system coding sequence A x (k), obtain the external information sequence of the uniform quantization of first decoder
(k);
(8) with above-mentioned external information sequence
(k) send into log compression circuit unit f
ECarry out log-compressed and handle, obtain compressed sequence
(k), the log compression function that adopted of log compression circuit unit is f
EPress the interleaving mode write memory again, to save storage space;
(9) from this memory, read compressed sequence
(k), send into logarithm expanded circuit unit again
After carrying out the logarithm expansion, sequence is expanded
(k), the logarithm expansion adopted of logarithm expanded circuit unit is the inverse transform function of log-compressed
Afterwards with sequence spreading
(k) send into second decoder as external information;
(10) second decoders obtain the external information sequence of logarithm expansion
(k), the system coding sequence A x after interweaving
p(k) and the second road check code sequence A y
2(k) after, begin to decipher processing; (11) the likelihood ratio sequence of second decoder output is deducted after the log-compressed of external information sequence of first decoder the sequence of expansion more respectively
(k) and the system coding sequence A x after interweaving
P(k) after the processing, obtain the uniform quantization external information sequence of second decoder
(k);
(12) the uniform quantization external information sequence that second decoder exported
(k) carry out obtaining compressed sequence after log-compressed handles
(k), the log compression function that is adopted is f
E, again by deinterleaving mode write memory, to save storage space;
(13) from this memory, read compressed sequence
(k), through after the logarithm expansion, sequence is expanded again
(k), the logarithm expansion of being adopted is the inverse transform function of log compression function
Afterwards with sequence spreading
(k) send into first decoder as external information;
(14) order is carried out above-mentioned steps (6)-(13) respectively once, is called iteration one time; Repeat above-mentioned steps (6)-(13), promptly stop through deciphering after the iteration repeatedly; For the first time the initialization condition during iteration is the external information sequence of first decoder and second decoder
(k) and
(k) be 0;
(15) the output likelihood ratio sequence of second decoder is sent into deinterleaver, the sequence after will handling through deinterleaving is again sent into decision device, obtains the output sequence of this decoder.
Through loop iteration repeatedly, just can obtain decode results in the described decoder operating procedure; Wherein the number of times of iterative cycles is 1 time at least, also can be the repeatedly iteration more than 2 times or 2 times; Iterations depends on the different requirements of decoding delay and hardware complexity.
In the described step (2) to the receiving sequence signal λ of uniform quantization
UWhen (k) carrying out the log-compressed processing, the accurate companding function that is adopted is g
I:
In the formula: the receiving sequence λ of uniform quantization
U(k) be expressed as (n
I, p
I), n wherein
IBe effective bit wide of data, p
IBe the precision bit of data, then its represented number range be (
); Effective bit wide n of common receiving sequence
IValue n
I=5,6,7,8, precision bit p
IValue p
I=2,3; Companding parameter M
IBe by (n
I, p
I) decision empirical value.
Realizing accurate logarithmic companding function g with hardware
IThe time, the companding function f of employing sectional broken line
IThe accurate logarithmic companding function of close approximation g
I: promptly use the piecewise approximation function f
IApproach accurate function g
I, use the piecewise approximation inverse function
Approach accurate function g
IInverse function; And receiving sequence λ when uniform quantization
U(k) be expressed as (n
I, p
I) time, data width n wherein
IWith data precision p
ICan get various numerical value, with corresponding to different approximate log compression function f
IAnd spread function
When externally information signal sequence carried out the log-compressed processing in described step (8) and (12), the accurate logarithmic companding function that is adopted was g
E:
In the formula: the external information sequence of uniform quantization
(k) (i=1,2) are expressed as (n
E, p
E), n wherein
EBe effective bit wide of data, p
EBe the precision bit of data, then its represented number range is: (
); Effective bit wide n of common external information sequence
EValue n
E=7,8,9,10,11,12, precision bit p
EValue p
E=2,3; Companding parameter M
EBe by (n
E, p
E) decision empirical value.
Realizing accurate logarithmic companding function g with hardware
EThe time, the companding function f of employing sectional broken line
EThe accurate logarithmic companding function of close approximation g
E: promptly use the piecewise approximation function f
EApproach accurate function g
E, use the piecewise approximation inverse function
Approach accurate function g
EInverse function; And when the external information sequence table of uniform quantization is shown (n
E, p
E) time, data width n wherein
EWith data precision p
ECan get various numerical value, with corresponding to different approximate log compression function f
EAnd spread function
Turbine (Turbo) code decoder of logarithmic companding coding proposed by the invention, be in traditional turbine (Turbo) code decoder circuit structure, to add log compression circuit unit and logarithm expanded circuit unit, greatly reduced the memory space of sequence signal, make that the hardware resource of decoder is greatly saved, kept identical decoding performance simultaneously.The present invention provides the implementation method of this turbine (Turbo) code decoder simultaneously.Relatively find out from the computer simulation curve performance of infinite precision shown in Figure 5 (Infinite), traditional uniform quantization (Uniform) and logarithmic companding coding (Companding) three kinds of modes: no matter be the error rate (BER) or frame error rate (FER) characteristic, uniform quantization is almost consistent with the performance that logarithmic companding is encoded; But owing to adopted the logarithmic companding coding, the memory space of decoder of the present invention has reduced γ=1-(4 * 5+2 * 6)/(4 * 6+2 * 10)=27.27%, the memory space of promptly having saved about 1/4-1/3 than traditional uniform quantization decoder.
Description of drawings
Fig. 1 is the structural representation of traditional turbine (Turbo) code decoder.
Fig. 2 is the structural representation of turbine (Turbo) code decoder of logarithmic companding coding of the present invention.
Fig. 3 is an embodiment schematic diagram that in turbine (Turbo) code decoder of logarithmic companding of the present invention coding receiving sequence is carried out the Function Mapping relation of log-compressed and expansion.
Fig. 4 be in turbine (Turbo) code decoder of logarithmic companding of the present invention coding externally information sequence carry out an embodiment schematic diagram of the Function Mapping relation of log-compressed and expansion.
Fig. 5 (A), (B) are respectively that turbine (Turbo) code decoder of logarithmic companding coding of the present invention is the error rate (being abbreviated as BER) curve chart and frame error rate (the being abbreviated as FER) curve chart that emulation enforcement obtains under the random interleaving condition at interleaving mode.(simulated conditions is: receiving sequence adopts 6 Bit data width, 2 Bit data precision, the external information sequence adopts 10 Bit data width, 2 Bit data precision, and adopt iteration 6 times, BPSK (binary phase shift keying) modulation system, frame length is 1000 symbols)
Embodiment
Referring to Fig. 2, the present invention is a kind of turbine (Turbo) code decoder of logarithmic companding coding, include: by two channel decoders, two interleavers, two deinterleavers, demultiplexing circuit, decision device and three turbine (Turbo) code decoders that memory is formed, these three memories are respectively applied at this decoder and handle storage uniform quantization receiving sequence λ in the sequence signal process
UThe external information sequence of the uniform quantization after (k), the process of first decoder output interweaves
(k) and the external information sequence of the uniform quantization of second decoder output
(k); The difference part of itself and conventional decoder is: the input and output side at described three memories is provided with the circuit unit f that the sequence signal of this corresponding stored device of input and output is carried out log-compressed coding and logarithm extended coding respectively
IWith
, and f
EWith
Wherein to the external information sequence of the uniform quantization of first decoder 1 output
(k) carry out the circuit unit f that log-compressed is encoded
EBe arranged on the input of its interleaver, and to the external information sequence of the uniform quantization of second decoder 2 output
(k) carry out the circuit unit of logarithm extended coding
Be arranged on the output of the deinterleaver that is connected with this memory output; And described three memories are respectively applied at this decoder and handle the receiving sequence λ that storage is encoded through log-compressed in the sequence signal process
C(k), process the log-compressed of first decoder output encode and interweave after the external information sequence
(k) and process the log-compressed of second decoder output external information sequence of encoding
(k).
The logarithmic companding function that logarithmic companding circuit unit in turbine (Turbo) code decoder of logarithmic companding coding of the present invention is used is Log-Map (logarithm maximum posteriori decoding) computational methods, or SOVA (soft output Viterbi decoding) computational methods.This decoder is realized with on-site programmable gate array FPGA (FieldProgrammable Gate Array) integrated circuit (IC) chip, or is made with application-specific integrated circuit ASIC (Application Specific Integrated Circuit) chip.This decoder is applied to WCDMA or CDMA2000 or TD-SCDMA system, and in satellite communication and the aerospace communication system.
Turbine (Turbo) code decoder of logarithmic companding coding of the present invention is to the receiving sequence signal λ of uniform quantization
UWhen (k) carrying out the log-compressed processing, the accurate companding function that is adopted is g
I:
In the formula: the receiving sequence λ of uniform quantization
U(k) be expressed as (n
I, p
I), n wherein
IBe effective bit wide of data, p
IBe the precision bit of data, then its represented number range be (
); Effective bit wide n of common receiving sequence
IValue n
I=5,6,7,8, precision bit p
IValue p
I=2,3; Companding parameter M
IBe by (n
I, p
I) decision empirical value.Data width n wherein
IWith data precision p
ICan get various numerical value, with corresponding to different log compression function f
IAnd spread function
Realizing accurate logarithmic companding function g with hardware
IThe time, the companding function f of employing sectional broken line
IThe accurate logarithmic companding function of close approximation g
I: promptly use the piecewise approximation function f
IApproach accurate function g
I, use the piecewise approximation inverse function
Approach accurate function g
IInverse function; And receiving sequence λ when uniform quantization
U(k) be expressed as (n
I, p
I) time, data width n wherein
IWith data precision p
ICan get various numerical value, with corresponding to different approximate log compression function f
IAnd spread function
When the external information signal sequence of turbine (Turbo) code decoder of logarithmic companding coding of the present invention carried out the log-compressed processing, the accurate logarithmic companding function that is adopted was g
E:
In the formula: the external information sequence of uniform quantization
(k) (i=1,2) are expressed as (n
E, p
E), n wherein
EBe effective bit wide of data, p
EBe the precision bit of data, then its represented number range is: (
); Effective bit wide n of common external information sequence
EValue n
E=7,8,9,10,11,12, precision bit p
EValue p
E=2,3; Companding parameter M
EBe by (n
E, p
E) decision empirical value.Realizing accurate logarithmic companding function g with hardware
EThe time, the companding function f of employing sectional broken line
EThe accurate logarithmic companding function of close approximation g
E: promptly use the piecewise approximation function f
EApproach accurate function g
E, use the piecewise approximation inverse function
Approach accurate function g
EInverse function; And when the external information sequence table of uniform quantization is shown (n
E, p
E) time, data width n wherein
EWith data precision p
ECan get various numerical value, with corresponding to different approximate log compression function f
EAnd spread function
Turbine (Turbo) code decoder that logarithmic companding coding of the present invention is described respectively below in conjunction with two embodiment is to receiving sequence and the log-compressed of outer sequence employing and the implementation method of expansion.
Referring to Fig. 3, turbine (Turbo) code decoder of logarithmic companding coding of the present invention has adopted log-compressed and expansion to receiving sequence.This log-compressed and expansion are achieved in that the receiving sequence λ that establishes uniform quantization
U(k) be expressed as (n
I, p
I), n in the formula
IBe effective bit wide of data, p
IBe the precision bit of data, then its represented number range be (
)。(n for example
I, p
I)=(6,2), the expression data width is 6 bits, and ratio of precision is specially for 2 bits, so the number range that it characterized is (8,7.75).The log-compressed of receiving sequence and spread function f
IAnd
Be to use piecewise approximation, below with (n
I, p
I)=(6,2) if implementation procedure for example explanation compression and expansion comprises the steps: (1) at least 4≤λ
U(k)＜8, the sequence 3/4≤λ that then obtains after the log-compressed
C(k)＜1, carry out Linear Mapping for the result in the data area according to broken line 33;
(2) if 2≤λ
U(k)＜4, the sequence 1/2≤λ that then obtains after the log-compressed
C(k)＜3/4, carry out Linear Mapping for the result in the data area according to broken line 32;
(3) if 1≤λ
U(k)＜2, the sequence 1/4≤λ that then obtains after the log-compressed
C(k)＜1/2, carry out Linear Mapping for the result in the data area according to broken line 31;
(4) if 0≤λ
U(k)＜1, the sequence 0≤λ that then obtains after the log-compressed
C(k)＜1/4, carry out Linear Mapping for the result in the data area according to broken line 30;
(5) if λ
U(k)＜0, then-λ
U(k)＞0, carry out log-compressed again after promptly the data of uniform quantization being taken absolute value; After obtaining compression result, add the polarity bit in highest order again.That is to say-8≤λ
U(k)＜-4 the log-compressed scope of correspondence is-1≤λ
C(k)＜-3/4;-4≤λ
U(k)＜-2 the log-compressed scope of correspondence is-3/4≤λ
C(k)＜-1/2;-2≤λ
U(k)＜-1 the log-compressed scope of correspondence is-1/2≤λ
C(k)＜-1/4;-1≤λ
U(k)＜0 the log-compressed scope of correspondence is-1/4≤λ
C(k)＜0;
(6) if 3/4≤λ
C(k)＜1, the sequence 4≤λ that then obtains after the logarithm expansion
E(k)＜8, carry out the linear inverse mapping for the result in the data area according to broken line 33;
(7) if 1/2≤λ
C(k)＜3/4, the sequence 2≤λ that then obtains after the logarithm expansion
E(k)＜4, carry out the linear inverse mapping for the result in the data area according to broken line 32;
(8) if 1/4≤λ
C(k)＜1/2, the sequence 1≤λ that then obtains after the logarithm expansion
E(k)＜2, carry out the linear inverse mapping for the result in the data area according to broken line 31;
(9) if 0≤λ
C(k)＜1/4, the sequence 0≤λ that then obtains after the logarithm expansion
E(k)＜1, carry out the linear inverse mapping for the result in the data area according to broken line 30;
(10) if λ
C(k)＜0, then-λ
C(k)＞0, carry out the logarithm expansion after promptly the data after the log-compressed being taken absolute value again, behind the result that is expanded, add the polarity bit in highest order again; That is to say-8≤λ
C(k)＜-4 the logarithm spreading range of correspondence is-1≤λ
E(k)＜-3/4;-4≤λ
C(k)＜-2 the logarithm spreading range of correspondence is-3/4≤λ
E(k)＜-1/2;-2≤λ
C(k)＜-1 the logarithm spreading range of correspondence is-1/2≤λ
E(k)＜-1/4;-1≤λ
C(k)＜0 the logarithm spreading range of correspondence is-1/4≤λ
E(k)＜0.
Referring to Fig. 4, the external information sequence of turbine (Turbo) code decoder of logarithmic companding coding of the present invention has adopted log-compressed and expansion.This log-compressed and expansion are achieved in that the external information sequence of establishing uniform quantization
(k) (i=1,2) are expressed as (n
E, p
E), n wherein
EBe effective bit wide of data, p
EBe the precision bit of data, then its represented number range be (
)。(n for example
E, p
E)=(10,2), the expression data width is 10 bits, and ratio of precision is specially for 2 bits, so the number range that it characterized is (128,127.75).The log-compressed of receiving sequence and spread function f
EAnd
Be to use piecewise approximation, below with (n
E, p
E)=(10,2) for illustrating compression and expansion process, example comprises the steps (i=1,2) at least:
(1) if 64≤
(k)＜128, the sequence 7/8 that then obtains after the log-compressed≤
(k)＜1, carry out Linear Mapping for the result in the data area according to broken line 47;
(2) if 32≤
(k)＜64, the sequence 3/4 that then obtains after the log-compressed≤
(k)＜7/8, carry out Linear Mapping for the result in the data area according to broken line 46;
(3) if 16≤
(k)＜32, the sequence 5/8 that then obtains after the log-compressed≤
(k)＜3/4, carry out Linear Mapping for the result in the data area according to broken line 45;
(4) if 8≤
(k)＜16, the sequence 1/2 that then obtains after the log-compressed≤
(k)＜5/8, carry out Linear Mapping for the result in the data area according to broken line 44;
(5) if 4≤
(k)＜8, the sequence 3/8 that then obtains after the log-compressed≤
(k)＜1/2, carry out Linear Mapping for the result in the data area according to broken line 43;
(6) if 2≤
(k)＜4, the sequence 1/4 that then obtains after the log-compressed≤
(k)＜3/8, carry out Linear Mapping for the result in the data area according to broken line 42;
(7) if 1≤
(k)＜2, the sequence 1/8 that then obtains after the log-compressed≤
(k)＜1/4, carry out Linear Mapping for the result in the data area according to broken line 41;
(8) if 0≤
(k)＜1, the sequence 0 that then obtains after the log-compressed≤
(k)＜1/8, carry out Linear Mapping for the result in the data area according to broken line 40;
(9) if
(k)＜0, then-
(k)＞0, carry out log-compressed again after promptly the extrinsic information data of uniform quantization being taken absolute value, after obtaining compression result, add the polarity bit in highest order again; That is to say ,-128≤
(k)＜-64 the log-compressed scope of correspondence be-1≤
(k)＜-7/8;-64≤
(k)＜-32 the log-compressed scope of correspondence be-7/8≤
(k)＜-3/4;-32≤
(k)＜-16 the log-compressed scope of correspondence be-3/4≤
(k)＜-5/8;-16≤
(k)＜-8 the log-compressed scope of correspondence be-5/8≤
(k)＜-1/2;-8≤
(k)＜-4 the log-compressed scope of correspondence be-1/2≤
(k)＜-3/8;-4≤
(k)＜-2 the log-compressed scope of correspondence be-3/8≤
(k)＜-1/4;-2≤
(k)＜-1 the log-compressed scope of correspondence be-1/4≤
(k)＜-1/8;-1≤
(k)＜0 the log-compressed scope of correspondence be-1/8≤
(k)＜0;
(10) if 7/8≤
(k)＜1, the sequence 64 that then obtains after the logarithm expansion≤
(k)＜128, carry out the linear inverse mapping for the result in the data area according to broken line 47;
(11) if 3/4≤
(k)＜7/8, the sequence 32 that then obtains after the logarithm expansion≤
(k)＜64, carry out the linear inverse mapping for the result in the data area according to broken line 46;
(12) if 5/8≤
(k)＜3/4, the sequence 16 that then obtains after the logarithm expansion≤
(k)＜32, carry out the linear inverse mapping for the result in the data area according to broken line 45;
(13) if 1/2≤
(k)＜5/8, the sequence 8 that then obtains after the logarithm expansion≤
(k)＜16, carry out the linear inverse mapping for the result in the data area according to broken line 44;
(14) if 3/8≤
(k)＜1/2, the sequence 4 that then obtains after the logarithm expansion≤
(k)＜8, carry out the linear inverse mapping for the result in the data area according to broken line 43;
(15) if 1/4≤
(k)＜3/8, the sequence 2 that then obtains after the logarithm expansion≤
(k)＜4, carry out the linear inverse mapping for the result in the data area according to broken line 42;
(16) if 1/8≤
(k)＜1/4, the sequence 1 that then obtains after the logarithm expansion≤
(k)＜2, carry out the linear inverse mapping for the result in the data area according to broken line 41;
(17) if 0≤
(k)＜1/8, the sequence 0 that then obtains after the logarithm expansion≤
(k)＜1, carry out the linear inverse mapping for the result in the data area according to broken line 40;
(18) if
(k)＜0, then-
(k)＞0, carry out the logarithm expansion after promptly the extrinsic information data of log-compressed takes absolute value again, behind the result that is expanded, add the polarity bit in highest order again.That is to say ,-1≤
(k)＜-7/8 the logarithm spreading range of correspondence be-128≤
(k)＜-64;-7/8≤
(k)＜-3/4 the logarithm spreading range of correspondence be-64≤
(k)＜-32;-3/4≤
(k)＜-5/8 the logarithm spreading range of correspondence be-32≤
(k)＜-16;-5/8≤
(k)＜-1/2 the logarithm spreading range of correspondence be-16≤
(k)＜-8;-1/2≤
(k)＜-3/8 the logarithm spreading range of correspondence be-8≤
(k)＜-4;-3/8≤
(k)＜-1/4 the logarithm spreading range of correspondence be-4≤
(k)＜-2;-1/4≤
(k)＜-1/8 the logarithm spreading range of correspondence be-2≤
(k)＜-1;-1/8≤
(k)＜0 the logarithm spreading range of correspondence be-1≤
(k)＜0.
For turbine (Turbo) code decoder of logarithmic companding coding of the present invention, the inventor utilizes on-site programmable gate array FPGA (the Field Programmable Gate Array) integrated circuit (IC) chip of VirtexII series to design and implements it.Its main design parameter is as follows: receiving sequence adopts 6 bit quantizations, 2 Bit data precision, and external information adopts 10 bit quantizations, 2 Bit data precision.Use turbine (Turbo) the code decoder structure of Verilog language description logarithmic companding coding, re-use Synplify software and carry out comprehensively, the ISE software with Xilinx company carries out sequential emulation, wiring and chip programming at last.The result of the test that above-mentioned development is implemented should be to have realized goal of the invention preferably as shown in Figure 5.
Claims (10)
1, a kind of turbine (Turbo) code decoder of logarithmic companding coding, include: by two channel decoders, two interleavers, two deinterleavers, demultiplexing circuit, decision device and three turbine (Turbo) code decoders that memory is formed, these three memories are respectively applied at this decoder and handle storage uniform quantization receiving sequence λ in the sequence signal process
UThe external information sequence of the uniform quantization after (K), the process of first decoder output interweaves
(k) and the external information sequence of the uniform quantization of second decoder output
(k); It is characterized in that: the input and output side at described three memories is provided with the circuit unit that the sequence signal of this corresponding stored device of input and output is carried out log-compressed coding and logarithm extended coding respectively; Wherein to the external information sequence of the uniform quantization of first decoder output
(k) circuit unit that carries out log-compressed coding is arranged on the input of its interleaver, and to the external information sequence of the uniform quantization of second decoder output
(k) circuit unit that carries out the logarithm extended coding is arranged on the output of the deinterleaver that is connected with this memory output, described three memories be respectively applied for this decoder handle storage in the sequence signal process encode through process the log-compressed of the receiving sequence λ C (k) of log-compressed coding, first decoder output and interweave after the external information sequence
(k) and process the log-compressed of second decoder output external information sequence of encoding
(k).
2, turbine (Turbo) code decoder of logarithmic companding coding according to claim 1, it is characterized in that: the logarithmic companding function that the log-compressed coding in the described decoder and the circuit unit of extended coding are used is Log-Map (logarithm maximum posteriori decoding) computational methods, or SOVA (soft output Viterbi decoding) computational methods.
3, turbine (Turbo) code decoder of encoding according to logarithmic companding as claimed in claim 1, it is characterized in that: turbine (Turbo) code decoder of described logarithmic companding coding is realized with the on-site programmable gate array FPGA integrated circuit (IC) chip, or is made with the application-specific integrated circuit ASIC chip.
4, turbine (Turbo) code decoder of logarithmic companding coding according to claim 1, it is characterized in that: described decoder is applied to WCDMA or CDMA2000 or TD-SCDMA system, and in satellite communication and the aerospace communication system.
5, a kind of implementation method of turbine (Turbo) code decoder of logarithmic companding coding is characterized in that: comprise the steps: at least
(1) will quantize receiving sequence r (k) (discrete time mark k=1 wherein, 2 ... .) with channel reliability tolerance
(E wherein
sThe coded representation symbol energy, N
0Be one-sided power spectrum density) processing of multiplying each other, obtain the receiving sequence λ of uniform quantization
U(k);
(2) with λ
U(k) send into log compression circuit unit f
ICarry out log-compressed and handle, obtain the sequence λ after the uniform quantization receiving sequence log-compressed
C(k), the log compression function that adopted of log compression circuit unit is f
ISequence λ after will compressing then
C(k) write memory is to save the space of memory;
(3) from memory, read sequence λ after the compression
C(k), send into logarithm expanded circuit unit
Carry out the logarithm expansion, obtain the sequence λ after logarithm is expanded
E(k), the logarithm spread function that adopted of logarithm expanded circuit unit is the inverse transform function of log-compressed
(4) with logarithm sequence spreading λ
E(k) carry out the serial to parallel conversion demultiplexing, obtain three parallel subsequence Ax (k), Ay
1(k) and Ay
2(k); This three sub-sequence A x (k), Ay
1(k) and Ay
2(k) represent system coding sequence, first via check code sequence and the second road check code sequence of turbine (Turbo) sign indicating number respectively;
(5) respectively with system coding sequence A x (k) and first via verification sequence Ay
1(k) send into first decoder, and with the system coding sequence through the sequence A x after interweaving
p(k) and the second tunnel verification sequence Ay
2(k) send into second decoder;
(6) first decoder is obtaining system coding sequence A x (k), first via verification sequence Ay
1(k) and the external information sequence of second decoder output
(k) after, begin to carry out channel decoding and handle;
(7) the likelihood ratio sequence of first decoder output is deducted after the log-compressed of external information sequence of second decoder sequence of expansion more respectively
(k) and after the processing of system coding sequence A x (k), obtain the external information sequence of the uniform quantization of first decoder
(k);
(8) with above-mentioned external information sequence
(k) send into log compression circuit unit f
ECarry out log-compressed and handle, obtain compressed sequence
(k), the log compression function that adopted of log compression circuit unit is f
EPress the interleaving mode write memory again;
(9) from this memory, read compressed sequence
(k), send into logarithm expanded circuit unit again
After carrying out the logarithm expansion, sequence is expanded
(k), the logarithm expansion adopted of logarithm expanded circuit unit is the inverse transform function of log-compressed
Afterwards with sequence spreading
(k) send into second decoder as external information;
(10) second decoders obtain the external information sequence of logarithm expansion
(k), the system coding sequence A x after interweaving
p(k) and the second road check code sequence A y
2(k) after, begin to decipher processing;
(11) the likelihood ratio sequence of second decoder output is deducted after the log-compressed of external information sequence of first decoder the sequence of expansion more respectively
(k) and the system coding sequence A x after interweaving
p(k) after the processing, obtain the uniform quantization external information sequence of second decoder
(k);
(12) the uniform quantization external information sequence that second decoder exported
(k) carry out obtaining compressed sequence after log-compressed handles
(k), the log compression function that is adopted is f
E, again by deinterleaving mode write memory;
(13) from this memory, read compressed sequence
(k), through after the logarithm expansion, sequence is expanded again
(k), the logarithm expansion of being adopted is the inverse transform function of log compression function
Afterwards with sequence spreading
(k) send into first decoder as external information;
(14) order is carried out above-mentioned steps (6)-(13) respectively once, is called iteration one time; Repeat above-mentioned steps (6)-(13), promptly stop through deciphering after the iteration repeatedly; For the first time the initialization condition during iteration is the external information sequence of first decoder and second decoder
(k) and
(k) be 0;
(15) the output likelihood ratio sequence of second decoder is sent into deinterleaver, the sequence after will handling through deinterleaving is again sent into decision device, obtains the output sequence of this decoder.
6, the implementation method of turbine (Turbo) code decoder of logarithmic companding according to claim 5 coding is characterized in that: through loop iteration repeatedly, just can obtain decode results in the described decoder operating procedure; Wherein the number of times of iterative cycles is 1 time at least, also can be the repeatedly iteration more than 2 times or 2 times; Iterations depends on the different requirements of decoding delay and hardware complexity.
7, the implementation method of turbine (Turbo) code decoder of logarithmic companding according to claim 5 coding is characterized in that: in the described step (2) to the receiving sequence signal λ of uniform quantization
UWhen (k) carrying out the log-compressed processing, the accurate companding function that is adopted is g
I:
In the formula: the receiving sequence λ of uniform quantization
U(k) be expressed as (n
I, p
I), n wherein
IBe effective bit wide of data, p
IBe the precision bit of data, then its represented number range be (
); Effective bit wide n of common receiving sequence
IValue n
I=5,6,7,8, precision bit p
IValue p
I=2,3; Companding parameter M
IBe by (n
I, p
I) decision empirical value.
8, according to the implementation method of turbine (Turbo) code decoder of claim 5 or 7 described logarithmic compandings coding, it is characterized in that: realizing accurate logarithmic companding function g with hardware
IThe time, the companding function f of employing sectional broken line
IThe accurate logarithmic companding function of close approximation g
I: promptly use the piecewise approximation function f
IApproach accurate function g
I, use the piecewise approximation inverse function
Approach accurate function g
IInverse function; And receiving sequence λ when uniform quantization
U(k) be expressed as (n
I, p
I) time, data width n wherein
IWith data precision p
ICan get various numerical value, with corresponding to different approximate log compression function f
IAnd spread function
9, the implementation method of turbine (Turbo) code decoder of logarithmic companding coding according to claim 5, it is characterized in that: when externally information signal sequence carried out the log-compressed processing in described step (8) and (12), the accurate logarithmic companding function that is adopted was g
E:
In the formula: the external information sequence of uniform quantization
(k) (i=1,2) are expressed as (n
E, p
E), n wherein
EBe effective bit wide of data, p
EBe the precision bit of data, then its represented number range is: (
); Effective bit wide n of common external information sequence
EValue n
E=7,8,9,10,11,12, precision bit p
EValue p
E=2,3; Companding parameter M
EBe by (n
E, p
E) decision empirical value.
10, according to the implementation method of turbine (Turbo) code decoder of claim 5 or 9 described logarithmic compandings coding, it is characterized in that: realizing accurate logarithmic companding function g with hardware
EThe time, the companding function f of employing sectional broken line
EThe accurate logarithmic companding function of close approximation g
E: promptly use the piecewise approximation function f
EApproach accurate function g
E, use the piecewise approximation inverse function
Approach accurate function g
EInverse function; And when the external information sequence table of uniform quantization is shown (n
E, p
E) time, data width n wherein
EWith data precision p
ECan get various numerical value, with corresponding to different approximate log compression function f
EAnd spread function
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