WO2014194761A1

WO2014194761A1 - Soft bit coding method and apparatus for radio receiving device

Info

Publication number: WO2014194761A1
Application number: PCT/CN2014/078051
Authority: WO
Inventors: 刘中伟; 李钦昕; 邱宁; 邢艳楠
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-06-05
Filing date: 2014-05-21
Publication date: 2014-12-11
Also published as: CN104218956A; CN104218956B

Abstract

A soft bit coding method and apparatus for a radio receiving device. The method comprises: during downlink processing, compressing to-be-coded Mbit soft bit data to obtain compressed Nbit soft bit data; and performing follow-up soft bit coding processing on the compressed Nbit soft bit data, M and N being positive integers and M being greater than N. By means of the method and the apparatus, during soft bit data coding of a radio receiving device, by slightly reducing performance, soft bit data of a cache is reduced, so that the size of the cache is reduced and the area of a chip of the radio receiving device is significantly reduced.

Description

TECHNICAL FIELD The present invention relates to a soft bit decoding technology suitable for a wireless receiving device, and more particularly to a soft bit decoding method and related device for a wireless receiving device. BACKGROUND OF THE INVENTION In a digital communication system, a general error is unavoidable, and for a wireless communication system with poor communication conditions, the error condition is particularly serious, and reducing the bit error and improving the reliability of the communication system have always been pursued by the communication system design. One of the main goals. Channel coding is an error control technique developed to improve communication reliability, and mainly includes two types of error detection codes and error correction codes. Error correction codes are commonly used in channel coding, and error correction codes can be further divided into two categories: block codes and convolutional codes. The block code is a memoryless error correction code. At the receiving end, only the current n inputs can be used to correct the transmitted information bits, which are often recorded as (n, k) codes. Where n is the number of symbols of a codeword, that is, the codeword length, k is the number of information symbols, and n-k is the number of supervised symbols. The convolutional code is a memory error correction code. At the receiving end, not only the current n inputs but also the m bits and n bits received in the past can be used to estimate the currently transmitted information bits, which is denoted as (n, k). , m) code. The linear block code only uses the current code word information for error correction, and the convolutional code can simultaneously use the previous multiple code word information for error correction, and thus, the error correction capability of the convolutional code is much stronger. In a harsh wireless receiving system, a convolutional code is mainly used for channel coding. Commonly used convolutional codes include two types, one is a convolutional code in the usual sense, and the other is a turbo code, which is an improvement on a common convolutional code, that is, two convolutional codes are simultaneously used. The input of one of the convolutional codes is the interleaving of another convolutional code input.

The convolutional code encoder in the TD protocol is shown in Figure 1, with a constraint length of 9. Before starting the encoding, the initial values of the eight shift registers D of the encoder are set to all zeros, and eight bits 0 are added at the end of the input bits. When encoding, each beat performs the operation of "first mode plus two, then register shift". According to the 3G protocol, as a result of the code block segmentation, the maximum input data amount encoded by the convolutional encoder at one time is 504 bits. The function of the Viterbi Viterbi decoder is to perform decoding of the 1/2 convolutional code and the 1/3 convolutional code. The Viterbi decoding algorithm is a maximum likelihood decoding method proposed by Viterbi in 1967, that is, the output selected by the decoder always makes the codeword with the highest conditional probability of the received sequence. According to the principle of maximum likelihood decoding, one of the most suitable paths (the one with the smallest distance) is obtained in all possible paths, and the path backtracking is used to obtain the decision output. This method has been proved to have the best error correction decoding performance. . The Viterbi decoding algorithm is mainly composed of the "plus-selection" operation of the path metric, the update of the cumulative metric, and the backtracking of the maximum likelihood path.

The turbo code decoder is shown in Fig. 2. The input information sequences X YP ¹ and ΥΡ ² are formed by adding the channel noise to the encoder output sequences X, Χ ^{Ρ 1} and Χ ^Ρ ² , respectively. The input of decoder 1 is ^^ ¹ ), and the input of decoder 2 is K ₂ = (X YP ² ). The best decoding strategy for Turbo codes is to calculate the posterior probability? ( _3⁄4 | ^^ ₂ ), _3⁄4 = 0,1., high computational complexity. The practical scheme is to calculate P^ l ^ ) and P(u _k | K ₂ , i ) by the member decoder respectively, and obtain a suboptimal strategy that the decoding complexity is acceptable. By looping iterations, let them converge? ( _3⁄4 | ]^ ₂ ). This is the basic idea of iterative decoding: The decoding process of complex long codes is divided into several steps, and the probability (soft information) transfer between decoding steps is guaranteed to cause little loss of information. For Turbo codes, there are two main decoding schemes: one is the maximum a posteriori probability (MAP) series, including the MAP algorithm, the Log-MAP algorithm and the Max-Log-MAP algorithm; the other is the soft output Viterbi. Algorithm SOVA. MAP is the optimal decoding algorithm, but its disadvantage is that it has high computational complexity and requires a large storage space.

The performance of Log-MAP algorithm is close to that of MAP algorithm. It is a suboptimal decoding algorithm. Because the operation is transferred to the logarithmic domain, the multiplication operation is added to the addition operation, which greatly reduces the computational complexity. Max-Log The -MAP algorithm ignores the logarithmic component in the addition expression of the Log-MAP algorithm likelihood value, and adds the likelihood values to the maximum value operation, further reducing the computational complexity, and the performance is 0.3~0.5 dB lower than the MAP; The decoding performance of SOVA is the worst. It differs from the MAP algorithm by about 0.5~ldB, and as the signal-to-noise ratio increases, the difference does not decrease, but its computational complexity is low, which is beneficial to hardware implementation. The choice of Turbo decoding algorithm should consider the balance between performance and complexity. The Max-Log-MAP algorithm is usually used. For viterbi decoding and turbo decoding, there are two methods of hard decision and soft decision. Compared with the soft decision, the performance of the hard decision has a 2~3dB drop in performance. Obviously, the soft decision scheme is superior. However, the soft decision scheme is limited by the quantization bits of the hardware. The wider the quantization bits, the larger the RAM area required to hold the soft decision bits. Taking TD-SCDMA as an example, the general decoding process of the downlink is as shown in FIG. 3, including physical channel demapping, subframe splicing, second de-interleaving, physical channel splicing, de-bit scrambling, physical channel going. Multiplexing, reverse rate matching, wireless frame splicing, first de-interlacing, radio frame backward equalization, channel decoding, coding block splicing/transport block segmentation, CRC detection, etc. Due to the existence of the second deinterleaving and the first deinterleaving, the UE terminal of the TD-SCDMA must store the data demapped for one frame period and one radio frame, This means that the wider the bits of the soft bits used for viterbi decoding and turbo decoding, the larger the buffer required, and therefore the larger the chip area of the wireless receiving device. SUMMARY OF THE INVENTION Embodiments of the present invention provide a soft bit decoding method and apparatus for a wireless receiving device, which can better solve the problem of reducing the chip area of a wireless receiving device without substantially losing performance. According to an aspect of the embodiments of the present invention, a soft bit decoding method of a wireless receiving device is provided, including: compressing Mbit soft bit data to be decoded during downlink processing to obtain a compressed Nbit Soft bit data; performing subsequent soft bit decoding processing on the soft bit data of the compressed bit; wherein, M and N are positive integers, and M>N. Preferably, before the physical channel demapping process, the soft bit data of the Mbit to be decoded is compressed to obtain soft bit data of the compressed bit. In this case, the step of the subsequent soft bit decoding process includes: sequentially performing physical channel demapping processing, second deinterleaving processing, first deinterleaving processing, and decoding on the soft bit data of the compressed bit. deal with. Preferably, after the physical channel demapping process, the soft bit data of the Mbit to be decoded is compressed to obtain soft bit data of the compressed bit. In this case, the step of the subsequent soft bit decoding process includes: storing soft bit data of the compressed bit into a buffer; decompressing the soft bit data of the bit read from the buffer to obtain Mbit soft bit data, and sub-frame splicing processing of the Mbit soft bit data. The step of the subsequent soft bit decoding process further includes: performing compression processing on the Mbit soft bit data obtained by the splicing process of the sub-frame to obtain soft bit data of the compressed bit; And storing soft bit data of the compressed bit into a buffer; decompressing the soft bit data of the bit read from the buffer to obtain soft bit data of Mbit, and performing soft bit data of the Mbit The second de-interlacing process. The step of the subsequent soft bit decoding process further includes: performing line compression processing on the Mbit soft bit data obtained after the second deinterleave process to obtain a compressed

Nbit soft bit data; storing soft bit data of the compressed bit into a buffer; decompressing soft bit data of the bit read from the buffer to obtain Mbit soft bit data, and The Mbit soft bit data is subjected to the first deinterleaving process. Preferably, the step of compressing comprises: converting, by mapping, Mbit uniformly quantized soft bit data to obtain bit non-uniformly quantized soft bit data. Preferably, the step of decompressing comprises: converting, by inverse mapping, the bit non-uniformly quantized soft bit data read from the buffer to obtain Mbit uniformly quantized soft bit data. According to another aspect of the present invention, there is provided a decoding apparatus, comprising the above-described soft bit data buffer processing unit, configured to cache soft bit data obtained by soft decision processing after physical channel demapping processing . According to another aspect of the present invention, a soft bit decoding apparatus for a wireless receiving device is provided, comprising: a compression module configured to compress Mbit soft bit data to be decoded during downlink processing Processing, obtaining soft bit data of the compressed bit; the decoding module is configured to perform subsequent soft bit decoding processing on the soft bit data of the compressed bit; wherein, M and N are positive integers, and M>N. Compared with the prior art, the beneficial effects of the embodiments of the present invention are: The embodiment of the invention can reduce the number of bits used for soft bit decoding under the condition that the performance is basically no loss or the performance is slightly decreased (not more than 0.2 dB), thereby significantly reducing the chip area of the wireless receiving device, and effectively saving the baseband. The cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic structural diagram of a convolutional encoder in a TD protocol provided by the prior art; FIG. 2 is a schematic structural diagram of a Turbo code decoder provided by the prior art; FIG. 3 is a schematic diagram of a TD-SCDMA provided by the prior art. GDTR downlink decoding and non-multiplexing flowchart; FIG. 4 is a flowchart of a soft bit decoding method of a wireless receiving device according to an embodiment of the present invention; FIG. 5 is a soft bit decoding of a wireless receiving device according to an embodiment of the present invention; FIG. 6 is a schematic diagram of a comparison of quantized signal to noise ratios between linear domain decoding and transform domain decoding according to an embodiment of the present invention; FIG. 7 is an additive white Gaussian white noise AWGN channel according to an embodiment of the present invention; FIG. 8 is a schematic diagram showing the performance comparison between the 8-bit linear domain decoding and the 4-bit transform domain decoding of the fading channel Casel according to the embodiment of the present invention; FIG. 9 is a schematic diagram of performance comparison between the 8-bit linear domain decoding and the 4-bit transform domain decoding. A performance comparison diagram of 8-bit linear domain decoding and 4-bit transform domain decoding in the fading channel Casel provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. 4 is a flowchart of a method for decoding a soft bit of a wireless receiving device according to an embodiment of the present invention. As shown in FIG. 4, the method includes: Step 401: During the downlink processing, the soft bit data of the Mbit to be decoded is performed. Compression processing is performed to obtain compressed bit soft bit data, where M and N are positive integers, and M > N. Step 402: Perform subsequent soft bit decoding processing on the soft bit data of the compressed bit. When the foregoing step 401 is performed before the physical channel demapping process, the step of the subsequent soft bit decoding process in step 402 includes: performing physical channel demapping processing on the soft bit data of the compressed bit in sequence, Secondary deinterleave processing, first deinterleave processing, and decoding processing. That is, the wireless receiving device performs descrambling and despreading to obtain soft bit data of the Mbit to be decoded, and the embodiment of the present invention compresses the soft bit data of the Mbit to obtain soft bit data of the compressed bit. Subsequent includes physical channel demapping, subframe splicing, second de-interleaving, physical channel splicing, de-bit scrambling, physical channel demultiplexing, reverse rate matching, wireless frame splicing, first de-interlacing, wireless In the process of frame inverse equalization and the like, soft bit data of the compressed bit is used, that is, full compression-transformed soft bit decoding is realized. When the above step 401 is performed after the physical channel demapping process, the step of the subsequent soft bit decoding process in step 402 includes: storing the soft bit data of the compressed bit to a cache, and The read soft bit data of the bit is subjected to decompression processing to obtain Mbit soft bit data, so as to perform sub-frame splicing processing on the Mbit soft bit data. Then, compressing the soft bit data of the Mbit obtained after the splicing process of the sub-frame, obtaining soft bit data of the compressed bit, storing the soft bit data of the compressed bit into a buffer, and reading from the cache The soft bit data of the bit is decompressed to obtain Mbit soft bit data, and the Mbit soft bit data is subjected to a second deinterleaving process. Finally, the Mbit soft bit data obtained after the second deinterleaving process is subjected to line compression processing to obtain compressed bit soft bit data, and the compressed bit soft bit data is stored in the buffer, and the buffer is buffered. The soft bit data of the bit read is subjected to decompression processing to obtain Mbit soft bit data, and the Mbit soft bit data is subjected to a first deinterleave process. That is to say, it is only necessary to perform Mbit-to-bit compression and Nbit-to-Mbit decompression of the data to be cached after physical channel demapping, before the second de-interleaving, and before the first de-interleaving, thereby simplifying the implementation. Soft bit decoding process. The fully compressed compression soft bit decoding process requires the entire soft bit decoding process to be modified from Mbit to bit. The workload is large, and the simplified soft bit decoding process has a small amount of work, due to the physical channel. The area of the chip required for the mapping, the second deinterleaving, and the first deinterleaving is large. Therefore, the compression from Mbit to bit can significantly reduce the chip area. The step of the above compression processing includes: converting the Mbit uniformly quantized soft bit data by mapping to obtain bit non-uniformly quantized soft bit data. The step of decompressing the above-mentioned processing includes: converting, by inverse mapping, the bit non-uniformly quantized soft bit data read from the buffer to obtain Mbit uniformly quantized soft bit data. The above cache is a random access memory RAM. The embodiments of the present invention are applicable to soft bit decoding of a wireless receiving device, and are widely applicable to a decoding process of a convolutional code and a turbo code. The embodiment of the present invention further provides a soft bit decoding apparatus for a wireless receiving device, including: a compression module, configured to compress, during the downlink processing, the soft bit data of the Mbit to be decoded, to obtain a compressed The soft bit data of the bit, where M and N are positive integers, and >^^ _{; the} decoding module is configured to perform subsequent soft bit decoding processing on the soft bit data of the compressed bit. When full compression-transformed soft bit decoding is employed, the subsequent soft bit decoding process includes: physical channel demapping processing, subframe splicing processing, second de-interleaving processing, physical channel splicing processing, de-biting The processing of scrambling processing, physical channel demultiplexing processing, reverse rate matching processing, wireless frame splicing processing, first deinterleaving processing, and radio frame reverse equalization processing are performed using compressed bit soft bit data. deal with. When a simplified compression-transformed soft bit decoding is employed, the subsequent soft bit decoding process includes: data to be cached after physical channel demapping, before second deinterleaving, and before first deinterleaving The Mbit-to-bit compression is performed, and in the actual processing, after the bit-to-Mbit decompression is performed, the Mbit soft-bit data is used for corresponding processing. FIG. 5 is a schematic diagram of a cache processing structure of a wireless receiving device in a soft bit decoding process according to an embodiment of the present invention. As shown in FIG. 5, the method includes: a compression module Comp, which is set to be stored during downlink processing. The soft bit data of the Mbit is subjected to compression processing to obtain soft bit data of the compressed bit. The Comp converts the Mbit uniformly quantized soft bit data by mapping, and obtains bit non-uniformly quantized soft bit data to implement compression. a cache RAM, configured to store soft bit data of the compressed bit; and a decompression module De-Comp configured to decompress the soft bit data of the bit read from the buffer to obtain Mbit soft bit data . The De-Comp converts the bit non-uniformly quantized soft bit data read from the buffer by inverse mapping, and obtains Mbit uniformly quantized soft bit data to implement decompression. Where M and N are positive integers and M>N. The buffer processing structure described in FIG. 5 can be widely applied to a decoding device of DTR (Download Transport Processing), and the chip area is significantly reduced by reducing the number of bits used for buffering soft bit decoding, thereby significantly reducing the wireless receiving device. Chip area. The DTR process is a general term for the downlink processing process. For the TD-SCDMA system, it includes two branches: GDTR (General Download Transport Processing) and HDTR (HSDPA Download Transport Processing). The main purpose of the DTR process is to process the soft demodulated symbol data, decode and demultiplex the data, and pass it to the upper layer. The DTR process is closely related to the protocol standard and is the inverse of the physical layer coding and multiplexing. Channel coding implements forward error correction by convolutional codes and Turbo codes, so that error correction capability close to the scent limit can be obtained under the AWGN channel. However, under the fading channel, due to the deep fading of the channel and the influence of the burst interference, it may cause a concentration error within a certain period of time. In this case, the error correction code alone is powerless, and the solution is interleaving and retransmission. Interleaving and de-interleaving are commonly used as methods of combating fading in the process of channel coding and decoding of ordinary services. In the process of channel coding and decoding of HSDPA services, retransmission is used as a method of combating fading. Therefore, in the DTR link, de-interleaving and re-transmission are important steps, and the problem is that for soft demodulated data, a large storage space is required. Taking deinterleaving as an example, if a Transmission Time Interval (TTI) is 20 ms, data of 4 subframes of the service needs to be stored. If a frame is 40 ms, data of 8 subframes of the service needs to be stored. Subsequent decoding can only be performed after deinterleaving. This storage amount increases with the increase of the number of quantization bits for saving soft bit data. Assuming that one subframe needs to store 2000 data bits, then for 40 ms TTI, 16000 data needs to be stored in advance, if each data is represented by 8 bits, It requires 128,000 bits of storage space. If each data is represented by 4 bits, the required storage space can be reduced to half, and only 64,000 bits of storage space is needed. Determining the number of data storage bits in the DTR link is the requirement of the input soft bit bits for the vertibi decoder and the turbo decoder. Considering turbo soft bit decoding, the information bits are discriminated by log likelihood ratio, which is expressed as follows:

^L 2( u _k ) = L _c x _k + _e2 ( u _k ) + _a2 ( u _k ) where L ₂ ( u _k ) represents the output of the turbo decoder and x _k represents the uniformly quantized soft bit of the input, λ _ώ _(¾) represents the decoder after decoding this "net" decode information is to be passed to a first sub-decoder as its a priori information λ _3, _a2 (u _k) represents the current input to the decoder The log likelihood ratio of the probability is derived from the output of the second sub-decoder. The above formula shows, turbo decoder and a turbo decoder output decision input x _k is linear, ¾ L soft ₂ (u _k) is larger when the input bits, a greater redundancy, even if a certain quantizing Errors are not easy to cause false positives. When the soft bit input of L ₂ ( u _k ) is small, a small amount of error during quantization may cause misjudgment. Therefore, for demodulating soft bits, non-uniform quantization processing can be used, for larger inputs, coarser quantization, and for smaller inputs, fine quantization. That is, the DTR process can be shifted from the uniformly quantized linear domain to the non-uniform quantized transform domain. The above process can also be explained by quantizing the signal-to-noise ratio. As shown in Fig. 6, when the soft bit data is uniformly quantized, quantization noise is actually added. For uniform quantization, the quantization noise is fixed. When the value of the soft bit is large, the signal-to-noise ratio SNR ratio of the signal soft bit and the quantization noise is relatively large. When the value of the soft bit is small, correspondingly, the SNR ratio of the signal soft bit and the quantization noise is relatively small. For uniform quantization, when the value of the soft bit of the signal is large, the quantized SR can always satisfy the requirement, but when the value of the soft bit of the signal is small, the quantized SNR decreases greatly, even less than OdB, thereby causing soft bits. Decoding performance is degraded. The above-mentioned transform domain decoding, that is, non-uniform quantization, uses a larger quantization step size when the value of the soft bit of the signal is large, and uses a smaller quantization step when the value of the soft bit of the signal is small. Long, this ensures that the quantization SR decreases more flatly within the quantization interval. Therefore, it is ensured that the quantization SR is substantially unchanged throughout the quantization interval, and the subsequent channel decoding performance is guaranteed. Figure 6 shows an 8-bit->4bit transform domain decoding as an example. Line 1 is an 8-bit uniform quantization signal-to-noise ratio curve. The larger the absolute value of the input value, the higher the quantized signal-to-noise ratio, but due to the operating point of HSDPA. That is, 14 to 15 dB, a higher signal to noise ratio does not help the accuracy of soft demodulation. Line 2 is a 4-bit uniformly quantized signal-to-noise ratio curve. When the input value is small, the quantized signal-to-noise ratio is lower than the operating point of HSDPA, thus resulting in a large quantization error, which affects the accuracy of the final decoding. Line 3 is the signal-to-noise ratio curve of the 4-bit transform domain decoding. When the absolute value of the input value is large, a larger quantization interval is used. At this time, the quantization signal-to-noise ratio is close to 4 bit uniform quantization, but because it is higher than HSDPA. The point does not affect the decoding performance at this time; when the absolute value of the input value is small, a smaller quantization interval is used, and at this time, the quantization signal-to-noise ratio is close to the performance of 8-bit uniform quantization. Thus, the bit width of the soft bit demodulation link can be significantly reduced without substantially loss of decoding performance. To implement DTR transform domain decoding, a bit transform domain decoder can be used instead of the Mbit uniform quantization decoder, which is equivalent to modifying the Mbit decoding link in the DTR to a bit decoding link, that is, Vertibi decoding. Although the process and turbo decoding process still use the usual decoding algorithm, the input information is not uniformly quantized Mbit soft bit data, but the non-uniform quantized bit soft bit of the transform domain. After multiple iterations, the translation is performed. The output of the coder is judged, and finally 0, 1 bit is acquired. If the modification is based on the original Mbit link, the modification of the entire link may take a long time. The workaround is to maintain each processing module in the Mbit decoding link, and only occupy the occupied area of the DTR link. Larger RAM for encapsulation, Mbit to bit compression when demodulating soft bits are stored in RAM, When it is necessary to acquire the data stored in the RAM, the bit data in the RAM is mapped to the Mbit data by decompression, as shown in FIGS. 4 and 5. That is to say, when the data is stored in the RAM, the conversion of the soft-bit data of the Mbit uniform quantization to the bit non-uniform quantization transform domain is realized by mapping, and the data read from the RAM is used to realize the bit non-uniform quantization soft bit data by mapping. The conversion of soft bit data to Mbit uniformly quantized, thereby compressing the RAM overhead of the DTR link. The mapping process of the Mbit uniformly quantized soft bit data to the bit non-uniform quantization transform domain may be expressed by the following formula:

The formula says:

Where alpha is the probability value. The embodiments of the present invention are applicable to the GDTR and HDTR downlinks of the TD-SCDMA system. Since WCDMA has a GDTR and HDTR downlink procedure similar to TD-SCDMA, this scheme is also applicable to the WCDMA system. The core invention of the strategy is that in the channel decoding process of the wireless receiving device, the Mbit linear domain is converted to the bit transform domain for the uniformly quantized soft bits, M and N are configurable, and M is always greater than N. Thus, a significant reduction in chip cost is achieved with less performance degradation (not more than 0.2 dB). In the common viterbi decoding and turbo decoding scheme, the demapped soft bits use 8-bit uniformly quantized soft bit data. In the embodiment of the present invention, 4 bit transform domain decoding and 8 bit linear decoding are respectively used to perform performance simulation. As shown in FIG. 7 to FIG. 9 , the simulation results show that the performance of the two is basically equivalent, and the performance degradation is not more than 0.2 dB. It is shown that it is feasible to use a 4-bit transform domain decoding scheme instead of an 8-bit linear decoding scheme. The following is a comparison of the performance of the usual 8bit and 4bit schemes. In the baseband portion of the wireless receiving chip, the RAM occupies a large area, and the RAM in the downstream GDTR link and the downstream HDTR link usually occupies more than 80% of the chip RAM area. This means that by using the M->Nbit transform, taking the 8->4bit change as an example, the RAM area in the DTR link can be reduced by half, which is equivalent to reduction. 40% of the RAM area in the baseband chip, which means that using the transform domain decoding scheme, the chip area can be greatly reduced without loss of performance, thereby effectively saving the cost of the baseband chip. A simplified implementation method of transform domain decoding is described below by taking the transform domain decoding of the GDTR link for TD-SCDMA as an example. For a specific flowchart, reference may be made to FIG. 3. For the GDTR link of TD-SCDMA, the complete transform domain decoding method converts the received data symbols into non-linear soft bits after soft demodulation, and then uses the entire GDTR link. In the channel decoding, the channel decoding is performed on the bit scheme of the transform domain, and the last 0 and 1 bits are decoded. Considering the complexity of the link modification, it can be implemented in a simplified manner, that is, the DTR link structure is not greatly modified, and the Mbit linear decoding is still used, but only the larger RAM in the DTR link is encapsulated. In this way, modifications to the link can be minimized. Specifically, when Mbit soft bit data is stored in the RAM, it is mapped once, and Mbit soft bit data is mapped into bit soft bit data, and is stored in the RAM. When it is necessary to acquire data in the RAM, the bit soft bit data in the RAM is mapped to Mbit soft bit data by one mapping. In this way, most of the chip area can be saved, and the modification of the original linear link can be minimized. The specific implementation steps are as follows: Step 1. The physical channel demaps the physical channel to be mapped to the inverse process of the physical layer mapping, and the physical channel mapping rule can be reversely applied to recover the user's subframe data, and the chip-level operation is converted into a bit-level operation. . After the physical channel is demapped, the equalized received data is soft-decised and quantized into appropriate soft bit data for subsequent vertibi soft bit decoding and turbo soft bit decoding. The soft bit data after the soft decision is stored in the frame RAM, and can be compressed and decompressed in the aforementioned manner. That is to say, the soft bit data after the soft decision is stored in the frame RAM by compression, and the data read from the RAM is decompressed when subsequent processing is required. Step 2: Sub-frame splicing When the length of the coded combined transmission channel ΤΉ is greater than 5 ms, a subframe splicing unit needs to be added between the second de-interleaving unit and the physical channel demapping unit to splicing the two subframes. Sub-frame splicing only changes the order in which the input soft bits are stored, and does not change the value of the input soft bits. Step 3: The main purpose of the second deinterleaving interleaving is to turn the burst error into a random error, so that the decoder can perform error correction and resist the influence of fast fading. Regardless of the first interleaving or the second interleaving, both are rectangular interleavers, following the principles outlined in the travel. The purpose of the second deinterleaving is to restore the data of the second interleaving to the original order. The data needs to be stored in the second deinterleaving RAM before the second deinterleaving, and the second deinterleaving is performed.

The data in the RAM needs to be compressed and decompressed in the manner described above. That is, before the second deinterleaving, the soft bit data is compressed and stored in the second deinterleaving RAM, and when the second deinterleaving is required, the second deinterleaving RAM is read. The data is decompressed. Step 4: Physical channel splicing When there is multi-code transmission at the transmitting end, that is, when a code division combined transmission channel CCTrCH is transmitted by using multiple physical channels, the receiving end needs to use physical channel splicing, that is, several physical channels belonging to the same CCTrCH. The data is serially stitched together. The physical channel splicing only changes the storage location of the input soft bits, and does not change the value of the input soft bits. Step 5. De-bit scrambling The bit scrambling process is the inverse of the bit scrambling process, and the bit scrambling process is an input sequence.

Modulo 2 sum with the scrambling code sequence p _k . De-bit scrambling only changes the order in which the input soft bits are stored, and does not change the value of the input soft bits. Step 6. Demultiplexing the transport channel Demultiplexing The 10 ms radio frame data of one transport channel multiplexed on one CCTrCH is detached one by one and sent to the corresponding transport channel. The demultiplexing of the transport channel only changes the order in which the input soft bits are stored, and does not change the value of the input soft bits. Step 7. Reverse rate matching Reverse rate matching is to restore the data after the rate matching processing to the data before the rate matching. Reverse rate matching only changes the order in which the input soft bits are stored, and does not change the value of the input soft bits. Step 8. Wireless frame stitching When the transmission time interval (ΤΉ) of the transmission channel is greater than 10 ms, the 10 ms radio frames mapped to the transmission channel by the inverse rate matching module are spliced into one frame in the wireless frame splicing module. The wireless frame splicing only changes the storage order of the input soft bits, and does not change the value of the input soft bits. Step 9. The first deinterleaving restores the first interleaved data to the original order. The first deinterleaving only changes the order in which the input soft bits are stored, and does not change the value of the input soft bits. The data needs to be stored in the first deinterleaving AM before deinterleaving, and the data in the first deinterleaving RAM needs to be compressed and decompressed in the foregoing manner. That is, before the first deinterleaving, the soft bit data is compressed and stored in the first deinterleaving RAM, and when the first deinterleaving is required, the first deinterleaving RAM is read. The data is decompressed. Step 10: Radio frame reverse equalization The radio frame reverse equalization process is the inverse process of the radio frame equalization process, and the reverse radio frame equalization rule can be used to recover the user data before the radio frame equalization. Radio frame reverse equalization only changes the order in which the input soft bits are stored, and does not change the value of the input soft bits. Step 1 1. Channel decoding Channel decoding is the inverse process of channel coding. Commonly used channel codes mainly include convolutional codes and turbo codes. Channel decoding mainly uses Viterbi decoding and MAX-LOG-MAP algorithm. After the compression and decompression processing in steps 1, 3 and 9, the Vertibi decoding process and the turbo decoding process still use the usual decoding algorithm, and the input information is still 8-bit soft bit data. After multiple iterations, The output of the decoder is judged, and finally 0, 1 bit is acquired. In summary, the embodiment of the present invention can greatly reduce the area of the wireless receiving chip under the condition that the performance is not substantially affected, thereby effectively saving the cost of the baseband chip. Although the invention has been described in detail above, the invention is not limited thereto, and various modifications may be made by those skilled in the art in accordance with the principles of the invention. Therefore, modifications made in accordance with the principles of the invention should be construed as falling within the scope of the invention. INDUSTRIAL APPLICABILITY As described above, a soft bit decoding method and apparatus for a wireless receiving device provided by an embodiment of the present invention have the following beneficial effects: the wireless receiving chip area can be greatly reduced without substantially affecting performance. Effectively save the cost of baseband chips.

Claims

Claims, a soft bit decoding method for a wireless receiving device, comprising:

During the downlink processing, the soft bit data of the Mbit to be decoded is compressed to obtain soft bit data of the compressed bit;

Subsequent soft bit decoding processing is performed on the soft bit data of the compressed bit; wherein M and N are positive integers, and M > The method according to claim 1, wherein before the physical channel demapping process, the soft bit data of the Mbit to be decoded is compressed to obtain soft bit data of the compressed bit. The method according to claim 2, wherein the step of the subsequent soft bit decoding process comprises: sequentially performing physical channel demapping processing, second deinterleaving processing, and soft decoding on the compressed bit soft bit data, The first deinterleaving process and the decoding process. The method according to claim 1, wherein after the physical channel demapping process, the soft bit data of the Mbit to be decoded is compressed to obtain soft bit data of the compressed bit. The method according to claim 4, wherein the step of the subsequent soft bit decoding process comprises: storing soft bit data of the compressed bit to a cache;

The soft bit data of the bit read from the buffer is subjected to decompression processing to obtain Mbit soft bit data, and sub-frame splicing processing is performed on the Mbit soft bit data. The method of claim 5, wherein the step of the subsequent soft bit decoding process further comprises:

Performing compression processing on the soft bit data of the Mbit obtained after the splicing process of the subframe to obtain soft bit data of the compressed bit;

Storing the soft bit data of the compressed bit to a cache;

The soft bit data of the bit read from the buffer is subjected to decompression processing to obtain Mbit soft bit data, and the Mbit soft bit data is subjected to a second deinterleave process. The method of claim 6, wherein the step of the subsequent soft bit decoding process further comprises:

Performing line compression processing on the Mbit soft bit data obtained after the second deinterleaving process to obtain soft bit data of the compressed bit; Storing the soft bit data of the compressed bit into a cache;

The soft bit data of the bit read from the buffer is decompressed to obtain Mbit soft bit data, and the Mbit soft bit data is subjected to a first deinterleave process. The method according to any one of claims 1-7, wherein the step of compressing comprises: converting, by mapping, Mbit uniformly quantized soft bit data to obtain bit non-uniformly quantized soft bit data. The method according to claim 8, wherein the step of decompressing the processing comprises:

By inverse mapping, the bit non-uniformly quantized soft bit data read from the buffer is converted to obtain Mbit uniformly quantized soft bit data. 0. A soft bit decoding apparatus for a wireless receiving device, comprising:

a compression module, configured to compress the soft bit data of the Mbit to be decoded during the downlink processing to obtain soft bit data of the compressed bit;

a decoding module, configured to perform subsequent soft bit decoding processing on the soft bit data of the compressed bit;

Where M and N are positive integers and M>N.