CN1388583A - Two-stage electrostatic discharge protecting circuit with acceleratively conducting secondary stage - Google Patents

Two-stage electrostatic discharge protecting circuit with acceleratively conducting secondary stage Download PDF

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Publication number
CN1388583A
CN1388583A CN 01116195 CN01116195A CN1388583A CN 1388583 A CN1388583 A CN 1388583A CN 01116195 CN01116195 CN 01116195 CN 01116195 A CN01116195 A CN 01116195A CN 1388583 A CN1388583 A CN 1388583A
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Prior art keywords
esd
protection circuit
electrostatic storage
storage deflection
pass transistor
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CN 01116195
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CN1161839C (en
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林耿立
柯明道
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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Abstract

The two-stage electrostatic discharge (ESD) protecting circuit is connected between one I/O pad and one power line, and includes a primary ESD protecting element and a detecting circuit, one serially connected resistor between the I/O pad and an inner circuit and a secondary ESD protecting element between the inner circuit and the power line. In case of some ESD event, the ESD detecting circuit provides provides one control signal to the control end of the secondary ESD protecting element to make the secondary ESD protecting element start preceding the primary ESD protecting element so as to clamp ESD voltage and protect the inner circuit effectively.

Description

Quicken the secondary formula electrostatic storage deflection (ESD) protection circuit of secondary conducting
(electrostatic discharge, ESD) protection circuit refer to a kind of secondary formula electrostatic storage deflection (ESD) protection circuit of quickening secondary conducting especially to the present invention relates to a kind of static discharge.
Strengthen the electrostatic storage deflection (ESD) protection circuit of opening speed at secondary (secondary) electrostatic storage deflection (ESD) protection circuit.
Along with the progress of semiconductor technology, and integrated circuit (integrated circuit, IC) semiconductor element in is more and more fragile, and the electrostatic stress that also is subjected to more and more easily on human body, machine or the article of not expecting destroys.Therefore, in the I/O port or power port of IC, often must add electrostatic storage deflection (ESD) protection circuit.Before ESD stress was not as yet up to the injury inner member, the just necessary conducting of the electrostatic storage deflection (ESD) protection circuit on the wafer discharged ESD stress to form discharge path.
Fig. 1 is a kind of secondary formula electrostatic storage deflection (ESD) protection circuit schematic diagram of prior art.Field oxidation element (the field oxide device) NF of the higher ESD tolerance level of tool is as elementary electrostatic storage deflection (ESD) protection circuit.NF is coupled directly to output and goes between joint sheet 12 and the VSS, in order to discharge most ESD electric charge.Just, the trigger voltage of NF is often too high, and makes internal circuit 10 that damaged danger still be arranged.Therefore, go between the joint sheet 12 to be connected in series a buffer resistance RL with output at internal circuit 10, and utilize a level ESD protective element to come strangulation to send into the magnitude of voltage at internal circuit 10 places, as shown in Figure 1, secondary electrostatic storage deflection (ESD) protection circuit is constituted with the nmos pass transistor N2 of a grounded-grid usually.When a pair of VSS is that positive esd event impacts when joint sheet 12 is gone in output, N2 can first conducting discharge a little ESD electric current with the voltage of strangulation end points 14 at a lower current potential.Subsequently, when the voltage of 16 ends up to a certain degree the time, NF just opens and discharges a large amount of ESD electric currents.Because N2 only is responsible for the conducting of little electric current, therefore, the area of N2 can be made forr a short time than NF.
Along with manufacturing progress, also (shallowtrench isolation, STI) technology replaces an oxidation isolation technology by shallow isolating trough gradually.The quick conducting of more difficult quilt that becomes of a field oxidation element under CMOS (Complementary Metal Oxide Semiconductor) (CMOS) manufacture craft of tool shallow isolating trough, so also improving and be not suitable on the CMOS integrated circuit of deep-sub-micrometer of the NF among Fig. 1 with manufacture craft.
A kind of now elementary and secondary electrostatic storage deflection (ESD) protection circuit of secondary formula electrostatic storage deflection (ESD) protection circuit all constitutes with the nmos pass transistor with identical critical voltage, respectively shown in the nmos pass transistor (N1 and N2) of two grounded-grids among Fig. 2.For in an electrostatic discharge event, reaching secondary electrostatic storage deflection (ESD) protection circuit opens to quicken the purpose of electrostatic storage deflection (ESD) protection circuit toggle speed, so the passage length of N2 often designs shortlyer than the passage length of N1 than elementary electrostatic storage deflection (ESD) protection circuit is Zao.Yet the difference of passage length is very limited for the open-interval influence of N1 and N2.That is to say, the electrostatic storage deflection (ESD) protection circuit of Fig. 2 in design, therefore the opening time of N1 and N2 differs obvious inadequately, has lost the main meaning of secondary formula electrostatic storage deflection (ESD) protection circuit, may reduce the ESD protective benefits of entire circuit.
For overcoming the defective of above prior art, main purpose of the present invention, be to provide a kind of and be applicable to shallow isolating trough (STI) manufacture craft, and can quicken the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration of the opening speed of secondary ESD protective element.
According to above-mentioned purpose, the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration of the present invention is applicable to an I/O port.This secondary formula electrostatic storage deflection (ESD) protection circuit of quickening secondary conducting is coupled in an output goes between a joint sheet and the power line, includes an elementary electrostatic storage deflection (ESD) protection circuit, a static discharge circuit for detecting, a series resistor and a level electrostatic storage deflection (ESD) protection circuit.This elementary electrostatic storage deflection (ESD) protection circuit and this static discharge circuit for detecting all are coupled in this and export between joint sheet and this power line.This series resistor is coupled between this joint sheet and the internal circuit.This secondary electrostatic storage deflection (ESD) protection circuit includes a nmos pass transistor, is coupled between this internal circuit and this power line.Wherein, when an electrostatic discharge event takes place; this static discharge circuit for detecting provides a grid of the nmos pass transistor that a control signal gives this secondary electrostatic storage deflection (ESD) protection circuit; so that this elementary electrostatic storage deflection (ESD) protection circuit unlatching more early of this secondary electrostatic storage deflection (ESD) protection circuit; and discharge the ESD electric current, thereby can more effectively protect internal circuit.This secondary electrostatic storage deflection (ESD) protection circuit can be a primary type (native) nmos pass transistor.
The present invention proposes a kind of secondary formula electrostatic storage deflection (ESD) protection circuit of quickening secondary conducting in addition, is applicable to an I/O port, is coupled in an output and goes between a joint sheet and the power line.Secondary formula electrostatic storage deflection (ESD) protection circuit of the present invention includes an elementary electrostatic storage deflection (ESD) protection circuit, a series resistor and a level electrostatic storage deflection (ESD) protection circuit.Elementary electrostatic storage deflection (ESD) protection circuit is coupled in this and exports between joint sheet and this power line, comprises a GENERAL TYPE nmos pass transistor with one first critical voltage.Series resistor is coupled between this joint sheet and the internal circuit.Secondary electrostatic storage deflection (ESD) protection circuit is coupled between this internal circuit and this power line, includes a primary type nmos pass transistor, has one second critical voltage low than this first critical voltage.When an electrostatic discharge event took place, this primary type nmos pass transistor was early opened than this GENERAL TYPE nmos pass transistor, to discharge the ESD electric current.
The invention has the advantages that can be suitable the opening speed between the elementary and secondary electrostatic storage deflection (ESD) protection circuit of separating.Utilization has primary type (native) nmos pass transistor of low critical voltage, or by controlling the time that the static discharge circuit for detecting sends control signal, can quicken the opening speed of secondary electrostatic storage deflection (ESD) protection circuit effectively, to reach the purpose of design of secondary formula electrostatic storage deflection (ESD) protection circuit.
Below be accompanying drawing of the present invention:
Fig. 1 is a kind of secondary formula electrostatic storage deflection (ESD) protection circuit schematic diagram of prior art;
Fig. 2 is the secondary formula electrostatic storage deflection (ESD) protection circuit schematic diagram of another kind of prior art;
Fig. 3 is a schematic diagram of the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration of the present invention;
Fig. 4 is an embodiment of the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration among Fig. 3;
Fig. 5 is another schematic diagram of the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration of the present invention;
Fig. 6 is the secondary formula electrostatic storage deflection (ESD) protection circuit in conjunction with the secondary conducting of acceleration of primary type NMOS and static discharge circuit for detecting.
Component parameters explanation among the figure:
10 internal circuits
Joint sheet is gone in 12 outputs
13,15,15 *Secondary formula electrostatic storage deflection (ESD) protection circuit of the present invention
14,16 end points
20 static discharge circuit for detecting
30 elementary electrostatic storage deflection (ESD) protection circuit
32 level electrostatic storage deflection (ESD) protection circuit
Below in conjunction with accompanying drawing the present invention is further described:
Fig. 3 is the schematic diagram of a secondary formula electrostatic storage deflection (ESD) protection circuit of the present invention.Secondary formula electrostatic storage deflection (ESD) protection circuit 13 of the present invention is applicable to an I/O port, is coupled in output and goes between joint sheet 12 and the internal circuit 10.Secondary formula electrostatic storage deflection (ESD) protection circuit 13 has an elementary electrostatic storage deflection (ESD) protection circuit 30 and a level electrostatic storage deflection (ESD) protection circuit 32.Elementary electrostatic storage deflection (ESD) protection circuit 30 is coupled in output and goes between joint sheet 12 and the VSS; Secondary electrostatic storage deflection (ESD) protection circuit 32 is coupled between internal circuit 10 and the VSS power line.Output goes between joint sheet 12 and the internal circuit 10 to be serially connected with a buffer resistance RL.When detecting an electrostatic discharge event when betiding output and going between joint sheet 12 and the VSS; static discharge circuit for detecting 20 can the secondary electrostatic storage deflection (ESD) protection circuit 32 of control quicken its conducting speed; the voltage that is born with strangulation internal circuit 10, and protection internal circuit 10.
Fig. 4 is an embodiment of the secondary formula electrostatic storage deflection (ESD) protection circuit among Fig. 3.Elementary electrostatic storage deflection (ESD) protection circuit 30 is constituted with the nmos pass transistor N1 of a grounded-grid.The drain electrode of N1 and source electrode are coupled to output respectively and go into joint sheet 12 and VSS.Secondary electrostatic storage deflection (ESD) protection circuit 32 in the secondary formula electrostatic storage deflection (ESD) protection circuit is made of a nmos pass transistor N2, and the drain electrode of N2 and source electrode are coupled to internal circuit 10 and VSS respectively.Include a RC coupling circuit in the static discharge circuit for detecting 20, as shown in Figure 4.This RC coupling circuit is done sth. in advance conducting with triggering N2 and is come strangulation ESD voltage, thereby can more effectively protect internal circuit in order to the grid of coupling (couple) ESD transient voltage (transient voltage) to N2.
Under general normal integrated circuit operative scenario, the grid of N2 is couple to VSS by resistance R.Therefore, N2 presents closed condition.N1 is a closed condition because of its grounded-grid also.Output is gone into joint sheet 12 and can be coupled by resistance R L and internal circuit 10.
When one goes on the joint sheet 12 with respect to VSS for the negative esd event that impacts betides output, be forward bias voltage drop in the parasitic diode D1 of drain electrode among the N1.Therefore discharged ESD stress.
When one goes on the joint sheet 12 with respect to VSS for the esd event that is just impacting betides output, because the coupling of capacitor C, so the grid of N2 can temporarily maintain a high-voltage state.By experiment as can be known, when the grid of a NMOS imposes suitable positive bias, the speed the when speed that its ESD protection starts (or snapback begins) will not apply this positive bias faster than the grid of this NMOS.Therefore, the speed of N2 (having the grid positive bias) will be faster than the opening speed of N1 (grounded-grid).The speed that secondary electrostatic storage deflection (ESD) protection circuit 32 of proper arrangement and elementary electrostatic storage deflection (ESD) protection circuit 30 are opened in regular turn, ESD stress can be released, and is unlikely to damage internal circuit 10.The transistor arrangement of N1 and N2 all can be identical with the nmos pass transistor that internal circuit uses.That is to say that implement the present invention and do not need special facture technology, the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration of the present invention is compatible to advanced IC manufacture craft fully.
In addition, in general complementary MOS transistor (CMOS) manufacture craft, a little shadow manufacture craft and a NMOS critical voltage are often arranged together, and (threshold voltage Vt) adjusts and implants technology (Vtimplantation), is used for adjusting the critical voltage of the nmos pass transistor of IC part.In general, NMOSVt adjusts and implants technology is to implant P conductivity type alloy, as boron (Boron), and the Vt of NMOS is heightened.Therefore, can comprise among the IC identical (cross section be it seems identical) on two kinds of structures, but Vt is different NMOS.Be not subjected to Vt to adjust the NMOS that implants technogenic influence, its Vt is lower, determines its Vt value with substrate or wellblock doping content usually, is called primary type (native) NMOS.As for other NMOS, have higher Vt, be called GENERAL TYPE (general) NMOS.Similarly reason also can comprise identical (cross section be it seems identical) on two kinds of structures among the IC, but Vt is different PMOS: primary type PMOS and GENERAL TYPE PMOS.
Fig. 5 is the schematic diagram of the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of another acceleration of the present invention.Electrostatic storage deflection (ESD) protection circuit 15 is made of buffer resistance RL, elementary electrostatic storage deflection (ESD) protection circuit 30 and secondary electrostatic storage deflection (ESD) protection circuit 32.Elementary electrostatic storage deflection (ESD) protection circuit 30 includes a GENERAL TYPE NMOS N1, and its grid and source-coupled are to VSS, and joint sheet 12 is gone in its drain coupled to output.Secondary electrostatic storage deflection (ESD) protection circuit 32 includes a primary type NMOS N *2, its grid and source-coupled are to VSS, and its drain coupled is to internal circuit 10.Because N *2 is primary type NMOS, and its Vt is low than the Vt of GENERAL TYPE NMO, the fast conducting of ratio N1 that can be relative.Utilize primary type NMOS, secondary electrostatic storage deflection (ESD) protection circuit 32 can be accelerated its opening time effectively, guarantees the ESD protective benefits of whole electrostatic storage deflection (ESD) protection circuit.
Fig. 6 is the secondary formula electrostatic storage deflection (ESD) protection circuit in conjunction with primary type NMOS and static discharge circuit for detecting.In Fig. 6, static discharge circuit for detecting 20 constitutes with a RC coupling circuit, is serially connected with output and goes between joint sheet 12 and the VSS.When an electrostatic discharge event took place, static discharge circuit for detecting 20 can temporary transient rising N *2 grid voltage more quickens N *2 opening speed.
Utilize static discharge circuit for detecting 20 or primary type NMOS, secondary electrostatic storage deflection (ESD) protection circuit can effectively be done sth. in advance its opening time, guarantees the ESD protective benefits of whole electrostatic storage deflection (ESD) protection circuit.
Electrostatic storage deflection (ESD) protection circuit among prior art such as Fig. 2 has the shortcoming that is difficult to separate elementary and secondary electrostatic storage deflection (ESD) protection circuit.Relative, the present invention utilize a static discharge circuit for detecting or with a primary type NMOS as secondary electrostatic storage deflection (ESD) protection circuit, the speed that the secondary electrostatic storage deflection (ESD) protection circuit of quickening that can be in good time is opened in esd event, therefore, whole ESD protective benefits can increase.
Though, more than with GENERAL TYPE NMOS and primary type NMOS as implementing element of the present invention, the present invention can also use GENERAL TYPE PMOS and primary type PMOS as implementing element of the present invention.The conversion between VSS and the VDD is followed in conversion between P type and the N type, be familiar with the people institute of ESD technology can be unlabored, therefore, do not constituted with GENERAL TYPE PMOS and primary type PMOS in this unnecessary description
Embodiment.
The above only is preferred embodiment of the present invention, and all other do not break away from the equivalence of being finished under the disclosed spirit and change or modification, all should be included in the claim scope of the present invention.

Claims (15)

  1. A secondary formula static discharge that quickens secondary conducting (electrostatic discharge, ESD) protection circuit includes:
    One elementary electrostatic storage deflection (ESD) protection circuit is coupled in an output and goes between a joint sheet and the power line;
    One series resistor is coupled between this joint sheet and the internal circuit;
    A level electrostatic storage deflection (ESD) protection circuit is coupled between this internal circuit and this power line;
    It is characterized in that:
    This secondary electrostatic storage deflection (ESD) protection circuit has a control end;
    This secondary formula electrostatic storage deflection (ESD) protection circuit also comprises: one can provide a control signal to aforementioned control end so that this secondary electrostatic storage deflection (ESD) protection circuit this elementary electrostatic storage deflection (ESD) protection circuit early open, with the static discharge circuit for detecting of release ESD electric current, be coupled in this and export between joint sheet and this power line.
  2. 2. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 1 is characterized in that: wherein, this elementary electrostatic storage deflection (ESD) protection circuit all includes nmos pass transistor with this secondary electrostatic storage deflection (ESD) protection circuit.
  3. 3. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 1 is characterized in that: wherein, this elementary electrostatic storage deflection (ESD) protection circuit is one first nmos pass transistor, has a gate coupled to this power line.
  4. 4. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 1 is characterized in that: wherein, this secondary electrostatic storage deflection (ESD) protection circuit is one second nmos pass transistor, and this control end is a grid of this second nmos pass transistor.
  5. 5. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 4, it is characterized in that: wherein, this elementary electrostatic storage deflection (ESD) protection circuit includes one first nmos pass transistor, have a gate coupled to this power line, the critical voltage of this second nmos pass transistor is identical with the critical voltage of this first nmos pass transistor.
  6. 6. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 4, it is characterized in that: wherein, this elementary electrostatic storage deflection (ESD) protection circuit includes one first nmos pass transistor, have a gate coupled to this power line, the critical voltage of this second nmos pass transistor is low than the critical voltage of this first nmos pass transistor.
  7. 7. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 4 is characterized in that: wherein, this second nmos pass transistor is a primary type (native) nmos pass transistor.
  8. 8. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 1 is characterized in that: wherein, this static discharge circuit for detecting includes one in order to distinguish the RC coupling circuit of this esd event and normal operating conditions.
  9. 9. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 1 is characterized in that: wherein, this power line is the VSS power line.
  10. 10. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 1 is characterized in that: wherein, this power line is the VDD power line.
  11. 11. a secondary formula electrostatic storage deflection (ESD) protection circuit of quickening secondary conducting, it includes:
    One elementary electrostatic storage deflection (ESD) protection circuit, one output of coupling what is gone between a joint sheet and the power line,
    One series resistor is coupled between this joint sheet and the internal circuit;
    A level electrostatic storage deflection (ESD) protection circuit is coupled between this internal circuit and this power line,
    It is characterized in that:
    This elementary electrostatic storage deflection (ESD) protection circuit includes a GENERAL TYPE nmos pass transistor, has one first critical voltage;
    This secondary electrostatic storage deflection (ESD) protection circuit includes a primary type nmos pass transistor, has one second critical voltage low than this first critical voltage.
  12. 12. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 11, it is characterized in that: wherein, this GENERAL TYPE nmos pass transistor has an one source pole and a grid that is coupled to this power line, and is coupled to this and exports a drain electrode into joint sheet.
  13. 13. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 11 is characterized in that: wherein, this primary type nmos pass transistor has an one source pole and a grid that is coupled to this power line, and a drain electrode that is coupled to this internal circuit.
  14. 14. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 11, it is characterized in that: wherein, this secondary formula electrostatic storage deflection (ESD) protection circuit includes one in addition when detecting this esd event generation, can trigger the static discharge circuit for detecting of this primary type nmos pass transistor, be coupled in this and export between joint sheet and this power line.
  15. 15. the secondary formula electrostatic storage deflection (ESD) protection circuit of the secondary conducting of acceleration as claimed in claim 14 is characterized in that: wherein, this static discharge circuit for detecting includes one in order to distinguish the RC coupling circuit of this esd event and normal operating conditions.
CNB011161957A 2001-05-30 2001-05-30 Two-stage electrostatic discharge protecting circuit with acceleratively conducting secondary stage Expired - Lifetime CN1161839C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB011161957A CN1161839C (en) 2001-05-30 2001-05-30 Two-stage electrostatic discharge protecting circuit with acceleratively conducting secondary stage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB011161957A CN1161839C (en) 2001-05-30 2001-05-30 Two-stage electrostatic discharge protecting circuit with acceleratively conducting secondary stage

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CN1388583A true CN1388583A (en) 2003-01-01
CN1161839C CN1161839C (en) 2004-08-11

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101273507B (en) * 2005-07-26 2010-12-29 德克萨斯仪器股份有限公司 System and method for protecting IC components
CN101442869B (en) * 2007-11-23 2011-08-24 上海华虹Nec电子有限公司 Dynamic detection electrostatic protection circuit
CN106449637A (en) * 2016-11-08 2017-02-22 中国电子科技集团公司第四十七研究所 Electrostatic protection of input circuit Based on large-scale CMOS integrated circuit and method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101273507B (en) * 2005-07-26 2010-12-29 德克萨斯仪器股份有限公司 System and method for protecting IC components
CN101442869B (en) * 2007-11-23 2011-08-24 上海华虹Nec电子有限公司 Dynamic detection electrostatic protection circuit
CN106449637A (en) * 2016-11-08 2017-02-22 中国电子科技集团公司第四十七研究所 Electrostatic protection of input circuit Based on large-scale CMOS integrated circuit and method thereof

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Publication number Publication date
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