CN1385897A - Method for making electrically EPROM with separated grid structure - Google Patents
Method for making electrically EPROM with separated grid structure Download PDFInfo
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- CN1385897A CN1385897A CN 01119231 CN01119231A CN1385897A CN 1385897 A CN1385897 A CN 1385897A CN 01119231 CN01119231 CN 01119231 CN 01119231 A CN01119231 A CN 01119231A CN 1385897 A CN1385897 A CN 1385897A
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- dielectric layer
- eeprom
- memo
- erasable programmable
- electrically erasable
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Abstract
A read-only memory production method contains microimage etch to a second dielectric layer and a first conductive layer to define a selection grating, to perform unconstant tropism etch to a third dielectric layer to form sidewall structure on the selection grating, an unconstant tropism etch to the second conductive layer and a second blend microimage etch is performed to get a suspended grating, to the interval well formed, to perform ionic arrangement after forming a fourth dielectric layer to further form a source zone and a drain zone and to perform the third blend microimage etch to the third conductive layer to finished the control grating with smaller program voltage and components.
Description
The present invention relates to a kind of manufacture method of EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure, refer to that especially a kind of spacer etch mode of utilizing carries out floating grid voluntarily in alignment with the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of the separated grid structure of selecting grid one side.
In various types of Nonvolatile memories (non-volatile Memory), EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable ROM) is a type that is widely used gradually, wherein especially quick with the growth of wiping memory (Flash Memory) by piece, and in the EEPROM (Electrically Erasable Programmable Read Only Memo) of stacked gate structure (stacked gate structure), mainly have a problem of excessively erasing (over-erase), and in the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure (split gate structure), be by setting up grid (select gate) or control gate (controll gate) structure avoid excessively the erasing problem of (over-erase) of selecting, but because in the existing means (as United States Patent (USP) 5280446 cases), selecting the making of grid (select gate) or control gate (control gate) structure is not voluntarily in alignment with floating grid (floating gate), therefore the size of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure (split gate structure) just is difficult to effectively dwindle, usually all greater than the size of stacked gate structure.
The manufacture method that the purpose of this invention is to provide a kind of EEPROM (Electrically Erasable Programmable Read Only Memo) of undersized separated grid structure.
For achieving the above object, the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure of the present invention is characterized in, comprises the following steps: to provide a substrate; On described substrate, form one first dielectric layer, one first conductor layer and one second dielectric layer in regular turn; Described second dielectric layer and first conductor layer are carried out one first light shield micro image etching procedure, and then define selection grid; On described first dielectric layer, described first conductor layer and described second dielectric layer, form one the 3rd dielectric layer; Described the 3rd dielectric layer is carried out an anisotropic etching, be used to form on the described selection grid side wall construction; On described substrate, form a tunnel dielectric layer again after removing described first dielectric layer; On described tunnel dielectric layer, described selection grid and described side wall construction, form one second conductor layer; Described second conductor layer is carried out an anisotropic etching, be used for the described side wall construction outside and form a clearance wall structure; Described clearance wall structure is carried out one second light shield micro image etching procedure,, be separated by with described side wall construction between described floating grid and described selection grid in order to finish a floating grid; After forming one the 4th dielectric layer on described tunnel dielectric layer, described selection grid, described side wall construction and the described floating grid, carry out an ion disposing process, and then form an one source pole zone and a drain zone; On described the 4th dielectric layer, form one the 3rd conductor layer; And described the 3rd conductor layer carried out one the 3rd light shield micro image etching procedure, in order to finish a control gate, be separated by with described the 4th dielectric layer between described control gate and described floating grid.
The used material of each layer in the described method is exemplified below: described substrate can be a silicon substrate, the formation material of described tunnel dielectric layer can be silica, the optional autoxidation silicon of the material of described first dielectric layer, one of in silicon nitride and the composite bed thereof, the material of described first conductor layer is to be selected from polysilicon (polysilicon), amorphous silicon (a-Si), again one of in silicon metal (recrystallized silicon) and the multi-crystal silicification metal (polycide), the material of described second dielectric layer is to be selected from silica, one of in silicon nitride and the composite bed thereof, the material of described the 3rd dielectric layer is to be selected from silica, one of in silicon nitride and the composite bed thereof, the material of described second conductor layer is to be selected from polysilicon (polysilicon), amorphous silicon (a-Si) and again one of in the silicon metal (recrystallizedsilicon), the material of described the 4th dielectric layer is to be selected from silica, one of in silicon nitride and the composite bed thereof, and the material of described the 3rd conductor layer is to be selected from polysilicon (polysilicon), amorphous silicon (a-Si) and again one of in the silicon metal (recrystallized silicon).
Wherein, the formation of described silica tunnel dielectric layer is to finish by the thermal oxidation processing procedure of described silicon substrate, the anisotropic etching that described the 3rd dielectric layer is carried out is preferably a dry-etching, and the anisotropic etching that described second conductor layer is carried out preferable also be a dry-etching.
Because the inventive method avoids using the little shadow technology of light shield, then the means of utilizing a spacer etch come floating grid is finished in the side of selecting grid with aiming at voluntarily, therefore can effectively dwindle the size of assembly, and then overcome existing separated grid structure EEPROM unit for the program disturbance immunocompetence disappearance that (program disturb immunity) causes size to be difficult for contracting is provided; Because structure that the inventive method is finished is to utilize the mode of source side injection (source side injection) to carry out data to write, so the internal storage location that the present invention is finished, its required program current (program current) is far below the existing required program current (program current) of stacked gate structure EEPROM unit.Therefore the inventive method will can be applicable to finish various types of EEPROM (Electrically Erasable Programmable Read Only Memo) (ElectricallyErasable Programmable ROM), what for example be widely used gradually wipes memory (FlashMemory) by piece, and the EEPROM unit that the means that all can have now are finished has lower programm voltage (program voltage) and littler size of components.
Be clearer understanding purpose of the present invention, characteristics and advantage, the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 1 (a) and (b), (c), (d), (e), (f), (g), (h), (i), (j), (k), (l), (m) are the preferred embodiment processing procedure schematic diagrames of the EEPROM unit manufacture method of separated grid structure of the present invention;
Fig. 2 is the schematic diagram that electric unit of the present invention is arranged to NOR gate pattern (NOR type) memory array circuit.
See also (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) processing procedure schematic diagram shown in (m) of Fig. 1 (a), they are preferred embodiment processing procedure schematic diagrames of separated grid structure EEPROM unit manufacture method.Fig. 1 (a) is depicted as provides a silicon substrate 100 and one first dielectric layer 101 of growing up thereon, subsequently shown in Fig. 1 (b), form one first conductor layer 102 and one second dielectric layer 103 in regular turn in described first dielectric layer 101, just described second dielectric layer 103 and first conductor layer 102 are carried out forming behind the first light shield micro image etching procedure selection grid 104 shown in Fig. 1 (c).Fig. 1 (d) is depicted as and forms one the 3rd dielectric layer 105 on the substrate of finishing said structure, described the 3rd dielectric layer 105 is being carried out an anisotropic etching, dry-etching (dryetch) for example is used to form a side wall construction 106 (shown in Fig. 1 (e)) on the circumferential surface of described selection grid 104.Remove exposed described first dielectric layer 101 subsequently to expose described substrate 100 (shown in Fig. 1 (f)), and then on described substrate 100, form the silicon oxide layer of about 30 to 200 dusts of a thickness with the thermal oxidation processing procedure, and then after finishing the making of tunnel dielectric layer 107, carry out the deposition manufacture process of second conductor layer 108 again, the schematic diagram of finishing is shown in Fig. 1 (g).Then described second conductor layer 108 is carried out an anisotropic etching, for example dry-etching (dry etch) is used to described side wall construction 106 outsides and forms a clearance wall structure 109 (shown in Fig. 1 (h)).Fig. 1 (i) is depicted as described clearance wall structure is carried out one second light shield micro image etching procedure, remove the described clearance wall structure 109 that is not shielded by photoresistance 110 in order to etching, and then finish floating grid 111 in one of described selection grid side voluntarily with aiming at, and described floating grid 111 and 104 of described selection grid are to be separated by with described side wall construction 106.Then, behind overall structure top formation one the 4th dielectric layer 112 (shown in Fig. 1 (j)), carry out an ion disposing process, and then form source region 113 and drain zone 114 shown in Fig. 1 (k).And then carry out one the 3rd light shield micro image etching procedure after depositing one the 3rd conductor layer 115 (shown in Fig. 1 (l)), in order to finishing the control gate 116 shown in Fig. 1 (m), and described control gate 116 and described floating grid 111 between be to be separated by with described the 4th dielectric layer 112.
And the material of said first dielectric layer 101 be can silica, silicon nitride and composite bed thereof wait and finish, its thickness is about 30 to 300 dusts.The material of first conductor layer 102 can be selected from polysilicon (polysilicon), amorphous silicon (a-Si), again one of in silicon metal (recrystallized silicon) and the multi-crystal silicification metal (polycide).And the material of said second dielectric layer 103 can be selected silica, silicon nitride, aforementioned both composite bed or other insulating material for use, and changing its thickness can adjust in order to the size (promptly the thickness summation of first conductor layer 102 and second dielectric layer 103 is the height that equal floating grid 111) to the follow-up floating grid of finishing 111.Also can select silica, silicon nitride or aforementioned both composite bed etc. for use as for the material of the 3rd dielectric layer 105 and the 4th dielectric layer 112.And the material of second conductor layer 108 and the 3rd conductor layer 115 all can be selected polysilicon (polysilicon), amorphous silicon (a-Si) or silicon metal materials such as (recrystallized silicon) again for use.
For the application of read-write at a high speed, the separated grid structure EEPROM unit of finishing for the inventive method can be arranged to NOR gate pattern (NOR type) memory array as shown in Figure 2.
In sum, because the inventive method has been avoided the little shadow technology of use light shield, then the means of utilizing a spacer etch come floating grid 111 is finished voluntarily in the side of selecting grid 104 with aiming at, therefore the existing separated grid structure EEPROM unit of the size that can effectively dwindle assembly, and then improvement is for providing the program disturbance immunocompetence disappearance that (program disturb immunity) causes size to be difficult for contracting.In addition, carry out data and write because the structure that the inventive method is finished is a mode of utilizing source side to inject (source side injection), so the internal storage location that the present invention is finished, its required program current (program current) is far below the existing required program current (program current) of stacked gate structure EEPROM unit.Therefore the inventive method will can be applicable to finish various types of EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable ROM), what for example be widely used gradually wipes memory (Flash Memory) by piece, all can have the EEPROM unit that means are finished now, have lower programm voltage (program voltage) and littler size of components.
Claims (12)
1. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of a separated grid structure is characterized in that, comprises the following steps:
One substrate is provided;
On described substrate, form one first dielectric layer, one first conductor layer and one second dielectric layer in regular turn;
Described second dielectric layer and first conductor layer are carried out one first light shield micro image etching procedure, and then define selection grid;
On described first dielectric layer, described first conductor layer and described second dielectric layer, form one the 3rd dielectric layer;
Described the 3rd dielectric layer is carried out an anisotropic etching, be used to form on the described selection grid side wall construction;
On described substrate, form a tunnel dielectric layer again after removing described first dielectric layer;
On described tunnel dielectric layer, described selection grid and described side wall construction, form one second conductor layer;
Described second conductor layer is carried out an anisotropic etching, be used for the described side wall construction outside and form a clearance wall structure;
Described clearance wall structure is carried out one second light shield micro image etching procedure,, be separated by with described side wall construction between described floating grid and described selection grid in order to finish a floating grid;
After forming one the 4th dielectric layer on described tunnel dielectric layer, described selection grid, described side wall construction and the described floating grid, carry out an ion disposing process, and then form an one source pole zone and a drain zone;
On described the 4th dielectric layer, form one the 3rd conductor layer; And
Described the 3rd conductor layer is carried out one the 3rd light shield micro image etching procedure,, be separated by with described the 4th dielectric layer between described control gate and described floating grid in order to finish a control gate.
2. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, described substrate is to be a silicon substrate.
3. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 2, it is characterized in that the method that forms described tunnel dielectric layer is: it is the described tunnel dielectric layer of silica to form material that described silicon substrate is carried out a thermal oxidation processing procedure.
4. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described first dielectric layer is one of to be selected from silica, silicon nitride and the composite bed thereof.
5. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described first conductor layer be selected from polysilicon, amorphous silicon, again one of in silicon metal and the multi-crystal silicification metal.
6. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described second dielectric layer is one of to be selected from silica, silicon nitride and the composite bed thereof.
7. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described the 3rd dielectric layer is one of to be selected from silica, silicon nitride and the composite bed thereof.
8. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the described anisotropic etching that described the 3rd dielectric layer is carried out is to be a dry-etching.
9. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described second conductor layer is to be selected from polysilicon, amorphous silicon and again one of in the silicon metal.
10. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the described anisotropic etching that described second conductor layer is carried out is to be a dry-etching.
11. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described the 4th dielectric layer is one of to be selected from silica, silicon nitride and the composite bed thereof.
12. the manufacture method of the EEPROM (Electrically Erasable Programmable Read Only Memo) of separated grid structure as claimed in claim 1 is characterized in that, the material of described the 3rd conductor layer is to be selected from polysilicon, amorphous silicon and again one of in the silicon metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01119231 CN1385897A (en) | 2001-05-14 | 2001-05-14 | Method for making electrically EPROM with separated grid structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01119231 CN1385897A (en) | 2001-05-14 | 2001-05-14 | Method for making electrically EPROM with separated grid structure |
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| CN1385897A true CN1385897A (en) | 2002-12-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328763C (en) * | 2003-04-29 | 2007-07-25 | 茂德科技股份有限公司 | Semiconductor structure with partial etching grid and making method thereof |
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2001
- 2001-05-14 CN CN 01119231 patent/CN1385897A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328763C (en) * | 2003-04-29 | 2007-07-25 | 茂德科技股份有限公司 | Semiconductor structure with partial etching grid and making method thereof |
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