CN1379476A - Non-volatile storage device with increased coupling ratio and method of manufacturing the same - Google Patents

Abstract

A memory device and a method of manufacturing the same increase the coupling ratio of a control gate to a floating gate by increasing the capacitance area, by increasing the overlapping area of the control gate and the floating gate. A non-volatile memory device with increased coupling ratio includes a substrate with multiple isolation regions, a first conductive layer formed on the substrate and the isolation regions, and a pair of sidewalls of the first conductive layer vertically formed on each isolation region, wherein the vertical sidewalls are formed by a dielectric layer mask etched to have vertical edges. A second conductive layer is formed on the first conductive layer, the second conductive layer separates the first conductive layer by an interface to increase a surface area, thereby increasing a coupling ratio.

Description

Non-volatile storage device with increased coupling ratio and method of manufacturing the same

The present invention relates to a non-volatile memory (Non-Volatile Memory, NVM), and in particular to a non-volatile storage device with an increased coupling ratio (Coupling Ratio), which is achieved by increasing the capacitance area, so that the The control gate voltage required for program and erase efficiency can be reduced.

The invention also relates to a method of manufacturing the above device.

A floating gate erasable memory cell (Erasable Memory Cell), typically including a field effect transistor (Field Effect Transistor), a floating gate is located above the channel of the field effect transistor, and at least a part of a control gate is located on the floating above the grid. Floating gates and control gates are usually made of polysilicon. As the name of the floating gate indicates, electrons are isolated in the floating gate. For example, the floating gate can be formed in an environment completely surrounded by oxide regions and oxide layers, by The floating gate is charged and released to program the memory cell.

The three traditional programming mechanisms of floating gate erasable memory are Fowler-Nordheim (FN) tunneling, enhanced FN tunneling, and channel hot electron (Channel HotElectron, CHE) injection, see H.Maes, J.Withers&G . Groeseneken, "Trends in Non-volatile Memory Devices and Technologies", SOLID STATEDEVICES pages 157-168 (1988). A non-volatile memory may be, for example, an erasable and programmable read-only memory (Erasable Programmable Read Only Memory, EPROM), an electrically erasable and programmable read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) or Flash memory (Flash Memory). In FN tunneling, electrons tunnel from a silicon region through an oxide layer (for example, a silicon dioxide (SiO ₂ ) layer that isolates the floating gate) into the floating or control gate, typically requiring an electric field of 10 MV/cm To reduce the silicon-silicon dioxide barrier so that electrons can tunnel from the silicon conduction band into silicon dioxide. It should be noted that under a high electric field, channel hot electrons can be generated adjacent to a drain junction, and such channel hot electrons can be injected from the channel into a floating gate.

The coupling ratio of the control gate to the floating gate is very important for non-volatile memory. A low coupling ratio requires a high control gate voltage to achieve program and erase efficiency. A high control gate voltage requirement This highlights the difficulties in the design of charge pumps. Moreover, the high control gate voltage requirements also hinder the reduction of oxide layer thickness and channel length of high voltage devices. In order to counteract the disadvantage of a high voltage requirement, there are several ways to increase the coupling ratio. For example, the thickness of the dielectric layer can be reduced. Another method is to increase the dielectric constant of the inner polysilicon. However, reducing the dielectric The thickness of the layer is limited by the lifetime of the data retention, plus increasing the dielectric constant of the inner polysilicon usually requires the development of new materials.

It is therefore an object of the present invention to overcome the disadvantages of the prior art.

Another object of the present invention is to increase the coupling ratio of the control gate to the floating gate of a non-volatile memory device.

Yet another object of the present invention is to increase the capacitor area in a non-volatile memory device.

Yet another object of the present invention is to increase the interface surface area between the first and second polysilicon conductive layers.

Yet another object of the present invention is to increase the coupling ratio regardless of lithography.

In order to achieve the above and other objects, the present invention discloses a memory device and a manufacturing method for increasing the coupling ratio of the control gate to the floating gate by increasing the capacitance area, which is by increasing the overlapping of the control gate and the floating gate area to reach.

In detail, a non-volatile storage device with increased coupling ratio includes a substrate with multiple isolation regions, the plurality of isolation regions are formed, for example, by Local Oxidation (LOCOS), a first conductive layer Formed on the substrate and isolation regions, wherein a pair of sidewalls of the first conductive layer are formed on each isolation region in a vertical manner, and the vertical sidewalls are formed by an etched dielectric layer cap having vertical sides. The curtain is formed.

A second conductive layer is formed on the first conductive layer. The second conductive layer isolates the first conductive layer with an interface to increase the surface area, thereby increasing the coupling ratio. Preferably, an inner conductive dielectric layer is formed between the first and the first conductive layer. In the middle of the second conductive layer, the inner conductive dielectric layer preferably includes the first and second silicon dioxide (SiO ₂ ) layers, and a silicon nitride (Si ₃ N ₄ ) layer in between.

Therefore, in the device of the present invention, since the first conductive layer is formed on a long line, vertical sidewalls are formed, thereby achieving a relatively large surface area between the first conductive layer and the second conductive layer. Interface, thus increasing the capacitance area, thereby increasing the coupling ratio of the control gate to the floating gate. In the case of increasing the coupling ratio, the control voltage applied to the control gate electrode (second conductive layer) can be reduced, in fact, it is possible to dispense with the charge pump typically used to reinforce the control voltage. Since the amount of charges induced in the first conductive layer is increased based on the large capacitive area, it is possible to apply a lower voltage to the control gate electrode.

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the preferred embodiments are particularly exemplified together with the accompanying drawings, and are described in detail as follows:

1 is a top view of the first step of the manufacturing process of a non-volatile storage device with increased capacitor area according to the present invention; and

Fig. 2 to Fig. 6 are according to an embodiment of the present invention, along the I'-I plane of Fig. 1, a manufacturing flow chart of a non-volatile storage device with increased capacitance area.

Wherein, the parts and reference signs are respectively:

10: Silicon substrate

12: Quarantine

14: The first dielectric layer

16: Tunneling dielectric layer

18: The first conductive layer

20: Second dielectric layer

22: The second conductive layer

24: Inner conductive dielectric layer

Example

The present invention is described below with an example of a non-volatile semiconductor memory device. It should be understood, however, that the present invention is not limited to the use of a particular type of device or memory cell, and that the present invention is more broadly applicable to any semiconductor device in which internal impedance is a concern. Furthermore, while the present invention is well suited for use in non-volatile semiconductor memory devices, it also provides significant advantages in numerous other applications.

1 to 6 show the process of forming an embodiment of the present invention, please refer to FIG. 1 and FIG. 2 (FIG. 2 is a cross-sectional view along the I'-I plane of FIG. As a starting point, a long line of an isolation region 12 is formed in the silicon substrate 10 by, for example, an area oxidation method, a first dielectric layer (for example, silicon nitride) 14 is formed on the isolation region 12 and the silicon substrate 10, A patterned first dielectric layer 14 forms a parallel strip line on each isolation region 12, and a tunneling dielectric layer (for example, silicon dioxide) 16 is formed on the silicon substrate between each of the isolation regions 12. 10, then, a first conductive layer (for example, doped polysilicon) 18 is formed as a floating gate electrode, it should be noted that the sidewalls of the first conductive layer 18 surrounding each first dielectric layer 14 Both are vertical and have a relatively large surface area. A large surface area is very important to increase the capacitance area, as will be discussed below.

Please continue to refer to FIG. 3, depositing a second dielectric layer (for example, silicon dioxide) 20, the second dielectric layer 20 has a thickness enough to fill the gap between the first conductive layer 18, and then, with the first The conductive layer 18 is used as an etch stop layer to erase or etch back the second dielectric layer 20 .

Please continue to refer to FIG. 4 , using the first dielectric layer 14 as an etching stop layer to etch the first conductive layer 18 .

Please continue to refer to FIG. 5 , the first dielectric layer 14 and the second dielectric layer 20 are removed, for example, by etching.

Please continue to refer to FIG. 6, an inner conductive dielectric layer 24 is formed on the first conductive layer 18 and the isolation region 12, the inner conductive dielectric layer 24 is composed of three dielectric layers, the first layer includes, for example, two a silicon oxide dielectric layer, the second layer includes, for example, a silicon nitride dielectric layer, and the third layer includes, for example, a silicon dioxide dielectric layer. Then, a second conductive layer (eg, doped polysilicon) 22 is formed on the inner conductive dielectric layer 24, and the second conductive layer 22 serves as the control gate electrode.

Referring back to Figure 1, the stack gate is patterned using a control gate mask and the buried bit line is formed. Finally, conventional back-end processes are used to complete the fabrication of the memory device (not shown in the figure).

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with this technology, without departing from the spirit and scope of the present invention, can make various Improvement and update, so the scope of protection of the present invention should be based on the scope of protection defined in the claims.

Claims (16)

1. non-volatile memory that increases the coupling ratio is characterized in that: comprising:

One substrate;

One complex isolation district is formed in this substrate;

One first conductive layer is formed in this substrate and this complex isolation district, and the pair of sidewalls of this first conductive layer is formed on each of this complex isolation district in vertical mode;

One second conductive layer is formed on this first conductive layer, and this second conductive layer is isolated this first conductive layer increasing by a surface area with the interface, and then increases the coupling ratio.

2. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: it also comprises conduction dielectric layer in, be formed on this first with this second conductive layer in the middle of.

3. the non-volatile memory of increase coupling ratio according to claim 2 is characterized in that: the silicon dioxide (SiO that comprises the ground floor and the second layer in this in the conduction dielectric layer ₂) layer, and one deck silicon nitride (Si in the middle of being positioned at ₃N ₄) layer.

4. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: the vertical sidewall of this first conductive layer is to form by the dielectric cover curtain with vertical sidewall.

5. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: this first conductive layer and this second conductive layer comprise a polysilicon material.

6. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: this second conductive layer forms a control grid electrode.

7. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: (Local Oxidation is LOCOS) to form this complex isolation district for the regional oxidizing process by silicon.

8. the non-volatile memory of increase coupling ratio according to claim 3 is characterized in that: it also comprises a dielectric layer, is formed in this substrate between each of this complex isolation district.

9. method of making the non-volatile memory that increases the coupling ratio, it is characterized in that: step comprises:

In a substrate, form a complex isolation district;

Form one first conductive layer in this substrate and this complex isolation district, the pair of sidewalls of this first conductive layer is formed on each of this complex isolation district in vertical mode;

Form one second conductive layer on this first conductive layer, this second conductive layer is isolated this first conductive layer increasing by a surface area with the interface, and then increases the coupling ratio.

10. manufacturing according to claim 9 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: it also be included in this first with this second conductive layer in the middle of form the step of conduction dielectric layer in.

11. manufacturing according to claim 10 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: the silicon dioxide (SiO that in this, comprises the ground floor and the second layer in the conduction dielectric layer ₂) layer, and one deck silicon nitride (Si in the middle of being positioned at ₃N ₄) layer.

12. manufacturing according to claim 9 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: the step that forms this first conductive layer comprises and forms the step of a dielectric cover curtain with vertical sidewall with this vertical sidewall of forming this first conductive layer.

13. manufacturing according to claim 9 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: this first conductive layer and this second conductive layer comprise a polysilicon material.

14. formation according to claim 9 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: this second conductive layer forms a control grid electrode.

15. formation according to claim 9 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: the regional oxidizing process by silicon is to form this complex isolation district.

16. formation according to claim 11 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: it also is included in the step that forms a dielectric layer in this substrate between each of this complex isolation district.

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