CN100349298C - Non-volatile memory with improved coupling rate and its making method - Google Patents
Non-volatile memory with improved coupling rate and its making method Download PDFInfo
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- CN100349298C CN100349298C CNB011103175A CN01110317A CN100349298C CN 100349298 C CN100349298 C CN 100349298C CN B011103175 A CNB011103175 A CN B011103175A CN 01110317 A CN01110317 A CN 01110317A CN 100349298 C CN100349298 C CN 100349298C
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Abstract
The present invention relates to a memory with increased coupling rate of a control grid to a floating grid by increasing capacity area and a making method thereof. The coupling rate is increased by increasing the overlapping region of the control grid and the floating grid. The non-volatile memory with an increased coupling rate comprises a substrate with a plurality of isolation regions, a first conductive layer is formed on the substrate and the isolation regions, a pair of side walls of the first conductive layer are vertically formed on the first isolation region, and the vertical side walls are formed from a dielectric layer mask with etched vertical edges. A second conductive layer is formed on the first conductive layer and is isolated from the first conductive layer by an interface to increase surface area, and thus, the coupling rate is increased. An internal conductive dielectric layer is formed between the first layer and the second conductive layer and preferably comprises a first silicon dioxide layer, a second silicon dioxide layer and a silicon nitride layer in the middle.
Description
Technical field
The present invention relates to a kind of non-voltile memory (Non-Volatile Memory, NVM), and be particularly related to the non-volatile memory of a kind of increase coupling than (Coupling Ratio), reach by increasing capacity area, so then make to reach program and the needed control-grid voltage of the efficient of erasing can reduce.
The invention still further relates to the manufacture method of said apparatus.
Background technology
A kind of floating boom memory cell (Erasable Memory Cell) of can erasing, comprise on the typical case that a field-effect transistor (Field Effect Transistor), a floating boom are positioned at the channel top of field-effect transistor, and a control gate to have some at least be the top that is positioned at floating boom.Floating boom and control gate normally are made of polysilicon, just as the name referring of floating boom, electronics is isolated in the floating boom, for example, floating boom can be formed on fully by zoneofoxidation and oxide layer institute around environment in, by floating boom electrically charged with the release electric charge with the memory cell sequencing.
Floating boom can erase three kinds of traditional sequencing mechanism of internal memory be respectively FN that Fowler-Nordheim (FN) wears tunnel, reinforcement wear tunnel and channel hot electron (ChannelHot Electron, CHE) injection, referring to H.Maes, J.Withers ﹠amp; G.Groeseneken, " Trends in Non-volatile Memory Devices and Technologies ", SOLIDSTATE DEVICES page 157-168 (1988).But a kind of non-voltile memory may be a kind of for example can erasing and program read-only memory (Erasable Programmable Read OnlyMemory, EPROM) but, can electricity remove and program read-only memory (Electrically ErasableProgrammable Read Only Memory, EEPROM) or flash memory (Flash Memory).Wear in the tunnel at FN, electronics is worn tunnel one oxide layer (for example, a silicon dioxide (SiO of isolated floating boom from silicon area
2) layer) entering floating boom or control gate, on the typical case, the electric field of needs one 10M volt/cm reduces the obstacle of silicon-silicon dioxide, enters the silicon dioxide so that electronics can be worn tunnel from the silicon conduction band.Must be noted that under the situation of a high electric field, can produce channel hot electron at the adjacent of a drain junction, this channel hot electron can enter the floating boom from the channel injection.
Control grid is very important to the coupling ratio of floating boom concerning non-voltile memory, one low coupling is than then needing a higher control-grid voltage to reach program and the efficient of erasing, one high control-grid voltage demand then highlights the difficulty in the charge pump design, moreover high control-grid voltage demand has also hindered the oxidated layer thickness and the channel length of dwindling high voltage device.Hinder a high this shortcoming of voltage requirements in order to hold back, the method that several increase coupling ratios are arranged, for example, can reduce the thickness of dielectric layer, other method is the dielectric constant of polysilicon in increasing, yet the thickness that reduces dielectric layer is limited by the life-span that data keeps, and adds the dielectric constant that increases interior polysilicon and need develop new material usually.
Summary of the invention
Therefore, a purpose of the present invention is exactly the shortcoming that overcomes prior art.
Another object of the present invention is exactly to increase the coupling ratio of the control gate of a non-volatile memory to floating boom.
A further object of the present invention is exactly the capacity area that is increased in the non-volatile memory.
Another purpose of the present invention is exactly the interfacial surface area that is increased between first and second polysilicon conducting layers.
Of the present invention also have a purpose not considering to increase the coupling ratio under little shadow situation exactly.
The present invention reaches above-mentioned and other purpose, discloses a kind ofly by increasing capacity area to increase control gate to the storage device of the coupling ratio of floating boom and the method for manufacturing in the present invention, and this is to reach by the overlay region that increases control gate and floating boom.
Know clearly it, a kind of non-volatile memory that increases the coupling ratio comprises that one has a substrate of most isolated areas, these isolated areas for example are by regional oxidizing process (Local Oxidation, LOCOS) form, one first conductive layer is formed on substrate and the isolated area, wherein, the pair of sidewalls of first conductive layer is formed on each isolated area in vertical mode, and this vertical sidewall is to have etched the dielectric layer cover curtain with vertical edges by one to form.
One second conductive layer is formed on first conductive layer, second conductive layer is isolated first conductive layer to increase surface area with the interface, and then increase coupling ratio, preferable situation is, one conduction interlayer dielectric layer is formed in the middle of first and second conductive layer, and the conduction interlayer dielectric layer preferably includes the silicon dioxide (SiO of the ground floor and the second layer
2) layer, and one deck silicon nitride (Si in the middle of being positioned at
3N
4) layer.
Therefore, in device of the present invention, because first conductive layer is formed on the rectangular line, make that vertical sidewall is formed, between first conductive layer and second conductive layer, produce a sizable surface area interface and reach, thereby the increase capacity area, and then increase the coupling ratio of control gate to floating boom.Under the situation that increases the coupling ratio, can reduce to be applied to the control voltage of control grid electrode (second conductive layer), in fact, be might save to be used for the charge pump of reinforcement control voltage on the typical case.Since increase the amount of charge of induction in first conductive layer based on big capacity area, so might be applied on the control grid electrode with a lower voltage.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, especially exemplified by preferred embodiment, and conjunction with figs., be described in detail below:
Description of drawings
Fig. 1 is according to the present invention, a kind of non-volatile memory that increases capacity area, the vertical view of the first step of its manufacturing process; And
Fig. 2 to Fig. 6 is according to one embodiment of the invention, along I '-I plane of Fig. 1, a kind of manufacturing flow chart that increases the non-volatile memory of capacity area.
Wherein, parts and Reference numeral are respectively:
10: silicon base
12: isolated area
14: the first dielectric layers
16: tunneling dielectric layer
18: the first conductive layers
20: the second dielectric layers
22: the second conductive layers
24: the conduction interlayer dielectric layer
Embodiment
The present invention illustrates it below in conjunction with the example of a Nonvolatile semiconductor memory device.Yet, will be appreciated that the present invention is not limited to use the device or the memory cell of special kenel, the present invention can be applied in the internal driving of being paid close attention in any semiconductor device more largo.Moreover, though the present invention very compatibly is applied in the Nonvolatile semiconductor memory device, in numerous other application, also provide significant advantage.
Fig. 1 to Fig. 6 is the processing procedure that expression forms one embodiment of the invention, please refer to Fig. 1 and Fig. 2 (Fig. 2 system is along a cross-sectional view on I '-I plane of Fig. 1), with a silicon base 10 is starting point, the rectangular line of one isolated area 12 for example is to be formed in the silicon base 10 with regional oxidizing process, one first dielectric layer (for example, silicon nitride) 14 is formed on isolated area 12 and the silicon base 10, first dielectric layer 14 of patterning forms a parallel rectangular line on each isolated area 12, one tunneling dielectric layer (for example, silicon dioxide) 16 is formed on isolated area 12 silicon base 10 between each.Then, one first conductive layer (for example, the polysilicon that mixes) 18 forms as a floating gate electrode, must be noted that round the sidewall of first conductive layer 18 of each first dielectric layer 14 all be vertical, and have a sizable surface area, one big surface area is very important to increasing capacity area, will discuss below.
Please continue with reference to Fig. 3, deposit one second dielectric layer (for example, silicon dioxide), 20, the second dielectric layers 20 and have the thickness that one deck is enough to fill up the slit of 18 of first conductive layers, then, come worn with first conductive layer 18 as etching stopping layer or eat-back (Etch-Back) second dielectric layer 20.
Please continue with reference to Fig. 4, come etching first conductive layer 18 as etching stopping layer with first dielectric layer 14.
Please continue with reference to Fig. 5, remove first dielectric layer 14 and second dielectric layer 20, for example, remove with etching method.
Please continue with reference to Fig. 6, one conduction interlayer dielectric layer 24 is formed on first conductive layer 18 and the isolated area 12, and conduction interlayer dielectric layer 24 is made up of three layers of dielectric layer, and ground floor comprises, for example, silicon dioxide dielectric layers, the second layer comprise, for example, silicon nitride dielectric layer, and the 3rd layer comprise, for example, and silicon dioxide dielectric layers.Then, one second conductive layer (for example, the polysilicon of doping) 22 is formed on the conduction interlayer dielectric layer 24, and second conductive layer 22 is as control grid electrode.
Please return with reference to Fig. 1, use the control gate light shield to make heap build gate patternization, and form the bit line that buries.At last, use traditional back segment operation to finish the manufacturing (not being illustrated among the figure) of storage device.
In sum; though the present invention with preferred embodiment openly as above; yet it is not in order to limit the present invention; any personnel that have the knack of this technology; without departing from the spirit and scope of the present invention; when can doing various improvement and renewal, so protection scope of the present invention is as the criterion when the protection range that limits with claims.
Claims (14)
1. non-volatile memory that increases the coupling ratio is characterized in that: comprising:
One substrate;
One most isolated area is formed in this substrate;
One first conductive layer, be formed on this substrate and the described majority isolated area, the pair of sidewalls of this first conductive layer is formed in vertical mode on each of a described majority isolated area, and wherein the vertical sidewall of this first conductive layer is to form by the dielectric cover curtain with vertical sidewall; And
One second conductive layer is formed on this first conductive layer, and this second conductive layer is isolated this first conductive layer increasing by a surface area with the interface, and then increases the coupling ratio.
2. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: it also comprise one the conduction interlayer dielectric layer, be formed on this first with this second conductive layer in the middle of.
3. the non-volatile memory of increase coupling ratio according to claim 2 is characterized in that: in this conduction interlayer dielectric layer, comprise the silicon dioxide layer of the ground floor and the second layer, and one deck silicon nitride layer in the middle of being positioned at.
4. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: this first conductive layer and this second conductive layer comprise a polysilicon material.
5. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: this second conductive layer forms a control grid electrode.
6. the non-volatile memory of increase coupling ratio according to claim 1 is characterized in that: the regional oxidizing process by silicon is to form a described majority isolated area.
7. the non-volatile memory of increase coupling ratio according to claim 3 is characterized in that: it also comprises a dielectric layer, is formed in this substrate between each of a described majority isolated area.
8. method of making the non-volatile memory that increases the coupling ratio, it is characterized in that: step comprises:
In a substrate, form one most isolated area;
On this substrate and a described majority isolated area, form one first conductive layer, the pair of sidewalls of this first conductive layer is formed in vertical mode on each of a described majority isolated area, and wherein the vertical sidewall of this first conductive layer is to form by the dielectric cover curtain with vertical sidewall; And
Form one second conductive layer on this first conductive layer, this second conductive layer is isolated this first conductive layer increasing by a surface area with the interface, and then increases the coupling ratio.
9. manufacturing according to claim 8 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: it also be included in this first with this second conductive layer in the middle of form the step of a conduction interlayer dielectric layer.
10. manufacturing according to claim 9 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: in this conduction interlayer dielectric layer, comprise the silicon dioxide layer of the ground floor and the second layer, and one deck silicon nitride layer in the middle of being positioned at.
11. manufacturing according to claim 8 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: this first conductive layer and this second conductive layer comprise a polysilicon material.
12. formation according to claim 8 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: this second conductive layer forms a control grid electrode.
13. formation according to claim 8 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: the regional oxidizing process by silicon is to form a described majority isolated area.
14. formation according to claim 10 increases the method for the non-volatile memory of coupling ratio, it is characterized in that: it also is included in the step of formation one dielectric layer in this substrate between each of a described majority isolated area.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011103175A CN100349298C (en) | 2001-04-03 | 2001-04-03 | Non-volatile memory with improved coupling rate and its making method |
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| CNB011103175A CN100349298C (en) | 2001-04-03 | 2001-04-03 | Non-volatile memory with improved coupling rate and its making method |
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| CN1379476A CN1379476A (en) | 2002-11-13 |
| CN100349298C true CN100349298C (en) | 2007-11-14 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324693C (en) * | 2003-07-24 | 2007-07-04 | 旺宏电子股份有限公司 | Manufacturing method of flash memory |
| CN101783286B (en) * | 2009-01-20 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing capacitor of metal-insulator-metal structure |
| US8772854B2 (en) * | 2012-04-02 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-time programming memory cells and methods for forming the same |
| US10756267B2 (en) * | 2017-04-11 | 2020-08-25 | National Chiao Tung University | Nonvolatile memory comprising variable resistance transistors and method for operating the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150695A (en) * | 1994-09-08 | 1997-05-28 | 现代电子产业株式会社 | Method for manufacturing non-volatile memory cell |
| CN1200574A (en) * | 1997-05-26 | 1998-12-02 | Lg半导体株式会社 | Nonvolatile semiconductor memory and method of fabrication |
| US6137133A (en) * | 1995-05-19 | 2000-10-24 | Micron Technology, Inc. | Programmable non-volatile memory cell and method of forming a non-volatile memory cell |
| US6200856B1 (en) * | 1998-03-25 | 2001-03-13 | Winbond Electronics Corporation | Method of fabricating self-aligned stacked gate flash memory cell |
| CN1289148A (en) * | 1999-08-31 | 2001-03-28 | 株式会社东芝 | Non-volatile semiconductor storage device and mfg. method thereof |
-
2001
- 2001-04-03 CN CNB011103175A patent/CN100349298C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150695A (en) * | 1994-09-08 | 1997-05-28 | 现代电子产业株式会社 | Method for manufacturing non-volatile memory cell |
| US6137133A (en) * | 1995-05-19 | 2000-10-24 | Micron Technology, Inc. | Programmable non-volatile memory cell and method of forming a non-volatile memory cell |
| CN1200574A (en) * | 1997-05-26 | 1998-12-02 | Lg半导体株式会社 | Nonvolatile semiconductor memory and method of fabrication |
| US6200856B1 (en) * | 1998-03-25 | 2001-03-13 | Winbond Electronics Corporation | Method of fabricating self-aligned stacked gate flash memory cell |
| CN1289148A (en) * | 1999-08-31 | 2001-03-28 | 株式会社东芝 | Non-volatile semiconductor storage device and mfg. method thereof |
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| CN1379476A (en) | 2002-11-13 |
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