CN1378252A - Method for producing different-thickness oxide layer - Google Patents
Method for producing different-thickness oxide layer Download PDFInfo
- Publication number
- CN1378252A CN1378252A CN 01109731 CN01109731A CN1378252A CN 1378252 A CN1378252 A CN 1378252A CN 01109731 CN01109731 CN 01109731 CN 01109731 A CN01109731 A CN 01109731A CN 1378252 A CN1378252 A CN 1378252A
- Authority
- CN
- China
- Prior art keywords
- oxide layer
- thickness
- assembly district
- manufacture method
- different
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The process of producing oxide layer in different thickness includes: providing one semiconductor substrate with one first module area and one second module area; forming the first oxide layer in the first module area and one second module area on the surface of the semiconductor substrate; doping the first oxide layer in the first module area to form one second oxide layer with performance dissimilar to that of the first oxide layer and thickness smaller then that of the first oxide layer; and finally removing the second oxide layer in the first module area. So, the first oxide layer in the first module area is greater than that in the second module area.
Description
The present invention relates to a kind of manufacture method of oxide layer, particularly have the manufacture method of the oxide layer of different-thickness.
In integrated circuit package, different circuit need have the different circuit unit close fit of different fundamental operation characteristics.Be the competitiveness and the diversity of adaptive circuit assembly, on some assembly, require to have different oxidated layer thickness, to satisfy the demand of different operating voltage or electric capacity.
Field-effect transistor (FETs) is one of assembly that is the most extensively used in the integrated circuit.Because field effect transistor circuitry can be carried out multiple different function, and the manufacturing of field-effect transistor has the reproducibility and the predictability of height.Another advantage of field effect transistor element is that size of components can be less, and can be arranged closely and install.One typical field-effect transistor is formed by the grid of the source electrode of channel region separation and a drain electrode and a conduction by being formed in the substrate, and source electrode and drain electrode are on the both sides of channel region, and grid is then separated by a gate oxide level and channel region.
The operating characteristic of field-effect transistor is because many different assembly structures determine, comprises the thickness of gate oxide level.The upper limit of the operating voltage of field-effect transistor, mainly relevant with the breakdown voltage that gate oxide level can be born, this voltage depends mainly on the thickness of gate oxide level.Because the field-effect transistor of different functions is designed in operation under the different voltage, the field-effect transistor that use on the historical facts or anecdotes border should have different gate oxide layer thicknesses, so that different operating voltages to be provided.Field-effect transistor also can utilize the gate oxide level of different-thickness, reaches the high service speed (thin gate oxide) of field-effect transistor or the effect of low leakage electrode stream (thicker gate oxide).Therefore, the field-effect transistor in memory subassembly, its gate oxide level may have one first thickness.And the field-effect transistor in the logical circuit of high speed, low-voltage then may have the obviously thin gate oxide level of one second thickness.Usually, internal memory lays respectively on the different chips with logical circuit.When internal memory and logical circuit are positioned on the different chips, then can utilize comprehensive thermal oxidation technology respectively, to generate the gate oxide of different-thickness to different chips.The gate oxide of different-thickness is that different base is exposed in the oxidation environment, and it is formed to control different open-assembly times.
Therefore recently, chip design has had the transistor of the oxide of different-thickness towards utilization, be combined into circuit on one chip, develops in order to the direction that obtains different operating voltages or change other operating characteristic.
Figure 1A to Fig. 1 C is in the known technology, is commonly used to form the manufacture method of different-thickness oxide skin(coating).Please refer to Figure 1A, at first, on the semiconductor-based end 10, form assembly isolation structure 11, form oxide layer 12 in substrate 10 surfaces with thermal oxidation method again, then deposition mononitride layer 13 on oxide layer 12.Afterwards, the definitions component district, etching nitride layer and oxide skin(coating) partly, to define different assembly district 14,15, the substrate surface in assembly district 15 forms an oxide layer 16 again, as the grid oxic horizon in assembly district 15.And the grid oxic horizon in assembly district 14 is constituted by oxide layer 12 and nitride layer 13.Therefore, assembly district 14 is also inequality with the thickness of the grid oxic horizon in assembly district 15.
And main purpose of the present invention just provides a kind of different operating voltage and electric capacity of can be applicable to, and has the oxide layer of different-thickness, and technology is simpler than above known technology.
For achieving the above object, the invention provides a kind of manufacture method of different-thickness oxide layer: at first, the semiconductor substrate is provided, and the semiconductor-based end, have one first assembly district and one second assembly district, then at the semiconductor-based end, the first assembly district and surface, the second assembly district form one first oxide layer.Provide an admixture to first oxide layer in the first assembly district again; for example be nitrogen; and on first oxide layer in the first assembly district, form one second oxide layer; wherein first oxide layer has different characteristics with second oxide layer; make second oxide layer can be used as a protective layer, and second oxidated layer thickness is less than first oxidated layer thickness.At last, remove second oxide layer in the first assembly district, expose the first oxide layer surface, then first oxidated layer thickness in the first assembly district is greater than first oxidated layer thickness in the second assembly district.According to above-mentioned manufacture method, can form the oxide layer of different-thickness in different assemblies district.
In addition, also can in different assembly districts, form the oxide layer of multilayer different-thickness.Its manufacture method is as follows: provide the semiconductor substrate, and the semiconductor-based end has one first assembly district and one second assembly district.Then, at the semiconductor-based end, the first assembly district and second assembly district surface forms one first oxide layer.Provide an admixture to first oxide layer in the first assembly district; on first oxide layer, form one second oxide layer; wherein first oxide layer has different character with second oxide layer, make second oxide layer can be used as a protective layer, and second oxidated layer thickness is less than first oxidated layer thickness.At last, remove second oxide layer in the first assembly district, expose the first oxide layer surface, make surface, the first assembly district form the oxide layer of one first thickness, the second assembly district forms the oxide layer of one second thickness.At last, repeat abovementioned steps, then can in the assembly district, form the different oxide layer of multi-layered thickness.
Form the oxide layer of different-thickness according to the present invention, its technology is simpler than the oxide layer that known technology produces different-thickness, and the quality of oxide layer is also preferable.Therefore except the required voltage that bears of different assembly operations can be provided, also can be used as the required different-thickness oxide layer of assembly simultaneously, also can be applicable on the grid oxic horizon.
Below in conjunction with drawings and Examples the present invention is made detailed explanation:
Figure 1A to Fig. 1 C is the flow process profile of known different-thickness oxide layer manufacture method.
Fig. 2 A to Fig. 2 C is according to preferred embodiment of the present invention, uses the flow process profile of different-thickness oxide layer manufacture method.
Wherein, parts and Reference numeral are respectively:
10,20: substrate
11,21: the assembly isolation structure
12,16,22,22a, 22c: oxide layer
13: nitride layer
22b: implant the nitrogen oxide layer
24: photoresistance
Embodiment:
Shown in Fig. 2 A to Fig. 2 C, be a preferred embodiment of the present invention, use the flow process profile of different-thickness oxide layer manufacture method.
The invention provides a kind of manufacture method that produces different-thickness oxide layer, can form the oxide layer of different-thickness simultaneously.Make it can bear different operating voltage, and make the circuit that forms subsequently can therefore have different component characteristics,, improve competitiveness of product to expand the diversity of assembly and circuit.Therefore the manufacture method of different-thickness oxide layer of the present invention applicablely anyly in integrated circuit technology needs the different-thickness oxide layer part, and not only is confined in the use of grid oxic horizon.Yet at this, for convenience of description, still with grid oxic horizon as a preferred embodiment of the present invention.
Please refer to Fig. 2 A.At first forming assembly isolation structure 21 in semiconductor silicon substrate 20, for example is the field oxide that forms with the LOCOS method, or isolation structure of shallow trench, and the assembly isolation structure is to be used for isolated different assembly districts, is short-circuited to prevent adjacent transistors.Then, form an oxide layer 22 on substrate 20 and assembly isolation structure surface, it can form with thermal oxidation method, and thickness is about the 120-210 Izod right side.
Please refer to Fig. 2 B.On the oxide layer 22 in an assembly district 23 that will form, be provided with a photoresistance 24, replant admixture 25 in the oxide layer that does not cover photoresistance, and define another assembly district 26.Admixture for example is a nitrogen, and the nitrogen implantation depth can be by implanting energy control, and implantation depth, looks the required thickness of oxide layer of assembly and determines, implants energy and is about about 5-10kev.Wherein, through the oxide layer 22 of nitrogen doped in assembly district 26, it implants the oxide layer 22b in nitrogen zone; its different in kind is in the oxide layer 22 of original formation, and for example, it is to same etchant; can have different rate of etch, so oxide layer 22a can be used as the protective layer of an etching step.
Remove oxide layer 22b at last, for example remove oxide layer 22b, remove photoresistance 24 with the electricity slurry again, form the oxide layer 22c shown in Fig. 2 C with BOE (a kind of solvent that contains HF) or hot phosphoric acid.After above-mentioned technological process, assembly district 23 is different with assembly district 26 thickness of oxide layer, and wherein, the oxidated layer thickness in assembly district 23 is greater than the oxidated layer thickness in assembly district 26.
Afterwards, on oxide layer, form required component with conventional art again.For example, as oxide layer 22c during, then can form compound crystal silicon layer in its surface again as pad oxide; and behind lithography, form grid, cover with insulating barrier again, and form clearance wall with protection grid side; implant substrate with impurity again, formation source/drain region, and finish MOS transistor.
Similarly, can also repeat the processing step of above-mentioned Fig. 2 B and Fig. 2 C, utilize nitrogen to mix oxide layer, form oxide layer of different nature, for same etchant, have different etching selection rates, and on the oxide layer of originally existing two layers of different-thickness, the oxide layer of different-thickness need be increased again according to assembly, and the oxide layer of multilayer different-thickness can be formed at last.
Though the present invention with preferred embodiment explanation as above, it is not that any personnel that have the knack of this technology without departing from the spirit and scope of the present invention, can be used for various modifications and upgrade in order to qualification the present invention.Therefore protection scope of the present invention should be as the criterion with restricted portion.
Claims (14)
1. the manufacture method of a different-thickness oxide layer, it is characterized in that: this manufacture method comprises the following steps at least;
In the semiconductor substrate, be provided with one first assembly district and one second assembly district;
Establish one first oxide layer in this first assembly district and this surface, second assembly district;
Provide an admixture to first oxide layer in this first assembly district, make on this first assembly district, first oxide layer, form one second oxide layer, wherein this first oxide layer has different character with this second oxide layer, and this second oxidated layer thickness is less than this first oxidated layer thickness;
Remove this second oxide layer in this first assembly district, expose this first oxide layer surface, make first oxide layer in this first assembly district, different with first thickness of oxide layer that forms in this second assembly district.
2. manufacture method according to claim 1 is characterized in that: this admixture is a nitrogen.
3. manufacture method according to claim 1 is characterized in that: the implantation depth of this admixture is implanted energy about 5kev to 10kev by implanting energy control.
4. manufacture method according to claim 1 is characterized in that: the implantation depth of this admixture determines this second thickness of oxide layer.
5. manufacture method according to claim 1 is characterized in that: use BOE to remove this second oxide layer.
6. manufacture method according to claim 1 is characterized in that: first oxidated layer thickness in this first assembly district is greater than first oxidated layer thickness in this second assembly district.
7. manufacture method according to claim 1 is characterized in that: removing this second oxide layer is etching end point with this first oxide layer.
8. the manufacture method of a different-thickness oxide layer, it is characterized in that: this manufacture method comprises the following steps: at least
A., the semiconductor substrate is provided, and this semiconductor-based end, have one first assembly district and one second assembly district;
B. form one first oxide layer in this first assembly district and surface, this second assembly district;
C. provide an admixture to first oxide layer in this first assembly district, on part first oxide layer in the first assembly district, form one second oxide layer, wherein this first oxide layer has different character with this second oxide layer, and this second oxidated layer thickness is less than this first oxidated layer thickness;
D. remove this second oxide layer in this first assembly district, expose this first oxide layer surface, make this surface, first assembly district form the oxide layer of one first thickness, this second assembly district forms the oxide layer of one second thickness.
Repeat b, c and d step, form the different oxide layer of multi-layered thickness.
9. manufacture method according to claim 8 is characterized in that: this admixture is a nitrogen.
10. manufacture method according to claim 8 is characterized in that: the implantation depth of this admixture is implanted energy about 5kev to 10kev by implanting energy control.
11. manufacture method according to claim 8 is characterized in that: use BOE to remove this second oxide layer.
12. manufacture method according to claim 8 is characterized in that: second thickness of this oxide layer is greater than first thickness.
13. manufacture method according to claim 8 is characterized in that: removing this second oxide layer is etching end point with this first oxide layer.
14. manufacture method according to claim 8 is characterized in that: the implantation depth of this admixture determines this second thickness of oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109731 CN1224085C (en) | 2001-03-29 | 2001-03-29 | Method for producing different-thickness oxide layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109731 CN1224085C (en) | 2001-03-29 | 2001-03-29 | Method for producing different-thickness oxide layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1378252A true CN1378252A (en) | 2002-11-06 |
| CN1224085C CN1224085C (en) | 2005-10-19 |
Family
ID=4658109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01109731 Expired - Fee Related CN1224085C (en) | 2001-03-29 | 2001-03-29 | Method for producing different-thickness oxide layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1224085C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433258C (en) * | 2004-02-02 | 2008-11-12 | Atmel德国有限公司 | Process for manufacturing vertically insulated structural components on SOI material of various thickness |
| CN103456613A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2001
- 2001-03-29 CN CN 01109731 patent/CN1224085C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433258C (en) * | 2004-02-02 | 2008-11-12 | Atmel德国有限公司 | Process for manufacturing vertically insulated structural components on SOI material of various thickness |
| CN103456613A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1224085C (en) | 2005-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7091079B2 (en) | Method of forming devices having three different operation voltages | |
| KR0141195B1 (en) | Fabrication method of semiconductor device having low-resistance gate electrod | |
| US5953599A (en) | Method for forming low-voltage CMOS transistors with a thin layer of gate oxide and high-voltage CMOS transistors with a thick layer of gate oxide | |
| US6159799A (en) | Method of manufacturing semiconductor device comprising high voltage regions and floating gates | |
| KR100334979B1 (en) | Semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability and method of manufacturing it | |
| KR100487951B1 (en) | A semiconductor device having self-aligned contact hole and fabrication method thereof | |
| US6157062A (en) | Integrating dual supply voltage by removing the drain extender implant from the high voltage device | |
| US5501997A (en) | Process of fabricating semiconductor devices having lightly-doped drain | |
| CN1224085C (en) | Method for producing different-thickness oxide layer | |
| US6537883B2 (en) | Method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor wafer | |
| KR20040004080A (en) | Semiconductor device and manufacturing method thereof | |
| US7804122B2 (en) | Non-volatile memory | |
| CN1224084C (en) | Method for producing different-thickness grid oxide layer | |
| US7060572B2 (en) | MOSFET with short channel structure and formation method thereof | |
| CN1299362C (en) | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area | |
| US6235566B1 (en) | Two-step silicidation process for fabricating a semiconductor device | |
| CN101552228B (en) | Manufacturing method of semiconductor device | |
| US6806155B1 (en) | Method and system for scaling nonvolatile memory cells | |
| CN101026127A (en) | Process for manufacturing semiconductor element with different voltage tolerance | |
| CN1228817C (en) | Method for producing semiconductor device having double grid oxide layers | |
| KR100407981B1 (en) | Structure of semiconductor device and fabricating method thereof | |
| US20060170040A1 (en) | Semiconductor device, semiconductor integrated circuit device, and semiconductor device fabrication method | |
| CN1430258A (en) | Method of integrated manufacturing high-voltage element and low voltage element | |
| US6110764A (en) | Method of manufacturing an assembly with different types of high-voltage metal-oxide-semiconductor devices | |
| KR100434712B1 (en) | Method of manufacturing soi mos transistor with reduced series resistance between source and drain regions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20051019 |