CN1377085A - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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CN1377085A
CN1377085A CN 01110181 CN01110181A CN1377085A CN 1377085 A CN1377085 A CN 1377085A CN 01110181 CN01110181 CN 01110181 CN 01110181 A CN01110181 A CN 01110181A CN 1377085 A CN1377085 A CN 1377085A
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protection circuit
circuit
source
type semiconductor
semiconductor layer
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CN1130768C (en
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陈伟梵
俞大立
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Winbond Electronics Corp
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Winbond Electronics Corp
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Abstract

The invention relates to an electrostatic discharge protection circuit, which comprises a semiconductor controlled rectifier and a nonvolatile memory. The semiconductor controlled rectifier includes an anode, a cathode and an anode grid, and the anode and the cathode are respectively connected to a first and a second circuit contact. The non-volatile memory comprises a floating gate and a pair of source/drain electrodes, wherein the source/drain electrodes are respectively connected with the cathode and anode grids of the semiconductor control rectifier, and the floating gate has a preset amount of charges so as to reduce the trigger voltage of the semiconductor control rectifier in a negative forward bias mode.

Description

ESD protection circuit
The invention relates to the protection using integrated circuit technology, particularly about a kind of ESD protection circuit, it is suitable for being applied in operating voltage and surpasses in the circuit of supply voltage range.
In the technical field of sub-micron CMOS, static discharge (electrostaticdischarge) effect is one of key factor of estimating good required consideration when bad of integrated circuit reliability.See also the 1st figure, the 1st figure is the profile that is formed on the semiconductor-based end for a known ESD protection circuit, and this ESD protection circuit is a side direction semiconductor controlled rectifier (Lateral Semiconductor Controlled Rectifier).Shown in the 1st figure, label 1 is represented a lsi core circuit (core circuit), under modes of circuit operation, by voltage source V SSAnd V DDRequired power supply is provided; Label 2 is represented a joint sheet (pad), and has a side direction semiconductor control rectifier 3 to be connected to joint sheet 2.Under the situation of static discharge, wish conducting by side direction semiconductor controlled rectifier 3, discharge the ESD stress at joint sheet 2 places, protection core circuit 1 avoids the destruction of static discharge.
See also the 1st figure again, a n type well region 11 is formed at at semiconductor-based the end 10.One p + Doped region 12 is formed in the n type well region 11, as the anode (anode electrode) of side direction semiconductor controlled rectifier 3; And a n +Type doped region 13 is formed in the p type substrate 10, as the negative electrode (cathode electrode) of side direction semiconductor controlled rectifier 3.Moreover, p + Doped region 12 is via a n + Type contact zone 14 couples n type well region 11, n +Type doped region 13 is via a p + Type contact zone 15 couples p N-type semiconductor N substrate 10.
So side direction semiconductor controlled rectifier 3 can be considered and includes two bipolar transistor T1 and T2.As shown in the figure, by p +Type doped region 12, n type well region 11 and p N-type semiconductor N substrate 10 be construction pnp transistor T 1 emitter, base stage and collector electrode respectively, and n type well region 11, the substrate 10 of p N-type semiconductor N and n +Type doped region 13 is collector electrode, base stage and the emitter of construction npn transistor T 2 respectively.And resistance R WellAnd R SubThen represent the spreading resistance (spreading resistance) of n type well region 11 and p N-type semiconductor N substrate 10 respectively.Shown in the 1st figure, n + Type contact zone 14 and p +Type doped region 12 all is connected to joint sheet 2, and n +Type doped region 13 and p + Type contact zone 15 all is connected to V SS(when in the circuit normal running, V SSBe generally earthing potential).
See also the 2nd figure, the 2nd figure is the I-V curve chart of the 1st figure side direction semiconductor controlled rectifier.Figure two is when electrostatic discharge event takes place, V SSAnd V DDPower supply not is floating as yet.Therefore, as with respect to V SSWhen appearing at joint sheet 2 for positive ESD stress, n type well region 11 and p N-type semiconductor N substrate 10 indirect faces are because of avalanche breakdown (avalanchebreakdown), and (this trigger voltage and trigger current are respectively V to trigger side direction semiconductor control rectifier 3 TrigAnd I Trig) conducting electric current release electrostatic discharge stress, be about sustaining voltage V and anode 12 and 13 current potentials of negative electrode are clamped to h, make core circuit 1 avoid static discharge and destroy.As with respect to V SSWhen appearing at joint sheet 2, then be forward bias voltage drop (forward bias), also can protect core circuit 1 to avoid the destruction of static discharge because of n type well region 11 and p N-type semiconductor N substrate 10 indirect faces for negative ESD stress.The I-V curve of this side direction semiconductor controlled rectifier 3 is promptly shown in the 2nd figure.And be approximately 30 to 50 volts (volt) with n type well region 11 and p N-type semiconductor N substrate 10 formed trigger voltages.
See also the 3rd figure and the 4th figure, the 3rd figure is the profile that the ESD protection circuit of known a kind of field oxide edge collapse (avalanche breakdown at field oxide edge) triggering is formed on the semiconductor-based end.The 4th figure is the profile that the ESD protection circuit of known another kind of grid auxiliary (gate-aided breakdown) triggering is formed on the semiconductor-based end.But just triggering 30 to 50 volts the time after all is too high really, and core circuit might just damage before the triggering on the throne, so improving one's methods of similar the 1st figure arranged.Shown in the 3rd figure, added a field oxide 20 among the 3rd figure and followed at the other n of field oxide 20 +Type collapse district 22, because field oxide can be implanted channel stop thing (channelstopper) for 20 times, so n +The edge of type collapse district 22 and field oxide 20 can more early collapse, so trigger the side direction semiconductor controlled rectifier.Shown in the 4th figure, the 4th figure utilizes the source/drain electrode of MOS transistor 24 to have lower breakdown voltage to trigger the side direction semiconductor controlled rectifier ahead of time than adding a last MOS transistor 24 among the 1st figure.And the trigger voltage that the 3rd figure and the 4th figure can reach is approximately 15 to 20 volts.
Yet by said method as can be known, any a kind of structure under the environment of a kind of size and a kind of technology, just can only have a kind of performance.Therefore, the semiconductor controlled rectifier that is applicable to 5V output/input (input/output, I/O) just not necessarily is applicable to 12V output/input.Must redesign, test, just can obtain two kinds of semiconductor controlled rectifiers for two kinds of different demands so expend many costs.
The object of the present invention is to provide a kind of ESD protection circuit that constitutes with non-voltile memory.Electric charge in the suitable adjustment non-voltile memory floating gate just can make semiconductor controlled rectifier produce different trigger voltages, so can utilization widely be arranged according to the demand of actual conditions.
According to above-mentioned purpose, the present invention can finish by a kind of ESD protection circuit.ESD protection circuit includes semiconductor control rectifier, and the anode of semiconductor controlled rectifier and negative electrode are connected to one first and one second circuit contact.ESD protection circuit also comprises a non-voltile memory (non-volatile memory); pair of source/the drain electrode of non-voltile memory is to be connected to the negative electrode of semiconductor controlled rectifier and anode grid; and the electric charge that has scheduled volume in the non-voltile memory floating gate is negative forward bias voltage drop one trigger voltage in order to reduce the semiconductor control rectifier.
Under modes of circuit operation; even if operating voltage surpasses the supply voltage range; after certain limit; non-voltile memory just can produce source/drain leakage (gate induceddrain leakage that grid cause; GIDL); this electric current can reduce the current potential of anode grid, and triggers semiconductor controlled rectifier, protects the normal running of core circuit.
Moreover the present invention also provides a kind of ESD protection circuit, can be implemented in the semiconductor substrate.ESD protection circuit includes a n type semiconductor layer; the n type semiconductor layer has one first contact zone; one p type semiconductor layer; be one with n N-type semiconductor N interlayer and connect face; and the p type semiconductor layer has one second contact zone; and a p type doped region, be arranged in the n type semiconductor layer, with first contact zone with being connected to one first circuit junction.ESD protection circuit also includes a non-voltile memory (non-volatile memory), is arranged in the p type semiconductor layer, includes a floating gate and pair of source/drain electrode.One of source/drain electrode person is connected in the n type semiconductor layer, and non-voltile memory is with the same second circuit contact that is connected in of another person and this second contact zone of source/drain electrode.Wherein, there is the electric charge of scheduled volume in the floating gate, to reduce the trigger voltage that the semiconductor control rectifier is negative forward bias voltage drop.
Once operating voltage surpasses the supply voltage range, after certain limit, source/drain leakage that grid cause just can begin to occur, can reduce the current potential of the n type semiconductor layer that meets the face place on the one hand, on the other hand, because source/drain leakage that grid cause fails to be convened for lack of a quorum through the p type semiconductor layer, so can draw high the current potential of the p type semiconductor layer that meets the face place.The both can trigger semiconductor controlled rectifier, protects the core circuit normal running.
The invention has the advantages that the electric charge in the non-voltile memory floating gate can control, so source/drain leakage that lock causes can be controlled just.So, can make ESD protection circuit of the present invention that utilization widely be arranged according to the demand of actual conditions as long as the electric charge in the floating gate of suitable adjustment non-voltile memory just can make semiconductor controlled rectifier produce different trigger voltages.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below:
Brief Description Of Drawings:
The 1st figure is the profile that a known ESD protection circuit is formed on the semiconductor-based end;
The 2nd figure is the I-V curve chart of the 1st figure side direction semiconductor controlled rectifier;
The 3rd figure is that known a kind of field oxide edge collapse (avalanche breakdown atfield oxide edge) triggers the profile that ESD protection circuit is formed on the semiconductor-based end;
The 4th figure is the profile that the ESD protection circuit of known another kind of grid auxiliary (gate-aided breakdown) triggering is formed on the semiconductor-based end;
The 5th figure is formed on the profile at the semiconductor-based end for ESD protection circuit of the present invention;
The 6th figure is the 5th figure equivalent circuit diagram;
The 7th figure is source/drain leakage flow diagram that grid cause;
The 8th figure is the I-V curve chart of the 5th figure;
The profile at the semiconductor-based end of the 9th figure when to be the present invention with minute grid formula internal memory implement.Symbol description:
28 ~ joint sheet; 29 ~ core circuit; 30 ~ ESD protection circuit; The substrate of 32 ~ p N-type semiconductor N; 34 ~ p +The type contact zone; 36 ~ n type well region; 38 ~ n +The type contact zone; 40 ~ p +The type doped region; 42 ~ n +The type doped region; 44 ~ floating gate; 50 ~ semiconductor controlled rectifier; 52 ~ non-voltile memory; 54 ~ the first source/drain electrodes; 70 ~ control gate.
Embodiment
See also the 5th figure and the 6th figure, the 5th figure is formed on the profile at the semiconductor-based end for ESD protection circuit of the present invention, and the 6th figure is the 5th figure equivalent circuit diagram.The present invention provides a kind of with non-voltile memory formation ESD protection circuit.Label 29 is represented lsi core circuit (core circuit), when under modes of circuit operation, via voltage source V SSAnd V DDRequired power supply is provided.Label 28 is represented joint sheet (pad), and 30 of ESD protection circuits of the present invention are connected to joint sheet 28.When under electrostatic discharge event, can protect core circuit 29 to avoid static discharge and destroy.According to the present invention, ESD protection circuit 30 includes a side direction semiconductor controlled rectifier 50 and a non-voltile memory 52.
ESD protection circuit 30 is made on the semiconductor chip, includes a n type semiconductor layer, as the n type well region (n-well) 36 shown in scheming to go up, and n type well region 36 has one first contact zone, such as the n on the n type well region 36 + Type contact zone 38 is used for making between n type well region 36 and afterwards metal wire (not shown) having excellent electrical property to contact.ESD protection circuit 30 has a p type semiconductor layer in addition; as p N-type semiconductor N substrate (p-sub) 32 on the 5th figure; and 36 of n type well regions are one and connect face (junction), and p N-type semiconductor N substrate 32 has one second contact zone, as the p on p N-type semiconductor N substrate 32 surfaces + Type contact zone 34 is used for making between p N-type semiconductor N substrate 32 and afterwards metal wire (not shown) having excellent electrical property to contact.One p +Type doped region 40 is arranged in the n type well region 36, with n + Type contact zone 38 is with being connected to one first circuit junction, and just joint sheet 28.One n +Type doped region 42 is arranged in the p N-type semiconductor N substrate 32, with p + Type contact zone 34 is with being connected to second circuit contact, just a V SsSo, p +Type doped region 40, n +Type doped region 42, n type well region 36 and p N-type semiconductor N substrate 32 become semiconductor controlled rectifier 50 anodes, negative electrode, the plate grid utmost point and cathode grid respectively.
ESD protection circuit 30 has a non-voltile memory (non-volatilememory) 52 in addition, is arranged in the p N-type semiconductor N substrate 32, includes a floating gate 44 and pair of source/drain electrode.One of source/drain electrode person is connected in n type well region 36, as near the first source/drain electrode 54 that is located among the 5th figure face of connecing.And non-voltile memory 52 is connected in a second circuit contact together with another person of source/drain electrode and second contact zone, and in the 5th figure, another person of source/drain electrode promptly is n +Type doped region 42.And have the scheduled volume electric charge in the floating gate 44, be negative forward bias voltage drop one trigger voltage to reduce semiconductor controlled rectifier 50.
Shown in the 6th figure, side direction semiconductor controlled rectifier 50 can be considered as containing two bipolar transistor T3 and T4.p +Type doped region 40, n +Type doped region 42 and p N-type semiconductor N substrate 32 constitute emitter (emitter), base stage (base) and the collector electrode (collector) of pnp bipolar transistor T3 respectively, and n +Type doped region 42, p N-type semiconductor N substrate 32 and n type well region 36 constitute collector electrode, base stage and the emitter of npn bipolar transistor T4 respectively.Resistance R WellAnd R SubRepresent n type well region 36 and p N-type semiconductor N substrate 32 spreading resistances (spread resistance) respectively.And the pair of source/drain electrode of non-voltile memory 52 is connected to pnp bipolar transistor T3 base stage and bipolar transistor T4 emitter, and non-voltile memory 52 base stages are connected in bipolar transistor T4 base stage.
See also the 7th figure, the 7th figure is source/drain leakage flow diagram that grid cause.In semiconductor subassembly physics (semiconductor device physics), the source/drain leakage (gate induced drain leakage) that has a known physical phenomenon to be referred to as grid to cause.Voltage reduction along with grid 60 above the p type substrate 62 below the grid can extend to source/drain electrode 64, has reduced the minimum range (minimumspace) of exhaustion region (deplete region) simultaneously.When the distance of exhaustion region is little to a certain degree the time, according to quantum-mechanical tunnel effect (tunneling effect), electronics (electron) or hole (hole) just have an opportunity to jump to p type substrate 62 or source/drain electrode 64 and the formation electric current.So, same reason, as long as the number of the electric charge in the floating gate 44 among control the 5th figure and the 6th figure, the grid that just can control non-voltile memory 52 cause the size of source/drain leakage.
As with respect to V SSWhen appearing on the joint sheet 28 for positive ESD stress, electric current can be in regular turn via n + Type contact zone 38, n type well region 36, first source/drain electrode 54, the substrate 32 of p N-type semiconductor N and p + Type contact zone 34 and to V SsWherein from first source/electric current of drain electrode 54 to p N-type semiconductor N substrates 32 is exactly source/drain leakage that grid cause.Along with the increase of ESD stress, when electric current arrived to a certain degree greatly, semiconductor controlled rectifier 50 just can be triggered, and so that ESD stress is discharged, avoided static discharge with protection core circuit 29 and destroyed.
See also the 8th figure, the 8th figure is the I-V curve chart of the 5th figure.As long as control the electric charge in non-voltile memory 52 floating gates 44, just can adjust the trigger voltage of semiconductor controlled rectifier 50, can make the electrostatic discharge protective circuit of different trigger voltages with identical circuit according to the demand on the circuit.Shown in the 8th figure, sequencing mode in the present invention is can be known fast erasable leaves electric charge in the floating gate 44 in, and the electron number in floating gate 44 is many more, and then to cause source/drain leakage to fail to be convened for lack of a quorum big more for grid, then semiconductor controlled rectifier 50 can more early be triggered, so trigger voltage can reduce.
See also the 9th figure, the profile at the semiconductor-based end of the 9th figure when to be the present invention with minute grid formula internal memory implement.Certainly, according to the principle of the invention, non-voltile memory 52 is not limited to pile grid formula internal memory, also can be for one fen grid formula (split gate) internal memory (memory cell), shown in the 9th figure.For the source that allows grid cause/drain leakage touches semiconductor controlled rectifier 50, so be to be connected in second circuit contact, just V near this minute grid formula internal memory control gate source/drain electrode of 70 SSAnd another source/drain electrode just can produce source/drain leakage that grid cause.
After having made ESD protection circuit of the present invention; as long as the chip in semiconductor process flow is selected in (wafer sorting) and the last test (final test); suitable to 52 sequencing of the non-voltile memory in the ESD protection circuit; the electric charge of scheduled volume is left in the floating gate 44; the size of the source/drain leakage that just can control gate causes, the trigger voltage of decision semiconductor controlled rectifier 50.So; if different circuit requirements is arranged; just can obtain different trigger voltages; for example; the ESD protection circuit that is used for output/input (input/output, I/O) of 5V can define trigger voltage about 10V, and the ESD protection circuit that is used for 12V output/input (input/output, I/O) then can define trigger voltage about 18V.Do not need extra design and experiment, saving cost very.
Compared to known ESD protection circuit; ESD protection circuit of the present invention needs only the electric charge in the suitable adjustment non-voltile memory floating gate; just can make semiconductor controlled rectifier produce different trigger voltages; can be according to the demand of actual conditions; make ESD protection circuit of the present invention that utilization widely be arranged, and can save extra design and experimental cost.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly know art technology person; do not breaking away from the spirit and scope of the invention; when can doing a little change and retouching, so protection range of the present invention is when looking claim and being as the criterion in conjunction with specification and the accompanying drawing person of defining.

Claims (11)

1.一种静电放电保护电路，包括：1. An electrostatic discharge protection circuit, comprising: 一半导体控制整流器，包含有一阳极、一阴极以及一阳极栅，而该阳极与该阴极是分别连接于一第一和一第二电路接点；以及a semiconductor controlled rectifier comprising an anode, a cathode and an anode grid, the anode and the cathode being respectively connected to a first and a second circuit contact; and 一非挥发性内存(non-volatile memory)，其包含有一浮动栅以及一对源/漏极，该对源/漏极是分别连接于该半导体控制整流器的阴极与阳极栅，且该浮动栅内存有预定量的电荷，以降低该半导体控制整流器呈负顺向偏压的一触发电压。A non-volatile memory (non-volatile memory), which includes a floating gate and a pair of source/drain, the pair of source/drain is respectively connected to the cathode and anode grid of the semiconductor control rectifier, and the floating gate memory There is a predetermined amount of charge to lower a trigger voltage at which the semiconductor controlled rectifier is negatively forward biased. 2.如权利要求1所述的静电放电保护电路，其中该非挥发性内存是为一分栅式(split gate)内存(memory cell)。2. The electrostatic discharge protection circuit as claimed in claim 1, wherein the non-volatile memory is a split gate memory cell. 3.如权利要求2所述静电放电保护电路，其中较靠近该分栅式内存的控制栅的一源/漏极是连接于该第二电路接点。3. The ESD protection circuit as claimed in claim 2, wherein a source/drain closer to the control gate of the split-gate memory is connected to the second circuit contact. 4.如权利要求1所述的静电放电保护电路，其中该非挥发性内存为一堆栅式(split gate)内存(memory cell)。4. The electrostatic discharge protection circuit as claimed in claim 1, wherein the non-volatile memory is a stack of split gate memory cells. 5.如权利要求1所述的静电放电保护电路，其中该第一电路接点是连接一集成电路接合垫。5. The ESD protection circuit as claimed in claim 1, wherein the first circuit contact is connected to an integrated circuit bonding pad. 6.一种静电放电保护电路，包括：6. An electrostatic discharge protection circuit, comprising: 一n型半导体层，该n型半导体层具有一第一接触区；an n-type semiconductor layer, the n-type semiconductor layer has a first contact region; 一p型半导体层，与该n型半导体层间呈一接面，该p型半导体层具有一第二接触区；A p-type semiconductor layer forms a junction with the n-type semiconductor layer, and the p-type semiconductor layer has a second contact region; 一p型掺杂区，设置于该n型半导体层内，与该第一接触区同连接至一第一电路接点；以及a p-type doped region, disposed in the n-type semiconductor layer, connected to a first circuit contact with the first contact region; and 一非挥发性内存(non-volatile memory)，设置于该p型半导体层内，其包含有一浮动栅以及一对源/漏极，该源/漏极之一者连接该n型半导体层，而该非挥发性内存以源/漏极之另一者以及该第二接触区同连接于一第二电路接点，而该浮动栅内存有预定量的电荷，以降低该半导体控制整流器呈负顺向偏压的一触发电压。A non-volatile memory (non-volatile memory), arranged in the p-type semiconductor layer, which includes a floating gate and a pair of source/drain, one of the source/drain is connected to the n-type semiconductor layer, and The non-volatile memory is connected to a second circuit contact with the other of the source/drain and the second contact region, and the floating gate has a predetermined amount of charge to reduce the negative forward direction of the semiconductor control rectifier. A trigger voltage for the bias. 7.如权利要求6所述的静电放电保护电路，其中该非挥发性内存包含有一基极，且该基极以该p型半导体层所构成。7. The electrostatic discharge protection circuit as claimed in claim 6, wherein the non-volatile memory comprises a base, and the base is formed by the p-type semiconductor layer. 8.如权利要求6所述的静电放电保护电路，其中该非挥发性内存为一分栅式(split gate)内存(memory cell)。8. The electrostatic discharge protection circuit as claimed in claim 6, wherein the non-volatile memory is a split gate memory (memory cell). 9.如权利要求8所述静电放电保护电路，其中较靠近该分栅式内存的控制栅的一源/漏极连接于该第二电路接点。9. The ESD protection circuit as claimed in claim 8, wherein a source/drain closer to the control gate of the split-gate memory is connected to the second circuit contact. 10.如权利要求6所述的静电放电保护电路，其中该非挥发性内存为一堆栅式(split gate)内存(memory cell)。10. The ESD protection circuit as claimed in claim 6, wherein the non-volatile memory is a stack of split gate memory cells. 11.如权利要求6所述的静电放电保护电路，其中该第一电路接点是连接一集成电路接合垫。11. The ESD protection circuit as claimed in claim 6, wherein the first circuit contact is connected to an integrated circuit bonding pad.
CN 01110181 2001-03-28 2001-03-28 Electrostatic discharge protection circuit Expired - Fee Related CN1130768C (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100364089C (en) * 2004-08-27 2008-01-23 联华电子股份有限公司 Substrate-triggered electrostatic protection circuit using triple-well structure
CN106847889A (en) * 2017-02-14 2017-06-13 上海华虹宏力半导体制造有限公司 A kind of adjustable vertical NPN bipolar transistor of base current and its manufacture method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100364089C (en) * 2004-08-27 2008-01-23 联华电子股份有限公司 Substrate-triggered electrostatic protection circuit using triple-well structure
CN106847889A (en) * 2017-02-14 2017-06-13 上海华虹宏力半导体制造有限公司 A kind of adjustable vertical NPN bipolar transistor of base current and its manufacture method
CN106847889B (en) * 2017-02-14 2019-09-17 上海华虹宏力半导体制造有限公司 A kind of adjustable vertical NPN bipolar junction transistor of base current and its manufacturing method

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Granted publication date: 20031210