CN1375765A - Fast large-scale multiplying circuit - Google Patents
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- CN1375765A CN1375765A CN 01107655 CN01107655A CN1375765A CN 1375765 A CN1375765 A CN 1375765A CN 01107655 CN01107655 CN 01107655 CN 01107655 A CN01107655 A CN 01107655A CN 1375765 A CN1375765 A CN 1375765A
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Abstract
The present invention relates to a Montgomery's modular multiplication circuit capable of using integrated circuit to implement great number modular power operation, the binary number length of module is n bit, and is made up by connecting n+2 basic processing units (PE), after the highest bit basic processing unit a trigger D (100) is connected, under the control of clock signal said circuit can make iterative operation, every bit B[i] and M[i] of binary numbers of operands of B and M are parallelly inputted into every basic processing unit PE; and all the bits of binary numbers of operand A are serially-inputted into lowest bit basic processing unit PEO, the tringgering time clock of even basic processing units adopts rising edge effective, and the triggering time clock of odd basic processing units adopts falling edge effective.
Description
The hardware that the present invention relates to computing method is realized the field, relates in particular to that big digital-to-analogue in the RSA cryptographic algorithms is taken advantage of, the hardware circuit implementation of Montgomery Algorithm.
Along with the development of mechanics of communication, the transmission of Information amount is increasing, and the safety problem of information is also more and more important, and especially at commercial field, the security of information transmission, integrality and non repudiation directly have influence on the operating mode and the economic interests of businessman.In the information age, the INTERNET networks development of high-speed computer and globalization, the people that make different regions, the world are exchange message mutually, and the legitimacy of message reference seems and becomes more and more important.Constantly various information encryptions, the decryption technology of development have adapted to the requirement in epoch, and good cryptographic algorithm makes information transmission more reliable, safer, and wherein public key encryption algorithm can better satisfy user's requirement.Up to the present, RSA cryptographic algorithms is most popular public key algorithm, can be used as information encryption and digital signature.
RSA cryptographic algorithms is by R.L.Riverst, the algorithm that A.Shamir, and L.Adleman propose, name with three names.In using the system of this cryptographic algorithm, corresponding three very big bigit M, e and d are generally 512 or 1024, difficult more the cracking of number big more institute information encrypted for each user.Between these three bigits special relation is arranged, wherein M and e are disclosed, and d maintains secrecy, and are preserved by the user, and M is a modulus, and e is an encryption key, and d is a decruption key.When certain user sends information C, utilize encryption key e that should the user, information C is encrypted be sent to this user again, C be a plaintext here, and E is a ciphertext, and ciphering process can be expressed as: E=C
eModM; After the user receives cipher-text information E, use and to recover cleartext information C:C=E to its deciphering decruption key d that should the user
dModM.
As seen, the Montgomery Algorithm that encrypt, decrypting process relates to big number, well-known Montgomery Algorithm can be decomposed into repeatedly modular multiplication, big digital-to-analogue is taken advantage of and can be realized by montgomery modulo multiplication, so montgomery modulo multiplication is the core calculations of RSA cryptographic algorithms, this computing is very complicated, realizes that with software speed is slow, be difficult to satisfy application requirements, adopt hardware approach to realize that the rsa encryption computing can reduce operation time greatly.U.S. Pat 6,061,706 have proposed a kind of Montgomery modular multiplication hardware circuit, be formed by connecting by basic processing unit, under clock signal control, carry out interative computation, but it is long for the Montgomery modular multiplication of n position needs 2n+11 clock period that this circuit is finished mould, and operation time is longer.
The objective of the invention is to propose a kind of new fast large montgomery modulo multiplication computing circuit that operation time, short available integrated circuit was realized.
If the binary number length of required calculating mould is the n position, Montgomery modular multiplication of the present invention is realized circuit, by PE0, PE1, PEn+1 n+2 basic processing unit (PE) altogether is formed by connecting, and also connects a trigger D100 after the most significant digit basic processing unit, carries out interative computation under clock signal control.
The basic processing unit PEi that is in described montgomery modulo multiplication circuit interposition comprises totalizer ADDi, five trigger D and two and door, i=1 here, and 2 ... n; Operand A transfers to a high basic processing unit after through trigger D 105, simultaneously again with operand B[i] with back input summer ADDi; Intermediate parameters Q transfers to high-order PEi+1 through behind the trigger D106, simultaneously again with modulus M[i] with back input summer ADDi; Two carry signal C1[i], C0[i] and operation result P[i], respectively through transferring to totalizer ADDi simultaneously behind the trigger D104,108,107; Totalizer ADDi is two totalizers, the high-order C1[i in the carry] transfer to the high position of totalizer; The input data after the totalizer computing, obtain a result data P[i-1] and two carry data C0[i+1], C1[i+1].
Being in described mould takes advantage of the basic processing unit PE0 of circuit lowest order to comprise totalizer ADD0, three trigger D, three and door and an XOR unit, operand A and operand B[0] Xiang Yuhou again with operation result P[0] behind the XOR unitary operation, produce intermediate parameters Q, intermediate parameters Q input trigger D102, through one the tunnel transferring to high-order basic processing unit PE1, another Lu Zaiyu modulus M[0 behind the trigger D102] with back input summer ADD0; Simultaneously operand A one the tunnel transfers to high-order PE1 after through trigger D101, and one the tunnel with operand B[0] with back input summer ADD0; Operation result P[0] through transferring to totalizer ADD0 behind the trigger D103; Totalizer ADD0 is three input signal additions, produces carry signal C[1] transfer to high-order basic processing unit PE1.
Being in described mould takes advantage of the basic processing unit PEn+1 of circuit most significant digit to comprise totalizer ADDn+1 and three trigger D, two carry signal C1[n+1], C0[n+1] and operation result P[n+1], respectively through transferring to totalizer ADDn+1 simultaneously behind the trigger D109,110,111, totalizer ADDn+1 exports a carry signal Co[n+2 with three input signal additions] and operation result P[n].
These basic processing units PE0, PEi, PEn+1 is connected to form the montgomery modulo multiplication circuit in proper order, operand A, the carry data C0[i of low basic processing unit output], C1[i] and intermediate parameters Q transfer to a high basic processing unit, result data P[i-1 respectively simultaneously] transfer to low basic processing unit as the operation result of this unit; Every B[i of the binary number of operand B, mould M] and M[i] all be the parallel corresponding basic processing unit PEi that imports simultaneously respectively, everybody serial input lowest order basic processing unit PE0 by turn of the binary number of operand A; Intermediate parameters Q produces in lowest order basic processing unit PE0, and operand A and intermediate parameters Q be constantly upwards basic processing unit transmission under clock control; Operand B and mould M import with zero at most significant digit basic processing unit PEn+1; Most significant digit processing unit PEn+1 output carry signal arrives trigger D100 thereafter, and the output of this trigger 100 turns back to processing unit PEn+1 with signal, as operation result P[n+1] input PEn+1.
The above-mentioned triggering clock that is numbered the trigger D in the even number basic processing unit adopts rising edge effective, the triggering clock that is numbered the trigger D in the odd number basic processing unit adopts negative edge effective, effective or the negative edge of the rising edge of the triggering clock of the trigger D100 after the most significant digit basic processing unit is effectively by its position decision, it is equivalent to n+3 processing unit, if n+2 is an even number, then rising edge is effective, if odd number, then negative edge is effective.
The present invention proposes a kind of Montgomery modular multiplication hardware circuit that is formed by connecting by basic processing unit, and in the just anticlockwise longshore current water iteration of the inner employing of basic processing unit, improved arithmetic speed, only just can finish the Montgomery modular multiplication one time with 3n/2+1 clock period.
Below in conjunction with accompanying drawing the present invention is described in further detail:
Fig. 1 is the processing unit block diagram that is used for montgomery modulo multiplication computing circuit lowest order;
Fig. 2 is the processing unit block diagram that is used for montgomery modulo multiplication computing circuit interposition;
Fig. 3 is the processing unit block diagram that is used for montgomery modulo multiplication computing circuit most significant digit;
Fig. 4 is the processing unit internal circuit synoptic diagram of montgomery modulo multiplication computing circuit lowest order as shown in Figure 1;
Fig. 5 is the processing unit internal circuit synoptic diagram of montgomery modulo multiplication computing circuit interposition as shown in Figure 2;
Fig. 6 is the basic processing unit internal circuit synoptic diagram of montgomery modulo multiplication computing circuit most significant digit as shown in Figure 3;
Fig. 7 is that the length of mould is the montgomery modulo multiplication computing circuit structure synoptic diagram of n position;
Fig. 8 is that the length of mould is 3 montgomery modulo multiplication computing circuit structure synoptic diagram.
Below in conjunction with accompanying drawing the present invention is described in further detail.
Montgomery Algorithm such as E=C that the essence that realizes RSA cryptographic algorithms is big number have been mentioned above
eModM, and the mould that mould power process can be decomposed into is repeatedly taken advantage of process: E=(C * C * ... * C) modM, modular multiplication can be realized by the montgomery modulo multiplication computing circuit, computing that montgomery modulo multiplication is finished note do Mont (A, B, M), here A, B is an operand, and M is the mould value, can realize in two steps by the following method as calculating C * CmodM:
P＝Mont(C，C，M)＝C×C×2
-(n+2)modM
Mont(P，2
-2(n+2)，M)＝P×2
-2(n+2)×2
-(n+2)modM＝C×CmodM
So realizing the montgomery modulo multiplication that RSA cryptographic algorithms requires calculates and can reduce:
S=A * B * 2
-(n+2)ModM is wherein: n is an integer;
A is that a is counted in the binary operation of n position
na
N-1A
1
B is that b is counted in the binary operation of n position
nb
N-1B
1
M is a n position scale-of-two modulus, require M＞(A, B).
The hardware of montgomery modulo multiplication realizes adopting usually following algorithm, finishes through n+2 iteration:
1.P＝0
2.for?i＝0?to?n+1?do
Q
PE0＝p[0]A
PE0·B[0]；----------(1)
P＝(P+A[i]·B+Q[i]·M)/2；--------(2)
End
3.Return(P)；
Montgomery modulo multiplication computing circuit of the present invention can be realized above-mentioned algorithm, and (PE) is formed by connecting by a series of processing units.The P here, Q are the computing parameters, Q
PE0Produce by the lowest order processing unit, transmit formation computing parameter Q by turn to a high position; The operation result of each processing unit is P[i] and to the low level transmission, the operation result of lowest order is given up, and has constituted computing parameter P like this.A wherein, B are operands, and M is the mould value.
Fig. 1, Fig. 2, shown in Figure 3 be basic processing unit block diagram in the montgomery modulo multiplication computing circuit, basic processing unit wherein shown in Figure 1 is used for the lowest order of circuit, basic processing unit shown in Figure 3 is used for most significant digit, and basic processing unit shown in Figure 2 is used for interposition.B[i among the figure] and M[i] be the corresponding positions of the binary number of operand B and mould M, B[i] and M[i] the corresponding PE of parallel input unit; Each of the binary number of operand A is transmitted each PE unit of input, the computing of participating from low bit serial input circuit by turn to a high position; Q is the computing parameter, is produced by the lowest order processing unit, transmits each PE unit of input, the computing of participating by turn to a high position; C[i] be the computing parameter that produces by each PE unit, in Fig. 1 and the highest shown in Figure 3, lowest order processing unit, have only one, need a signal line, in the processing unit of interposition shown in Figure 2, have two, need two signal line, they transfer to a high PE unit; After computing, the operation result P[i-1 of i PE unit] transfer to than low level, participate in computing than low level.
The bit arithmetic in the algorithm arithmetic expression (2) is finished in each PE unit:
P[i]=(P[i+1]+A[j] B[i+1]+Q[j] M[i+1])/2 so all PE unit are finished arithmetic expression in the algorithm (2) together.
Fig. 4, Fig. 5 and Fig. 6 are and Fig. 1, Fig. 2 and the corresponding internal circuit diagram of Fig. 3.
Fig. 4 is a lowest order PE unitary operation electrical block diagram, and the circuit in the frame of broken lines is that this unit is distinctive, is used to calculate Q
PE0=p[0] A
PE0B[0], the signal Q of generation
PE0Input trigger 102, the output Q of this trigger 102 transfer to a high PE unit, simultaneously again with M[0] with after transfer to totalizer ADD0; Each serial input trigger D101 of the binary number of operand A, this trigger 101 is imported a high PE unit with operand A, simultaneously again with signal B[0] with transfer to totalizer ADD0; Signal P[0] input trigger D103, the output input summer ADD0 of this trigger 103; Totalizer ADD0 produces carry signal C[1 with three end input signal additions].
Signal A, Q are imported by a low PE unit in Fig. 5, and be high one through transferring to behind the trigger 105,106 respectively, participates in the computing of this PE unit simultaneously; Carry signal by the input of a low PE unit has two: C1[i], C0[i] (in Fig. 2, be expressed as C[i], for ease of explanation, split into two here, a high position is C1[i], low level is C0[i]), pass through trigger D104,108 respectively after, transfer to totalizer ADDi simultaneously; Totalizer ADDi is two totalizers, the high-order C1[i in the carry] transfer to the high position of totalizer; The input data are after the totalizer computing, obtain a result data and two carry data P[i-1], C0[i+1], C1[i+1], the high-order output data C0[i+1 of totalizer wherein] transfer to a high PE unit as carry, the low level of totalizer result data transfers to low PE unit as the operation result of this unit.Circuit structure among Fig. 6 is identical with Fig. 5, but simpler, and wherein operand A, B and mould M are 0, and the parameter Q relevant with mould M also can dispense.
Fig. 7 is the montgomery modulo multiplication circuit structure by above-mentioned algorithm design, because of the length of the mould of computational data is n, then need construct from PE0 to PEn+1 n+2 PE processing unit altogether.In circuit, the clock of the d type flip flop in the even location adopts rising edge effective, and the employing negative edge of odd location is effective.Like this, in a clock period, data are to two of front transfers.Be the data operation of n position for mould length, after n+1 clock period, export first data, again through last position of output after n/2 clock period.In the circuit, M[n-1] ..., M[1], M[0] each bit parallel input of binary number of expression operand modulus, A represents that the every of binary number of operand A imports B[n from the lowest order serial] ..., B[1], B[0] each bit parallel input of binary number of expression operand B; Between processing unit, each unit has three kinds of signals to output to next stage, comprises A, Q, C[i], it is P[i-1 that a kind of signal turns back to upper level]; Operand B and mould M high-order if not enough zero padding.Most significant digit processing unit PEn+1 output carry signal arrives d type flip flop 100 thereafter, and this trigger 100 turns back to processing unit PEn+1 with signal output, as P[n+1] computing parameter signal input PEn+1; Effective or negative edge is effectively by its position decision at rising edge for the clock of this d type flip flop 100, and it is equivalent to n+3 processing unit, is even number as if n+3, and then rising edge is effective, odd number, and then negative edge is effective.
Fig. 8 is that data bit is 3 montgomery modulo multiplication computing circuit embodiment, needs 5 arithmetic elements here, and promptly mould length need be constructed the montgomery modulo multiplication arithmetical unit with n+2 processing unit for the Montgomery modular multiplication of n position.In the montgomery modulo multiplication arithmetical unit, for carry signal C, operand A and intermediate operations variable Q, it is the input that transfers to back one-level processing unit by the output of previous stage processing unit, C[1] and C[5] show that a bars is arranged, other carry has two barss, and its subscript is corresponding to transferring to processing unit PE; And signal P transfers to low one by Gao Yiwei.Operand B and mould M are parallel inputs, and each is corresponding to corresponding processing unit.The not enough zero padding of the operand B of most significant digit processing unit and mould M.Signal A among the figure and Q are imported to the serial of PE4 direction little-endian by PE0.The input of clock signal clk has shown the sequential relationship between each processing unit PE, adjacent processing unit at different clocks along action.The course of action of this circuit: at the rising edge of first clock, processing unit PE0, PE2, PE4 action, first difference of the binary number of operand A, B, M be input processing unit PE0 simultaneously, PE0 produces signal A, Q, C[1], and transfer to PE1; And the input and output of PE2, PE4 are all zero at this moment.Handle unit PE1 and PE3 and trigger 100 actions at the negative edge of first clock, PE1 is with output signal A, Q, the C[1 of PE0] import its inside, also distinguish input processing unit PE1 simultaneously for second of the binary number of operand B, M simultaneously, PE1 produces signal A, Q, C[2], and transfer to PE2, and produce operation result signal P[0 simultaneously] transfer to PE0; And this moment PE3 and trigger D100 input and output be all zero.After the rising edge of second clock arrived, second input PE0 of the binary number of operand A produced the signal A and the Q that point to PE1, and processing unit PE2 is with input signal A, Q and C[2] write its inner d type flip flop, export after the computing; And the input and output of PE4 are all zero at this moment.When negative edge occurs, input signal A, Q and C[1] write processing unit PE1 respectively simultaneously, union is exported A, Q and C[3]; Input signal A, Q and C[3] write processing unit PE3 respectively simultaneously, union is exported C[4]; And the input and output of trigger D100 are all zero at this moment.The computing that iterates like this, first output of operation result behind the 4th the clock negative edge, every result of half clock period output, after 5.5 clock period, computing is finished.
Claims (3)
1. the Montgomery modular multiplication of a large module power multiplication is realized circuit, the binary number length of mould is the n position, (PE) is formed by connecting by basic processing unit, under clock signal control, carry out interative computation, it is characterized in that described montgomery modulo multiplication circuit comprises n+2 basic processing unit, also connects a trigger D (100) after the most significant digit basic processing unit;
The basic processing unit PEi that is in described montgomery modulo multiplication circuit interposition comprises totalizer ADDi, five trigger D and two and door, i=1 here, and 2 ... n; Operand A transfers to a high basic processing unit after through trigger D (105), simultaneously again with operand B[i] with back input summer ADDi; Intermediate parameters Q transfers to high bit after through trigger (106), simultaneously again with operand M[i] with back input summer ADDi; Two carry signal C1[i], C0[i] and operation result P[i], transfer to totalizer ADDi simultaneously after passing through trigger (104,108,107) respectively; Totalizer ADDi is two totalizers, the high-order C1[i in the carry] transfer to the high position of totalizer; The input data after the totalizer computing, obtain a result data P[i-1] and two carry data C0[i], C1[i];
Being in described mould takes advantage of the basic processing unit PE0 of circuit lowest order to comprise totalizer ADD0, three trigger D, three and door and an XOR unit, operand A and operand B[0] Xiang Yuhou the result again with operation result P[0] import the XOR unit respectively simultaneously, behind the XOR unitary operation, produce intermediate parameters Q
PE0And input trigger D (102), through transferring to PE1 after trigger (102), simultaneously again with operand M[0] with back input summer ADD0; Operand A transfers to high-order basic processing unit PE1 after through trigger D (101), simultaneously again with operand B[0] with back input summer ADD0; Operation result P[0] through transferring to totalizer ADD0 behind the trigger D (103); Totalizer ADD0 is three input signal additions, produces carry signal C[1] transfer to high-order basic processing unit PE1;
Being in described mould takes advantage of the basic processing unit PEn+1 of circuit most significant digit to comprise totalizer ADD0 and three trigger D, two carry signal C1[n+1], C0[n+1] and operation result P[n+1], transfer to totalizer ADDn+1 simultaneously after passing through trigger D (109,111,110) respectively, totalizer ADDn+1 is three input signal additions, output carry signal C[n+2] and operation result P[n];
Described basic processing unit PE0, PEi, PEn+1 forms described montgomery modulo multiplication circuit, operand A, the result data P[i of a low basic processing unit PEi] and carry data C0[i], C1[i] and intermediate parameters Q transfer to a high basic processing unit PEi+1, result data P[i respectively simultaneously] transfer to as the operation result of this unit and hang down a basic processing unit PEi-1; Every B[i of the binary number of operand B, M] and M[i] all be the parallel corresponding basic processing unit PEi that imports simultaneously respectively, everybody serial input lowest order basic processing unit PE0 by turn of the binary number of operand A, intermediate parameters Q produces in lowest order basic processing unit PE0, and operand A and intermediate parameters Q be constantly upwards basic processing unit transmission under clock control; Operand B and M import with zero at most significant digit basic processing unit PEn+1; Most significant digit processing unit PEn+1 output carry signal is to thereafter trigger D, and the output of this trigger turns back to processing unit PEn+1 with signal, as P[n+1] the computing parameter imports wherein.
2. the realization circuit of the Montgomery modular multiplication of large module power multiplication according to claim 1, the triggering clock that it is characterized in that the trigger D in the described basic processing unit that is numbered even number adopts rising edge effective, the triggering clock that is numbered the trigger D in the basic processing unit of odd number adopts negative edge effective, the triggering clock of trigger D (100) after the most significant digit basic processing unit is that the effective or negative edge of rising edge is effectively by its position decision, it is equivalent to n+3 processing unit, if n+2 is an even number, then rising edge is effective, if odd number, then negative edge is effective.
3. the realization circuit of the Montgomery modular multiplication of large module power multiplication according to claim 1 is characterized in that this circuit is implemented in the same integrated circuit block.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100437548C (en) * | 2003-10-15 | 2008-11-26 | 微软公司 | Utilizing SIMD instructions within Montgomery multiplication |
| CN102117195A (en) * | 2009-12-30 | 2011-07-06 | 上海华虹集成电路有限责任公司 | Large-number modular multiplier circuit |
| CN1750460B (en) * | 2004-09-16 | 2011-11-16 | 英特尔公司 | Method for performing modular exponentiations |
| CN103605495A (en) * | 2013-10-17 | 2014-02-26 | 陕西万达信息工程有限公司 | Circuit for removing superfluous parts |
| CN103645883A (en) * | 2013-12-18 | 2014-03-19 | 四川卫士通信息安全平台技术有限公司 | FPGA (field programmable gate array) based high-radix modular multiplier |
| CN105573712A (en) * | 2014-10-31 | 2016-05-11 | Arm有限公司 | Apparatus, method and program for calculating the result of a repeating iterative sum |
| CN113032845A (en) * | 2021-03-31 | 2021-06-25 | 郑州信大捷安信息技术股份有限公司 | EdDSA signature implementation method and device for resource-constrained chip |
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2001
- 2001-03-19 CN CN 01107655 patent/CN1375765A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100437548C (en) * | 2003-10-15 | 2008-11-26 | 微软公司 | Utilizing SIMD instructions within Montgomery multiplication |
| CN1750460B (en) * | 2004-09-16 | 2011-11-16 | 英特尔公司 | Method for performing modular exponentiations |
| CN102117195A (en) * | 2009-12-30 | 2011-07-06 | 上海华虹集成电路有限责任公司 | Large-number modular multiplier circuit |
| CN102117195B (en) * | 2009-12-30 | 2013-05-01 | 上海华虹集成电路有限责任公司 | Large-number modular multiplier circuit |
| CN103605495A (en) * | 2013-10-17 | 2014-02-26 | 陕西万达信息工程有限公司 | Circuit for removing superfluous parts |
| CN103605495B (en) * | 2013-10-17 | 2017-07-28 | 陕西万达信息工程有限公司 | One kind is left out the beginning and the end circuit |
| CN103645883A (en) * | 2013-12-18 | 2014-03-19 | 四川卫士通信息安全平台技术有限公司 | FPGA (field programmable gate array) based high-radix modular multiplier |
| CN105573712A (en) * | 2014-10-31 | 2016-05-11 | Arm有限公司 | Apparatus, method and program for calculating the result of a repeating iterative sum |
| CN105573712B (en) * | 2014-10-31 | 2020-09-04 | Arm 有限公司 | Apparatus, method and storage medium for calculating results of iterative sums |
| CN113032845A (en) * | 2021-03-31 | 2021-06-25 | 郑州信大捷安信息技术股份有限公司 | EdDSA signature implementation method and device for resource-constrained chip |
| CN113032845B (en) * | 2021-03-31 | 2022-02-11 | 郑州信大捷安信息技术股份有限公司 | EdDSA signature implementation method and device for resource-constrained chip |
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